JP2002359190A - SEMICONDUCTOR SUBSTRATE AND FIELD EFFECT TRANSISTOR, METHOD FOR FORMING SiGe LAYER, METHOD FOR FORMING STRAINED Si LAYER USING IT AND METHOD FOR MANUFACTURING FIELD EFFECT TRANSISTOR - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate and a field effect transistor, a method for forming an SiGe layer, a method for forming a strained Si layer and a method for manufacturing a field effect transistor in which dislocation density of the SiGe layer is reduced by a method by which restriction on the process and on the degree of freedom in the placement of device design is suppressed. SOLUTION: The semiconductor substrate comprises an SiGe layer SG formed on an Si substrate 1 and a region 1a having a higher impurity concentration than other region is patterned on the surface of the Si substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-speed MOSFET
The present invention relates to a method for forming a SiGe layer suitable for forming a semiconductor substrate, a field effect transistor, a strained Si layer, and the like used for the like, a method for forming a strained Si layer using the same, and a method for manufacturing a field effect transistor.

[0002]

2. Description of the Related Art In recent years, SiG (SiG)
High-speed M using a strained Si layer epitaxially grown through an e (silicon-germanium) layer for the channel region
OSFET, MODFET and HEMT have been proposed. In this strained Si-FET, tensile strain occurs in the Si layer due to SiGe having a larger lattice constant than Si,
For this reason, the band structure of Si is changed, the degeneracy is released, and the carrier mobility is increased. Therefore, by using this strained Si layer as a channel region, it is possible to increase the speed by about 1.5 to 8 times the normal speed. Further, a normal Si substrate by the CZ method can be used as a substrate as a process, and a high-speed CMOS can be realized by a conventional CMOS process.

However, in order to epitaxially grow the strained Si layer required as a channel region of the FET, it is necessary to epitaxially grow a high-quality SiGe layer on a Si substrate. However, due to the difference in lattice constant between Si and SiGe, There was a problem in crystallinity due to dislocations and the like. For this purpose, the following various proposals have conventionally been made.

For example, a method using a buffer layer in which the Ge composition ratio of SiGe is changed at a constant gentle slope, a method using a buffer layer in which the Ge (germanium) composition ratio is changed stepwise (stepwise), a Ge composition A method using a buffer layer whose ratio is changed in a superlattice shape, a method using a buffer layer whose Ge composition ratio is changed at a constant gradient using an off-cut wafer of Si, and the like have been proposed (USPate).
nt 5,442,205, USPatent 5,221,413, PCT WO98 / 0085
7, JP-A-6-252046).

[0005] US Patent 5,285,086, US Patent
No. 5,158,907 proposes a technique in which an SiO ₂ film or the like on a Si substrate is patterned to form a restricted region which is selectively removed, and a SiGe layer is selectively formed only in the restricted region. According to this technique, the dislocation moving in the SiGe layer is trapped at the side of the restricted region by preventing the dislocation from reaching the surface by setting the SiGe layer in the restricted region to have a constant thickness and area.

[0006]

However, the above-mentioned conventional technique has the following problems. That is, in the above-described conventional technique, the threading dislocation density on the wafer surface is still high, and there is a further demand for a reduction in threading dislocation in order to prevent a malfunction of the transistor. In particular, in the technique of forming a SiGe layer only in the above-described restricted region, the SiGe layer is formed only in the restricted region having a thickness of about the SiGe film. As a technology, selective growth with a high film formation rate and a low film formation rate is required, so that there is an inconvenience that restrictions on processes are large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to reduce the threading dislocation density of a SiGe layer and to further reduce the restrictions on process and the degree of freedom in device design. Transistor, method of forming SiGe layer, and strained Si using the same
It is an object to provide a method for forming a layer and a method for manufacturing a field-effect transistor.

[0008]

The present invention has the following features to attain the object mentioned above. That is, the semiconductor substrate of the present invention comprises a Si substrate and SiGe on the Si substrate.
A high-concentration region having a higher impurity concentration than other regions is formed in a pattern on the surface of the Si substrate. The method of forming a SiGe layer according to the present invention is a method of forming a SiGe layer on a Si substrate, wherein a high-concentration region having a higher impurity concentration than other regions is formed in a pattern on the surface of the Si substrate. It is characterized by having a process. Further, a semiconductor substrate of the present invention is a semiconductor substrate in which a SiGe layer is formed on a Si substrate, wherein the SiGe layer is formed by the above-described method of forming a SiGe layer of the present invention.

In these methods of forming a semiconductor substrate and a SiGe layer, a high-concentration region having a higher impurity concentration than other regions is formed in a pattern on the surface of the Si substrate. Are induced or trapped or terminated by local distortion or lattice defects, thereby reducing threading dislocations on the surface of the SiGe layer and reducing surface roughness due to so-called cross hatching. More specifically, near the dopant atoms in the high-concentration region, there are local distortions of atom arrangement, point defects, cluster-like defects or precipitation, and dislocations such as misfit dislocations generated during film formation are high. It is more likely to occur on the concentration region side, and the occurrence of dislocations on the surface of the SiGe layer is reduced. In addition, the generated dislocations easily move toward the high concentration region side, are easily captured or terminated by local strain or defects near the dopant atoms, and the number of dislocations that appear on the outermost surface of the SiGe layer and become threading dislocations is reduced. In particular, since the high-concentration region is formed in a pattern, the threading dislocation density and the surface roughness decrease in regions other than the high-concentration region. In addition, since the SiGe layer is uniformly formed on the flat Si substrate surface, an advanced and low-speed film forming technique such as the selective growth of the related art is not required.

The method of forming a semiconductor substrate and a SiGe layer according to the present invention employs a technique of forming the high concentration region by ion implantation of the impurity. In other words, in the method of forming the semiconductor substrate and the SiGe layer, the high concentration region is formed by ion implantation of impurities, so that defects and the like caused by ion implantation also induce, capture or terminate dislocations. The density can be reduced, and a high-density region having a predetermined pattern can be easily and accurately obtained.

In the semiconductor substrate according to the present invention, it is preferable that the high-concentration region is adjacent to a device region where a semiconductor element is formed. In the method of forming a SiGe layer according to the present invention, it is preferable that the high concentration region is formed adjacent to a device region where a semiconductor element is formed.

According to the method of forming the semiconductor substrate and the SiGe layer, since the high concentration region is provided at a position adjacent to the device region where the semiconductor element is formed, dislocation can be induced on the high concentration region side. Further, dislocations generated in the SiGe layer in the device region can be efficiently captured in the high concentration region.

In the semiconductor substrate according to the present invention, it is preferable that the high-concentration region is arranged in a cut-off portion for cutting and separating a semiconductor chip having the device region into a chip size. In the method of forming a SiGe layer according to the present invention, it is preferable that the high-concentration region is formed in a cut-off portion for cutting and separating a semiconductor chip having the device region into a chip size.

In the method of forming the semiconductor substrate and the SiGe layer, the high-concentration region is provided in the cut-off portion for cutting and separating the semiconductor chip having the device region into a chip size. Since the concentration region can be formed, there is no waste in device fabrication, and there is no restriction on circuit design.

In the semiconductor substrate of the present invention, it is preferable that the high-concentration region is formed in a substantially lattice shape in which a plurality of cross-shaped patterns are arranged vertically and horizontally corresponding to the cut-off portions. Further, it is preferable that the arrangement direction of the cross-shaped pattern is oblique to the <110> direction of the crystal orientation on the surface of the Si substrate. Further, the method for forming a SiGe layer of the present invention includes:
It is preferable that the high-density region is formed in a substantially lattice shape in which a plurality of cross-shaped patterns are arranged vertically and horizontally corresponding to the cut-away portions. Further, it is preferable that the arrangement direction of the cross pattern is oblique to the <110> direction of the crystal orientation on the surface of the Si substrate.

According to the method of forming the semiconductor substrate and the SiGe layer, a rectangular device region can be obtained inside the cross-shaped pattern, so that no waste occurs in device fabrication and no restriction is imposed on circuit design. . Further, the arrangement direction of the cross-shaped pattern is such that the crystal orientation <1 on the Si substrate surface.
10>, the dislocation is mainly <11
Since it extends in the 0> direction, dislocations running in the openings between adjacent cross-shaped patterns can easily reach the high-concentration regions of the cross-shaped patterns, and the influence of the openings can be reduced.

In the semiconductor substrate according to the present invention, it is preferable that the SiGe layer has, at least in part, a gradient composition region in which the Ge composition ratio gradually increases toward the surface. In the method of forming a SiGe layer according to the present invention, it is preferable that a gradient composition region in which a Ge composition ratio is gradually increased toward a surface is formed in at least a part of the SiGe layer.

In the method of forming the semiconductor substrate and the SiGe layer, at least a part of the SiGe layer is formed as a gradient composition region in which the Ge composition ratio is gradually increased toward the surface. Gradually increases, the density of dislocations can be suppressed, particularly on the surface side in the SiGe layer, and the dislocations can easily extend in the direction along the SiGe layer and easily reach the high concentration region, so that the dislocations can be trapped more. Alternatively, it can be terminated.

The semiconductor substrate according to the present invention is characterized in that the semiconductor substrate according to the present invention has a strained Si layer disposed directly on the SiGe layer or via another SiGe layer. The method of forming a strained Si layer of the present invention is a method of forming a strained Si layer on a Si substrate via a SiGe layer, wherein the SiGe layer on the Si substrate is
It is characterized by being formed by an iGe layer forming method.
The semiconductor substrate of the present invention is a semiconductor substrate in which a strained Si layer is formed on a Si substrate via a SiGe layer, and the strained Si layer is formed by the above-described method of forming a strained Si layer of the present invention. It is characterized by.

In the above-mentioned semiconductor substrate, the semiconductor substrate of the present invention is provided with a strained Si layer disposed directly or via another SiGe layer on the SiGe layer. The upper SiGe layer is formed by the above-described method of forming a SiGe layer of the present invention, and the semiconductor substrate is formed by forming a strained Si layer by the above-described method of forming a strained Si layer of the present invention. It is suitable as a strained Si layer for an integrated circuit using a MOSFET or the like having a layer as a channel region or a semiconductor substrate.

The field-effect transistor according to the present invention comprises Si
A field effect transistor having a channel region in a strained Si layer on a Ge layer, wherein the strained Si layer of the semiconductor substrate according to the present invention has the channel region. Further, the method of manufacturing a field effect transistor according to the present invention provides a method for manufacturing a strained S epitaxially grown on a SiGe layer.
A method for manufacturing a field-effect transistor in which a channel region is formed in an i-layer, wherein the strained Si layer is formed by the method for forming a strained Si layer according to the present invention. Further, the field-effect transistor of the present invention is formed of SiG
a field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on the e layer,
According to the method for forming a strained Si layer of the present invention, the strained Si
It is characterized in that a layer is formed.

The strained Si layer of the semiconductor substrate of the present invention has the channel region in the strained Si layer. In the field effect transistor, the strained Si layer is formed by the method of forming a strained Si layer of the present invention. In the method for manufacturing a field-effect transistor, the strained Si layer is formed by the method for forming a strained Si layer according to the present invention. Thus, a high-quality field-effect transistor can be obtained with a high yield by using a high-quality strained Si layer. it can.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment according to the present invention will be described below with reference to FIGS.

FIGS. 1 and 2 show the cross-sectional structures of a semiconductor wafer (semiconductor substrate) W0 of the present invention and a semiconductor wafer (semiconductor substrate) W having a strained Si layer. The structure of a semiconductor wafer having a layer will be described together with its manufacturing process. As shown in FIG. 1A, a mask M (for example, a resist or the like) having a predetermined pattern on the surface of a Si substrate 1 is provided.
And a plurality of patterned high-concentration regions 1 are formed on the surface of the Si substrate 1 by ion-implanting impurities from above.
a is formed. That is, the mask M
The impurity is added only to the opening portion, and a high concentration region 1a having a higher impurity concentration than other regions (device region 1b) is formed.

As shown in FIG. 3, the high-concentration region 1a formed by patterning is adjacent to a device region 1b where a semiconductor element is formed, and cuts and separates a semiconductor chip having the device region 1b into a chip size. (A so-called scribe line, which is a hatched area in FIG. 3). That is, the width of the high concentration region 1a is determined by, for example, the blade width of the dicing saw. The width of the device region 1b is determined in consideration of the chip size and an appropriate width at which the effects of the present invention can be obtained. The high-concentration region 1a is formed in a substantially lattice shape in which a plurality of cross-shaped patterns are arranged vertically and horizontally corresponding to the cut-away portion, and the arrangement direction of the cross-shaped pattern is the <110> crystal orientation of the surface of the Si substrate 1. It is oblique to (in the direction of the arrow in FIG. 3), and is arranged, for example, at 45 °.

The high-concentration region 1a preferably has an impurity concentration within a range of 1 × 10 ¹⁸ / cm ³ or more and 1 × 10 ²¹ / cm ³ or less, and a dopant such as B
(Boron), C (carbon), N (nitrogen), Al (aluminum), P (phosphorus), Ga (gallium), As (arsenic), In (indium), Sn (tin), Sb (antimony), Tl (Thallium), Pb (lead), Bi (bismuth) and combinations thereof are added. In addition, as exemplified above, the element to be doped can be arbitrarily selected regardless of its conductivity. In particular, since the doping is performed not on the surface layer but on the Si substrate 1, the influence of the conductivity of the impurity on the device characteristics is obtained. Less is.

Next, on the ion-implanted Si substrate 1,
As shown in FIG. 1B, FIGS. 2 and 4, the first composition layer is a gradient composition layer in which the Ge composition ratio x gradually increases from 0 to 0.3 with a gradient (toward the surface) in the film forming direction. SiGe
The layer 2 is epitaxially grown by a low pressure CVD method. Note that the film formation by the low pressure CVD method uses H ₂ as a carrier gas and SiH ₄ and GeH ₄ as a source gas.

Next, the first SGe layer is formed on the first SiGe layer 2.
At the final Ge composition ratio (0.3) of the iGe layer 2, the second SiGe layer 3, which is a constant composition layer and a relaxation layer, is epitaxially grown to manufacture the semiconductor wafer W0. These first SiGe layer 2 and second SiGe layer 3
It functions as a SiGe layer SG for forming a layer. Since the second SiGe layer 3 having a constant composition is formed after the first SiGe layer 2 having the gradient composition is formed as described above, the generation and growth of dislocations in the second SiGe layer 3 are suppressed. As a result, the dislocation density on the surface of the final second SiGe layer 3 can be reduced.

At this time, dislocations DL such as misfit dislocations generated during the formation of the SiGe layer SG extend along the layer direction of the SiGe layer SG during the film formation as shown in FIG. At the same time as reaching the upper portion 1a, it is trapped or terminated by local distortion near the dopant atom or near the defect in the high concentration region 1a, a point defect, or the like. Thereafter, Si is epitaxially grown on the second SiGe layer 3 of the semiconductor wafer W0 to form a strained Si layer 4,
A semiconductor wafer W having a strained Si layer is manufactured. The thickness of each layer is, for example, 1.
5 μm, second SiGe layer 3 is 0.75 μm, strained Si
Layer 4 is 15-22 nm.

As described above, in the present embodiment, the Si substrate 1
Since a high-concentration region 1a having a higher impurity concentration than other regions is formed in a pattern on the surface, dislocations are induced, trapped, or terminated by local distortion or lattice defects in the high-concentration region 1a, and the SiGe layer is formed. The threading dislocations on the surface can be reduced, and the surface roughness due to a so-called cross hatch or the like also decreases. In addition, since the SiGe layer SG is uniformly formed on the flat surface of the Si substrate 1, an advanced and low-speed film forming technique such as the selective growth of the related art is not required.

Further, the first SiG which is a gradient composition region
Since the Ge composition ratio in the e-layer 2 gradually increases, the density of dislocations in the layer can be suppressed, and the dislocations DL can easily move in the direction along the first SiGe layer 2, and the higher concentration region The dislocation DL can be captured by 1a. Further, since the high-concentration region 1a is arranged in a cut-off portion for cutting and separating a semiconductor chip having the device region 1b into a chip size, it is possible to form a region where impurities are high in concentration without any trouble in the device region 1b. No waste occurs in device fabrication, and no restrictions are imposed on circuit design.

The width of the device region 1b is determined in consideration of the chip size and an appropriate width at which the effects of the present invention can be obtained. In addition, the arrangement direction of the high-concentration regions 1a composed of a plurality of cross-shaped patterns is such that the crystal orientation of the surface of the Si substrate 1 is <11.
0> direction, the dislocation is mainly <110
, The dislocations running in the gap portion (non-ion-implanted portion) 1c between adjacent cross-shaped patterns (high-concentration regions 1a) easily reach the high-concentration region 1a, and the influence of the gap portion 1c is reduced. can do.

Next, a field effect transistor (MO) using the semiconductor wafer W having the strained Si layer according to the present invention will be described.
SFET) will be described together with its manufacturing process with reference to FIG.

FIG. 6 shows a schematic structure of a field-effect transistor of the present invention. In order to manufacture this field-effect transistor, a strained Si layer manufactured in the above-described manufacturing process was provided. A gate oxide film 5 of SiO ₂ and a gate polysilicon film 6 are sequentially deposited on the strained Si layer 4 on the surface of the semiconductor wafer W. Then, a gate electrode (not shown) is formed by patterning on the gate polysilicon film 6 on a portion to be a channel region.

Next, the gate oxide film 5 is also patterned to remove portions other than those below the gate electrode. Further, an n-type or p-type source region S and a drain region D are formed in the strained Si layer 4 and the second SiGe layer 3 in a self-aligned manner by ion implantation using the gate electrode as a mask. Thereafter, a source electrode and a drain electrode (not shown) are formed on the source region S and the drain region D, respectively.
n-type or p-type MOSF in which i-layer 4 becomes a channel region
An ET is manufactured.

In the MOSFET thus manufactured,
Since a channel region is formed in the strained Si layer 4 of the semiconductor wafer W having the strained Si layer manufactured by the above-described manufacturing method,
MOSFE with excellent operation characteristics due to high quality strained Si layer 4
T can be obtained with a high yield.

The technical scope of the present invention is not limited to the above embodiment, and various changes can be made without departing from the spirit of the present invention. For example, in the above embodiment, a high concentration region is formed by adding an impurity by ion implantation, but a high concentration region may be formed by another doping means (for example, an impurity introduction method using a diffusion source). Absent. As described above, according to the ion implantation, a defect occurs in the crystal at the time of implantation, and this defect can also capture or terminate dislocations in the SiGe layer, so that the dislocation density can be further reduced. Further, the present invention includes a semiconductor wafer further provided with a SiGe layer on the strained Si layer of the semiconductor wafer W having the strained Si layer of the above embodiment. Further, although the strained Si layer was formed directly on the second SiGe layer, another SiGe layer was further formed on the second SiGe layer, and the strained Si layer was formed via the SiGe layer.
The i-layer may be epitaxially grown.

In the above embodiment, a semiconductor wafer having a SiGe layer is manufactured as a substrate for a MOSFET. However, the semiconductor wafer may be used for other purposes. For example, the method for forming a SiGe layer and the semiconductor substrate of the present invention may be applied to a substrate for a solar cell. That is, the SiG of the gradient composition layer in which the Ge composition ratio is gradually increased on the Si substrate of the above-described embodiment so as to be 100% Ge at the outermost surface.
A solar cell substrate may be manufactured by forming an e-layer and further forming GaAs (gallium arsenide) thereon. In this case, a high-performance solar cell substrate having a low dislocation density can be obtained.

[0039]

According to the present invention, the following effects can be obtained.
According to the method for forming a semiconductor substrate and a SiGe layer of the present invention, a high-concentration region having a higher impurity concentration than other regions is formed in a pattern on the surface of a Si substrate. Is induced, trapped, or terminated by the local distortion or defect, and threading dislocations in the surface region can be reduced, and the surface roughness due to cross hatching or the like can also be reduced. In particular,
If a region other than the high-concentration region is used as a device region, a device having high characteristics can be obtained at a high yield in a region where the threading dislocation density and the surface roughness are further improved. In addition, since the SiGe layer is uniformly formed on the flat Si substrate surface, a high-speed and low-speed film forming technique such as selective growth is not required, so that the yield can be improved and the manufacturing cost can be reduced.

According to the semiconductor substrate provided with the strained Si layer and the method of forming the strained Si layer of the present invention, the Si substrate having the SiGe layer is the semiconductor substrate of the present invention, and the SiGe layer on the Si substrate is provided. Is formed by the above-described method for forming a SiGe layer of the present invention, so that Si
A Si layer can be formed on the Ge layer, and a high-quality strained Si layer can be formed.

According to the field effect transistor of the present invention and the method of manufacturing the field effect transistor, a channel region is formed in the strained Si layer of the semiconductor substrate of the present invention, and the strained Si layer of the present invention is formed. Since the strained Si layer serving as the channel region is formed by the formation method described above, a high-performance MOSFET can be obtained with a high yield by using a high-quality strained Si layer.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a semiconductor substrate according to an embodiment of the present invention in the order of manufacturing steps.

FIG. 2 is an enlarged cross-sectional view of a main part showing a semiconductor substrate provided with a strained Si layer in one embodiment according to the present invention.

FIG. 3 is a plan view of a main part showing a semiconductor substrate in one embodiment according to the present invention.

FIG. 4 is a graph showing a Ge composition ratio with respect to a film thickness of a semiconductor substrate having a strained Si layer according to one embodiment of the present invention.

FIG. 5 is a conceptual diagram in a main part cross section for explaining dislocation in one embodiment according to the present invention.

FIG. 6 shows a MOSFET according to an embodiment of the present invention.
It is a schematic sectional drawing which shows T.

[Explanation of symbols]

Reference Signs List 1 Si substrate 1a High concentration region 1b Device region 2 First SiGe layer 3 Second SiGe layer 4 Strained Si layer 5 SiO ₂ Gate oxide film 6 Gate polysilicon film S Source region D Drain region DL Dislocation SG SiGe layer M Mask W Semiconductor wafer provided with strained Si layer (semiconductor substrate) W0 Semiconductor wafer (semiconductor substrate)

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H01L 31/04 H01L 31/04 HF term (reference) 5F045 AA06 AB01 AB02 AC01 AF03 BB12 CA05 CA07 DA53 DA58 HA05 5F051 AA08 CB19 DA12 GA04 GA20 5F052 CA00 DA01 DA05 DA10 DB02 EA15 JA01 5F140 AA00 AA01 AC28 BA01 BA05 BA16 BA20 BB13 BC12 BC19 BF01 BF04 BK13 CD02 CD06

Claims (20)

[Claims] 1. A semiconductor device comprising: a Si substrate; and a SiGe layer on the Si substrate, wherein a high-concentration region having a higher impurity concentration than other regions is formed in a pattern on the surface of the Si substrate. Semiconductor substrate. 2. The semiconductor substrate according to claim 1, wherein the high-concentration region is adjacent to a device region where a semiconductor element is formed. 3. The semiconductor substrate according to claim 2, wherein the high-concentration region is provided in a cut-off portion for cutting and separating a semiconductor chip having the device region into a chip size. Semiconductor substrate. 4. The semiconductor substrate according to claim 1, wherein the high-concentration region is formed in a substantially lattice shape in which a plurality of cross-shaped patterns are arranged vertically and horizontally corresponding to the cut-away portion. A semiconductor substrate. 5. The semiconductor substrate according to claim 4, wherein an arrangement direction of the cross pattern is oblique to a crystal orientation <110> direction on a surface of the Si substrate. 6. The semiconductor substrate according to claim 1, wherein the SiGe layer has, at least in part, a gradient composition region in which a Ge composition ratio gradually increases toward a surface. Semiconductor substrate. 7. A semiconductor substrate according to claim 1, further comprising a strained Si layer disposed directly or via another SiGe layer on the SiGe layer of the semiconductor substrate according to claim 1. . 8. A field effect transistor having a channel region in a strained Si layer on a SiGe layer, wherein the field region has the channel region in the strained Si layer of the semiconductor substrate according to claim 7. Effect type transistor. 9. A method for epitaxially growing a SiGe layer on a Si substrate, comprising a step of forming a high-concentration region having a higher impurity concentration than another region in a pattern on the surface of the Si substrate. Forming a SiGe layer. 10. The method for forming a SiGe layer according to claim 9, wherein the formation of the high concentration region is performed by ion implantation of the impurity. 11. The method for forming a SiGe layer according to claim 9, wherein the high concentration region is formed adjacent to a device region where a semiconductor element is formed. Formation method. 12. The method for forming a SiGe layer according to claim 11, wherein the high-concentration region is formed in a cut-off portion for cutting and separating a semiconductor chip having the device region into a chip size. Method for forming a SiGe layer. 13. The method of forming a SiGe layer according to claim 12, wherein the high-concentration region is formed in a substantially lattice shape in which a plurality of cross-shaped patterns are arranged vertically and horizontally corresponding to the cut-away portion. Forming a SiGe layer. 14. The SiGe layer forming method according to claim 13, wherein an arrangement direction of the cross pattern is oblique to a crystal orientation <110> direction of the surface of the Si substrate. The method of forming the layer. 15. The method for forming a SiGe layer according to claim 9, wherein a gradient composition region in which a Ge composition ratio is gradually increased toward a surface is formed in at least a part of the SiGe layer. A method for forming a SiGe layer, comprising: 16. A method for forming a strained Si layer on a Si substrate via a SiGe layer, wherein the SiGe layer on the Si substrate is formed by the method according to claim 9. A method for forming a strained Si layer, characterized in that the film is formed by: 17. A method for manufacturing a field-effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, wherein the strained Si layer is formed by the method for forming a strained Si layer according to claim 16. Forming a field effect transistor. 18. A semiconductor substrate having a SiGe layer formed on a Si substrate, wherein the SiGe layer is formed by the method of forming a SiGe layer according to claim 9. Description: Semiconductor substrate. 19. A semiconductor substrate having a strained Si layer formed on a Si substrate via a SiGe layer, wherein the strained Si layer is formed by the method for forming a strained Si layer according to claim 16. A semiconductor substrate characterized by the above-mentioned. 20. A field effect transistor in which a channel region is formed in a strained Si layer epitaxially grown on a SiGe layer, wherein the strained Si layer is formed by the method for forming a strained Si layer according to claim 16. A field-effect transistor.