JPH0384960A - Semiconductor device - Google Patents

Abstract

PURPOSE:To insulate discrete elements from a Ge substrate and to prevent a mutual interference effect and a latch-up phenomenon by a method wherein a semiinsulating chromium-doped gallium arsenide layer, a p-type or n-type germanium layer and a semiconductor element are formed on the germanium substrate. CONSTITUTION:A Cr-doped GaAs layer 2 and a p-type Ge layer 3 are pil one after another from the of a Ga substrate 1 by MBE. Since the Cr-doped GaAs layer 2 is semiinsulating and its lattice constant is close to that of Ge, a crystal defect due to a mismatched lattice is produced little. Then, an n-type well 6 is formed in the p-type Ge layer 3 by implanting ions. Then, gate insulating films 4a, 4b and gate electrodes 5a, 5b are formed; p-type source-drain regions 7 are formed inside the n-well 6; n-type source-drain regions 8 are formed in the p-type Ge layer 3 adjacent to it; a p-channel MIS transistor and an n-channel MIS transistor are formed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Conventional technology]

FIG. 2 is a sectional view of an example of a conventional complementary MIS transistor. A p-type Ge layer 3 is epitaxially grown on a Ge substrate 1. An n-well 6 is selectively formed in this p-type Ge layer 3. Next, a gate insulating film 4a is formed in the n-well 6.
, a gate electrode 5a, and a p-type source/drain region 7 to form a p-channel MIS transistor. On the p-type Ge layer 3 next to it, a gate insulating film 4b, a gate electrode 5b, an n
An n-channel M/S transistor consisting of type source/drain regions 8 is formed. Regarding the Ge gate insulating film,
For example, J, J, Rosenberg (J, J, R
IEEE Electron Device Letters (IEEE E
electronDevice Letters) No. 9
As described in Vol., No. 12, pp. 639 onwards, good MIS can be achieved by using a Ge nitride film or oxynitride film instead of the gate oxide film when forming an OMO3) transistor on a Si substrate. ) A transistor can be manufactured.

[Problem to be solved by the invention]

As mentioned above, a semiconductor substrate made only of Ge
Since there is no semi-insulating substrate such as doped GaAs or Fe-doped InP, a latch-up phenomenon occurs due to parasitic thyristors and parasitic transistors, as described in, for example, LSI Handbook, edited by the Institute of Electronics and Communication Engineers, page 402. To explain with FIG. 2, the p-type source/drain region 7
A parasitic pnpn thyristor is formed by the n-well 6, the p-type Ge substrate 1, and the n-type source/drain region 8. In order to avoid this, there is a drawback that an extremely complicated process such as trench isolation is required as described on page 132 of the LSI handbook.

[Means to solve the problem]

A semiconductor device of the present invention includes a germanium substrate, a semi-insulating chromium-doped gallium arsenide layer formed on the germanium substrate, a p-type or n-type germanium layer formed on the chromium-doped gallium arsenide layer, and the germanium layer. and a semiconductor element formed in.

[Effect]

It is known that Cr-doped GaAs has high resistance.

Regarding the heterojunction of Ge and GaAs, for example,
・K. Jadas (D, K.

IE Transactions on Electron Devices (IEE) by Jadus et al.
E Transactionson Electr
on Devices), Vol. ED-16, No. 1, p. 102, and by Yochu et al.
ou r-nal of Crystal
As described in Vol. 95, page 421 onwards, epitaxial growth with good crystallinity can be achieved by using the molecular beam epitaxial method (MBE method). Therefore, by growing semi-insulating GaAs on a Ge substrate, and then growing a Ge layer on top of it, and building elements within this Ge layer, each element is insulated from the Ge substrate, thereby preventing mutual interference effects and latch-up. The phenomenon does not occur.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of one embodiment of the present invention.

As shown in FIG. 1, C was deposited on the Ge substrate 1 by MBE.
An r-doped GaAs layer 2 and a p-type Ge layer 3 are sequentially laminated. The Cr-doped GaAs layer 2 is semi-insulating and has a lattice constant close to that of Ge, so it is suitable because there are few crystal defects caused by lattice mismatch. Forming Well 6 Next, gate insulating films 4a, 4b and gate electrodes 5a, 5b are formed by a conventional method, and p-type source/drain regions 7,
An n-type source/drain region 8 is formed in the adjacent p-type Ge layer 3 to form p- and n-channel MIS transistors. Here, the n-channel MIS transistor region and the p-channel MIS transistor region were separated using a reactive ion etching method using CF4 gas. Since the etching ratio between Ge and GaAs can be large in this region, it is possible to etch only the region where electrons travel.

In the above embodiment, a complementary MIS transistor is formed in the p-type Ge layer 3, but a bipolar transistor, a diode, a resistor, etc. may also be formed.

〔Effect of the invention〕

According to the present invention, it is possible to obtain the effect that it is extremely easy to manufacture a semiconductor device without mutual interference effects or latch-up phenomena.

[Brief explanation of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a conventional complementary type M-S transistor. 1.-G e substrate, 2-Cr-doped GaAs layer, 3.
p-type Ge layer, 4a, 4b...gate insulating film, 5a. 5b...gate electrode, 6...n well, 7...p
type sole/drain region, 8...n type source/drain region.

Claims (1)

[Claims] a germanium substrate, a semi-insulating chromium-doped gallium arsenide layer formed on the germanium substrate, a p-type or n-type germanium layer formed on the chromium-doped gallium arsenide layer, and a semiconductor formed on the germanium layer. A semiconductor device characterized by including an element.