JP2611358B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a CMOS transistor in which a channel layer of a PMOS transistor is formed of a semiconductor layer having a high hole mobility. The object of the present invention is to provide a CMOS transistor including a PMOS transistor having a high speed and a large current capacity. and then, sequentially and laminated intrinsic Si _1-x Ge _x layer and the intrinsic Si layer on each of at least a first region and a second region on a semiconductor substrate of high resistance, and the surrounding each of the first and second regions electrically and means for separating the source / drain regions formed by implanting p-type impurities as the said vacuum resistant Si layer side reaches said vacuum resistance Si _1-x Ge _x layer in a predetermined area of the first region A source / drain region formed by implanting an n-type impurity into the intrinsic Si layer in a predetermined region in the second region; and the intrinsic Si region between the source / drain region in each of the first and second regions. Insulation layer over layer A gate electrode formed Te, consists in having the ohmic electrode formed in contact with the source / drain region in each of the first and second regions.

[Industrial applications]

The present invention relates to a semiconductor device, in particular, a stacked different semiconductor layer including a semiconductor layer having high hole mobility.
The present invention relates to a CMOS transistor including a PMOS transistor and an NMOS transistor serving as a channel layer and an n-channel layer.

[Conventional technology]

CMOS used for highly integrated memory such as silicon DRAM
(Complementary MOS) gates have many advantages in circuit configuration, such as low power consumption, high integration, high noise immunity, and high fan-out. As shown in FIG. 5, this CMOS gate is composed of an NMOS (n-channel MOS) transistor (Tr ₁ ) and a PMOS (p-channel MOS) transistor (Tr ₂ ), but is usually a carrier of the PMOS transistor. The mobility of holes is smaller than the mobility of electrons that are carriers of NMOS transistors. For example, the mobility of electrons in silicon at room temperature is 1500 cm ² / V / S, whereas that of holes is 450 cm ² / V / S, which is about 1/3.

Therefore, in order to obtain the same current capacity as that of the NMOS transistor, it is necessary to increase the gate width of the PMOS transistor by two to three times, which increases the occupied area. This is one of the factors that limit the densification of integrated circuits using CMOS gates. In addition, carrier mobility is directly related to gate switching time.
For these reasons, there is a demand for a PMOS transistor having a high hole mobility, which is a decisive factor for realizing an increase in the current capacity and an increase in the speed of the CMOS gate.

Among the semiconductors known to date, materials having high hole mobility include Ge and InSb. The electron mobility and the hole mobility at room temperature are as shown in the following table.

Of these, InSb has a narrow bandgap of 0.17 eV, making it difficult to manufacture devices that operate at room temperature. On the other hand, Ge has been studied as a p-type transistor for some time. However, it is not possible to obtain a high-quality and stable oxide film such as SiO ₂ film on silicon, and there is a problem in surface treatment. As a result, it has not yet been put to practical use.

In recent years, the growth of crystal growth technology has been remarkable, and MBE (Molecu
lar Beam Epitaxy) has made it possible to form various semiconductor thin-film crystals. Among them, there is a method of growing Si _1-x Ge _x (x is a composition ratio of Ge) having an intermediate composition between Si and Ge on a silicon crystal (TPPearsall et al., 1s
t Int.Symp.on Si MBE 1985, H. Daembkes et al., IEDM 1
985, Sakamoto MitsuruIsao Electrotechnical Laboratory Research Report No. 875 No. etc. see) Moreover, the transistor used a two-dimensional hole gas generated at the heterojunction interface between the Si _1-x Ge _x and Si have been reported (TPPearsall , et al., IEEE Electron Device Letter
s, Vol.EDL-7, No. 5, May 1986, PP.308-310). This structure, as shown in FIG. 6, is obtained by forming a Ge on a p-type Si substrate.
_{It has a 0.2} Si _0.8 layer and a Si layer, and performs so-called modulation doping in which only the Si layer is doped with p-type impurities.
The concentration of the two-dimensional hole gas supplied to the _0.2 Si _0.8 layer is controlled by the gate voltage.

[Problems to be solved by the invention]

Fig. 6 shows that the Si layer is heavily doped with p-type
This is a structure for fabricating only transistors,
In the case where it is necessary to form an NMOS transistor together with a PMOS transistor like a gate, first, a substrate structure suitable for forming an NMOS transistor is formed, and this substrate is partially etched away in a region as shown in FIG. Ge _0.2 Si
_0.8 layer and Si layer will be grown. That is, it is necessary to perform selective growth in which semiconductor layers are individually epitaxially grown in a region where an NMOS transistor is formed and a region where a PMOS transistor is formed, and there is a problem that the process becomes complicated.

On the other hand, the inventor of the present invention has formed a Ge layer and a Si layer on an insulating silicon substrate by stacking the Ge layer and the Si layer as a channel layer of a PMOS transistor, and using the Si layer as a channel layer of an NMOS transistor. (Japanese Patent Application No. 63-000742, dated January 07, 1988).

FIG. 7 is a cross-sectional view of a principal part of the CMOS structure according to the above-mentioned application, in which a p-type Ge layer 2B serving as a channel layer of a PMOS transistor and a channel layer of an NMOS transistor are formed on an intrinsic silicon (i-Si) substrate 1. A p-type Si layer 3 is formed.
On both sides of the p-type Ge layer 2B, the Ge layer 2B, the Si substrate 1 and the Si layer 3
_1-x G for relaxing strain stress due to lattice mismatch with Si
e _x layer 2A is provided. The x value in the Si _1-x Ge _x layer 2A continuously changes so as to be 0 at the interface with the Si substrate 1 and the Si layer 3 and 1 at the interface with the Ge layer 2B.

P ⁺ source / drain 7 and 8 are formed for the PMOS transistor, and n ⁺ source / drain 11 and 10 are formed for the NMOS transistor. Gates 5PG and 5NG are provided on the upper surface of the p-type Si layer 3 between the p ⁺ source / drain 7 and 8 and between the n ⁺ source / drain 11 and 10 via gate insulating films 4PG and 4NG, respectively. . As described above, the gate 5PG and the p ⁺ source / drain 7 and 8 constitute a PMOS transistor having the p-type Ge layer 2B as the channel layer, and the gate 5NG and the n ⁺ source / drain 11
And 10 constitute an NMOS transistor having the p-type Si layer 3 as a channel layer. Then, the gates 5PG and 5NG are interconnected, and for example, the drain 8 and the drain 10 are interconnected to form a CMOS gate. Reference numeral 4A is a means for electrically separating the PMOS transistor and the NMOS transistor, for example, a groove. Codes 12,13,
Reference numerals 15 and 16 denote source / drain electrodes made of, for example, aluminum, V _DD and V _SS denote the voltages of the source electrodes of the p-channel and n-channel transistors, respectively. Usually, the power supply voltage is applied to V _DD , and V _SS is Connected to ground potential (GND). V _I and V _O represent, respectively, the input signal voltage and an output signal voltage.

The CMOS structure of FIG. 7 makes it possible to form a PMOS transistor having high hole mobility on the same substrate as the NMOS transistor.

The present invention is a further improvement of the CMOS structure according to the above-mentioned application, in which the logic amplitude of the CMOS gate having the above-mentioned structure is expanded and a crystal growth step containing a high concentration of impurities is performed, as will be described later. The object is to improve the uniformity of the element by eliminating the presence of the element.

[Means for solving the problem]

The above object is achieved at least by the first step on a high-resistance semiconductor substrate.
Intrinsic Si _1-x G sequentially laminated in each of the region and the second region
e _x layer and the intrinsic Si layer and, means for separating each of the first and second regions surrounding electrically, said vacuum resistant Si _1-x in a predetermined area of the first region from said vacuum resistant Si layer side and source / drain regions formed by implanting p-type impurity so as to reach the Ge _x layer, and the source / drain regions formed by implanting n-type impurities into said vacuum resistance Si layer in a predetermined area of the second region A gate electrode formed on the intrinsic Si layer between the source / drain regions in each of the first and second regions via an insulating layer; and a source / drain in each of the first and second regions. According to the present invention, there is provided an ohmic electrode formed to be in contact with the region.
Achieved by CMOS transistors.

(Operation)

C with Ge layer as p channel layer and Si layer as n channel layer
In the MOS structure, by forming the Ge layer from an intrinsic semiconductor, the threshold voltage for making the PMOS transistor conductive is lower than when both layers are p-type. As a result, the logic amplitude of the CMOS gate composed of these transistors becomes wider, and the noise margin increases.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same parts as those in FIG. 7 are denoted by the same reference numerals.

FIG. 1 is a cross-sectional view of a principal part showing the structure of a CMOS gate according to the present invention. For example, a thickness of a channel layer of a PMOS transistor is formed on a high-resistance Si substrate 1 such as intrinsic silicon (i-Si). An Si _1-x Ge _x layer 21 of about 200 ° and an Si layer 22 of about 100 ° in thickness serving as a channel layer of an NMOS transistor are formed. As in the CMOS gate of FIG. 7, Si _1-x
The composition of Ge _x layer 21, x value in the vicinity of the central portion of the thickness direction of the x value is 0, Si _1-x Ge _x layer 21 at the interface continuously such that the first and the Si substrate 1 and the Si layer 22 Is changing. As a result, the Si substrate 1
And it is between the interface between the Si layer 22 and the Si _1-x Ge _x layer 21 does not occur lattice mismatch. Note that a sapphire substrate may be used instead of the Si substrate 1.

In the present invention, impurities are not doped in the Si _1-x Ge _x layer 21 and the Si layer 22, are both intrinsic semiconductor. That is, i
It is difference from the case of Figure 7 is -Si _1-x Ge _x layer 21 and the i-Si layer 22.

As in FIG. 7, p ⁺ source / drain 7 and 8 and n ⁺
Source / drain 11 and 10, gate insulating films 4PG and 4NG made of, for example, SiO ₂ and gates 5PG and 5NG made of polycrystalline silicon (n ⁺ -Poly-Si) doped with n-type impurities are formed. PM gate 5PG and p ⁺ source / drain 7 and 8 of the _{i-Si 1-x} Ge _x layer 21 and the channel layer
OS transistor, gate 5NG and n ⁺ source / drain 11
And 10 constitute an NMOS transistor having the i-Si layer 22 as a channel layer. The gates 5PG and 5NG are interconnected, for example, the drain 8 and the drain 10 are interconnected to form a CMOS gate. Reference numeral 4A denotes a means for electrically separating the PMOS transistor and the NMOS transistor, and a method of forming the means will be described later. Code 12,1
3,15,16 is, for example, the source / drain electrodes made of Aruminiumu, for example p ⁺ source 7 to the high voltage power supply V _SS,
The n ⁺ source 11 is connected to a low voltage power supply, for example, a ground potential (GND).

FIG. 2 is an energy band diagram for the CMOS structure of FIG. In the figure, _{ｐ p} and χ _s are
Polycrystalline silicon gate (5PG and 5NG) and Si layer respectively
Indicates electron affinity with the 22, also, E _c and E _v are the top of the bottom and the valence band of the conduction band, E _i is an intermediate level of E _c and E _v,
E _F indicates the Fermi level, respectively. FIG. 2 (a) corresponds to the case where the gate voltage is 0 volt. In this state, the _{i-Si 1-x} Ge _x layer 21 and the i-Si layer 22 not channel occurs.

On the other hand, as shown in FIG. 2 (b), a positive bias voltage V _{TN of} a certain magnitude exists at the gates (5PG and 5NG).
When n is applied, an n-channel is generated by electrons accumulated in the conduction band of the i-Si layer 22 near the interface with the SiO ₂ gate insulating film (4PG and 4NG). On the other hand, as shown in FIG. 2 (c), a gate (5PG and 5 ng) by applying a negative bias voltage V _TP of magnitude in, near the interface vicinity of the i-Si layer 22 i-Si _1- p-channel occurs due to the positive holes accumulated in the valence band of _x Ge _x layer 21. That is, the bias voltage V _TN is a threshold voltage at which the NMOS transistor becomes conductive, and when the gate-source voltage V _GS is V _GS > V _TN , the NMOS transistor of the CMOS gate is conductive. on the other hand,
The bias voltage _VTP is a threshold voltage at which the PMOS transistor is turned on, and when _VGS < _VTP , the PMOS transistor of the CMOS gate is turned on.

FIGS. 3 (a) and 3 (b) are diagrams for explaining the operation of the CMOS gate.
MOS transistor source-drain resistance R _DS and V
₅ is a general graph showing the relationship between _{GS and} the relationship between the output voltage V _O and V _GS of the CMOS gate. Although no special explanation is required for these graphs, the logic amplitude of the CMOS gate, that is, the input signal voltage V V required to switch the output voltage V _O between a high level (for example, V _SS ) and a low level (for example, 0 volt) is shown. _The amount of change in _I (V _GS ) is the difference between V _TN and V _TP .

As in the above embodiment, by constituting the p-channel layer by _{i-Si 1-x} Ge _x layer 21 is an intrinsic semiconductor, compared with the case of using a p-type Ge layer 2B, as shown in FIG. 7 Since _VTP shifts to a lower voltage direction, the logic amplitude of the CMOS gate is expanded.

Next, a process of forming a CMOS structure having the structure shown in FIG. 1 will be described with reference to a cross-sectional view of a main part in FIG.

Fourth, as shown in Figure (a), for example i-Si on the substrate 1, a thickness of about _{200Å i-Si 1-x Ge} x layer 21 and the thickness of about 100Å of i
-Forming an Si layer 22 sequentially; The formation of these layers is well-known MB
It is preferable to use the E (molecular beam epitaxy) method. As indicated above, the composition of the _{i-Si 1-x} Ge _x layer 21, at the interface between the i-Si substrate 1 is x = 0, x = 1 becomes in the vicinity of the center of the layer thickness, i-Si layer 22 Are continuously changed so that x = 0 again at the interface with. This can be easily implemented using the MBE method. After the formation of the Si _1-x Ge _x layer 21, the Si _1-x Ge _x layer 21 is covered by the subsequently formed Si layer 22 in the same device, so that the interface state can be maintained without being exposed to the air. .

Next, in order to electrically separate the PMOS transistor formation region and the NMOS transistor formation region, protons (H ⁺ ) are implanted between these regions, and as shown in FIG. To form As another separating means instead of the separating layer 4A, the i-Si substrate 1 to i-Si layer
The groove may be formed by removing the groove 22. Separation layer 4A
After that, for example, the entire surface of the i-Si layer 22 is oxidized to form a SiO ₂ film 40 having a thickness of about 100 ° which becomes a gate oxide film.

Next, a polycrystalline silicon layer having a thickness of about 3500 ° is formed on the entire surface of the SiO ₂ film 40 using, for example, a known CVD method. The polycrystalline silicon layer and the SiO ₂ film 40 are selectively removed by using a well-known lithographic technique, doped with arsenic (As), and then, as shown in FIG.
Gate 5P opposed to i-Si layer 22 via 4PG and 4NG
Form G and 5NG.

After the above, as shown in FIG. 4 (d), the NMOS formation region is selectively masked with a mask layer 23 made of, for example, aluminum (Al), and a p-type region is formed on the surface exposed from the mask layer 23. BF ₂ (boron difluoride) ion (B
F ₂ ⁺⁾ is injected. The dose at this time is about 10 ¹⁵ ions / cm
² , and the ion acceleration voltage is about 50 KeV. At the above ion acceleration voltage, BF ₂ ions cannot pass through the gate 5PG,
As a result, p ⁺ source / drain 7 and 8 are formed on both sides of gate 5PG. Although p ⁺ source / drain 7 and 8 it is sufficient to form a depth in contact with the _{i-Si 1-x} Ge _x layer 21, according to the ion acceleration voltage, BF ₂ ions are i-Si layer
Because they have an energy that passes through 22 and _{i-Si 1-x} Ge _x layer 21, the source / drain 7 and 8 a depth reaching the i-Si substrate 1.

Next, after the mask layer 23 is removed, as shown in FIG.
, And As ions (As ⁺ ) are implanted as n-type impurities into the surface exposed from the mask layer 24.
The dose at this time is about 10 ¹⁶ ions / cm ² and the ion acceleration voltage is about 120 KeV. In the above ion acceleration voltage
As ions cannot pass through gate 5NG, resulting in gate 5
N ⁺ source / drain 11 and 10 are formed on both sides of NG. It is sufficient if the n ⁺ source / drain 11 and 10 are formed at a depth in contact with the i-Si layer 22. However, according to the above-mentioned ion accelerating voltage, As ions are converted into the i-Si layer 22 and i-Si _1-x Ge _x layer 2
The source / drain 11 and 10 have a depth reaching the i-Si substrate 1 because they have energy passing through 1.

After the above, the mask layer 24 is removed, and as shown in FIG. 4 (f), the source / drain electrodes 12, 1 made of, for example, an Al layer connected to the source / drain 7, 8, 10, 11 respectively.
3,15,16 are formed. Source / drain electrodes 12, 13, 15, 16
May be formed using a known thin film technique and lithographic technique. Thereafter, as shown in FIG.
The G and 5 NG and the p ⁺ drain 8 and the n ⁺ drain 10 are interconnected to complete the CMOS structure according to the present invention.

〔The invention's effect〕

According to the present invention, there is provided a PMOS transistor in which a semiconductor layer in which a Ge layer and a Si layer having high hole mobility are stacked is used as a channel layer.
High speed, high current capacity CMOS that can form NMOS transistors
There is an effect that a transistor can be realized. In particular, in the CMOS structure of the present invention, since the channel layer is made of an intrinsic semiconductor, the operation margin is expanded, and the uniformity of the device is further improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a principal part showing a CMOS structure according to the present invention, FIG. 2 is an energy band diagram in the COMS structure of FIG. 1, FIG. 3 is a graph for explaining the operation of a CMOS gate, FIG. Is a cross-sectional view of a main part showing a process of forming the CMOS structure of FIG. 1, FIG. 5 is an equivalent circuit diagram of a CMOS transistor, and FIG. 6 is a conventional p-channel type using a GeSi layer as a channel layer.
FIG. 7 is a cross-sectional view of a main part showing a structure of a FET.
FIG. 3 is a cross-sectional view of a main part for describing a structure of an OS structure before the improvement according to the present invention. In the figure, 1 is i-Si substrate, 2A is p-type Si _1-x Ge _x layer, 2B is p-type Ge layer, 3 p-type Si layer, 4A separation layer, 4PG and 4NG gate insulating film, 5PG and 5NG gate, 7 and 8 p ⁺ source / drain 11 and 10 are n ⁺ source / drain, 12 and 13 and 15 and 16 the source / drain electrode, 21 _{i-Si 1-x} Ge _x layer, 22 is an i-Si layer, 23 and 24 are mask layers, and 40 is an SiO ₂ film.

Claims (1)

(57) [Claims] _1. Intrinsic Si _1-x Ge _x sequentially laminated on at least each of a first region and a second region on a high-resistance semiconductor substrate.
A layer and an intrinsic Si layer; means for electrically separating each of the first and second regions from the surroundings; and a predetermined region in the first region from the intrinsic Si layer side to the intrinsic Si layer.
_1-x Ge _x and the source / drain regions formed by implanting p-type impurity so as to reach the layer, formed by implanting n-type impurities into said vacuum resistance Si layer in a predetermined area of the second region source / A drain region; a gate electrode formed on the intrinsic Si layer between the source / drain regions in each of the first and second regions via an insulating layer; and a gate electrode in each of the first and second regions. A semiconductor device comprising: an ohmic electrode formed to be in contact with a source / drain region.