WO1997011496A1

WO1997011496A1 - Semiconductor device, method of producing the same and system using the semiconductor device

Info

Publication number: WO1997011496A1
Application number: PCT/JP1995/001844
Authority: WO
Inventors: Eiji Ooue; Takahiro Onai; Katsuyoshi Washio; Yukihiro Kiyota; Masao Kondo; Katsuya Oda; Toru Masuda
Original assignee: Hitachi, Ltd.
Priority date: 1995-09-18
Filing date: 1995-09-18
Publication date: 1997-03-27

Abstract

A low-power ultrahigh-speed bipolar transistor and a circuit using the same are provided to achieve ultrahigh-speed transmission and receiving of a large quantity of signals as well as low-noise operation of a portable wireless device for extended periods of time. A silicon oxide film (115) is inserted under a polycrystalline silicon graft base (113) that connects a base region (114) to a base polycrystalline silicon electrode (110). This makes it possible to lower the base resistance and the base-collector capacitance, and to obtain a low-power transistor that operates at high speeds.

Description

Semiconductor device, method of manufacturing the same, and system using semiconductor device

The present invention relates to a semiconductor device capable of high-speed operation, particularly to a bipolar transistor, and further relates to a method for manufacturing the semiconductor device, an optical transmission system device using the semiconductor device, and a mobile wireless portable device. . Background art

In order to increase the operation speed of bipolar transistors and to improve the cutoff frequency, research and development on so-called “shallow” bases, in which the base region is formed thinner, are being conducted. In order to make the base shallow, there is known a technique of forming the base region thin by depositing the base region by epitaxy, as in a conventional technology described later. According to this technology, the thickness of the base region can be controlled relatively easily, compared to a technology in which the base region is formed by diffusion into a semiconductor substrate. be able to. Also, when the base region is formed by an epitaxial growth method, a technique for selectively performing epitaxial growth only on a desired region is known. By using the selective epitaxy technique, it is possible to reduce the size of the active region by eliminating the above-described shallow base, and to eliminate extra parasitic components.

FIG. 2 is a cross-sectional view of a conventional bipolar transistor using a conventional silicon selective epitaxial method disclosed in Japanese Patent Application Laid-Open No. Hei 5-3-1542. In FIG. 2, reference numeral 201 denotes a p-type silicon substrate, 202 denotes an n + -type buried layer, 203 denotes an n- -type silicon epitaxial layer, 204 denotes a LOCOS oxide film, and 2 denotes a LOCOS oxide film. 05 is an n + type phosphorus diffusion layer, 206 is a silicon nitride film, 207 is polycrystalline silicon for a p + type base electrode, 208 is polycrystalline silicon for an n + type collector electrode, 2 09, 214, 220 are silicon nitride films, 210 is an n-type buried layer, 211 is a single-crystal silicon collector, 211 is a single-crystal silicon intrinsic base layer, 2 13 is polycrystalline silicon WO 97/11496

215, a single-crystal silicon emitter; 216, an Ai-based electrode; and 219, a polycrystalline silicon for an n + -type emitter electrode. The single-crystal silicon intrinsic berth layer 212 is deposited by an epitaxy method on the main surface of the silicon substrate 201 on which the collector region is formed. Disclosure of the invention

In the prior art shown in FIG. 2, in order to reduce the base resistance, the amount of side etching of the silicon nitride film 206 is increased to make the base polycrystalline silicon electrode 207 and the polycrystalline silicon graph base 21 1 As the area 3 increases, the contact area between the base region 2 12 and the collector low-accuracy layer 203 increases, and the base-collector capacitance increases. In general, the contact area between the base polycrystalline silicon electrode 207 and the polycrystalline silicon graphite base 213 cannot be reduced below a certain area in consideration of the maximum base resistance. Therefore, the content of the base region 211 and the collector region 203 is inevitable! : Cannot be less than a certain value. Thus, in the conventional structure shown in Fig. 2, the base resistance and base no collector capacitance! There is a trade-off of M, and it is impossible to achieve a bipolar device that can operate at high speed by balancing both. If the parasitic capacitance component is large, power is consumed by charging / discharging the capacitance Jfc component, making it * difficult to reduce power consumption.

As described above, even if the base region is epitaxially grown, particularly by selective epitaxy, and a certain high-speed operation is achieved, the conventional technology reduces the base resistance for further high-speed operation, and It is difficult to eliminate the parasitic capacitance i component such as base and collector capacitance. The limitation of the high-speed operation of such a bipolar transistor impedes the high-speed operation of various semiconductor integrated circuit devices using the same, and furthermore, the high-speed operation of a system using the same. The need to compensate for the high-speed operation of Gbps optical communication systems also necessitates an increase in the operating speed of transistors. In addition, when constructing a system that requires strong power consumption, such as a mobile wireless terminal device, it is necessary to realize a transistor with a reduced parasitic capacitance component.

Therefore, a typical object of the present invention is to overcome the above-mentioned problems, Another object of the present invention is to provide a transistor that operates at high speed with low power consumption by reducing the base / collector capacitance ft.

Still another object of the present invention is to provide a manufacturing method capable of realizing the above-described transistor by a relatively simple process.

Still another object of the present invention is to provide a system such as an optical transmission system that can operate at high speed with low power consumption by using a semiconductor device that can operate at high speed with low power consumption.

Further, other typical objects of the present invention will become apparent from the specification and drawings of the present application.

In order to achieve the above-mentioned typical object, in a typical embodiment of the present invention, an insulating film is inserted under a polycrystalline semiconductor graft base which is a connection portion between a base region and a base polycrystalline silicon electrode. And separate it from the collector region to reduce base / collector junction area.

A semiconductor device according to a representative embodiment of the present invention includes:

A first conductive type semiconductor substrate (103) and a first conductive type second semiconductor of a second conductive type opposite to the first conductive ffi type formed in contact with the main surface of the semiconductor base A region (1 14), a second semiconductor region (1 18) of a first conductivity type formed in the first semiconductor region, and a polycrystalline semiconductor deposited on the semiconductor substrate via an insulating film And the polycrystalline semiconductor layer is configured so as to be connected to the first semiconductor region on the side surface thereof.

In addition, a semiconductor device according to a typical configuration of the present invention includes:

A semiconductor substrate (101), a first semiconductor region (103) of a first conductivity type formed on the semiconductor substrate, and a second conductivity type opposite to the first conductivity type. A second conductive semiconductor region (114); a first conductive third semiconductor region (118) formed in the first semiconductor region; and a first wiring layer The second semiconductor region is formed on the main surface of the first semiconductor region, and the first wiring layer is formed on the main region of the first semiconductor region. It is formed on the first semiconductor region via the insulating film (105) formed on the surface.

Further, a semiconductor device according to a representative embodiment of the present invention includes: A first semiconductor region of the first conductivity type (103); a second semiconductor region of the second conductivity type (1 14) deposited on the main surface of the first semiconductor region; A third semiconductor region of the first conductivity type formed in the semiconductor region of the first conductivity type, and a first insulating film formed on the main surface of the first semiconductor region and having a first opening. (105); a second insulating film (107) formed on the first insulating film and having a second opening having an opening area larger than that of the first opening; A wiring layer (115, etc.) formed in contact with the second semiconductor region, the bottom surface of the second semiconductor region is defined by the first opening, and the wiring layer is The second opening is connected to the first insulating film, and the first opening is connected to the second semiconductor region.

Further, a method for manufacturing a semiconductor device according to a representative embodiment of the present invention includes:

A first step (105) of forming a first insulating film on a surface of a semiconductor substrate (103) of a first conductivity type formed on a semiconductor substrate (101), and the first insulating film A second step of forming a second insulating film (107) thereon; a third step of forming a first conductor layer (110) on the second insulating film; A fourth 'step (FIG. 5 (b)) of forming a first opening by etching the first conductor layer and the second insulating film; and forming the second opening through the first opening. A fifth step (FIG. 5 (c)) of forming a second opening by selectively etching the insulating film;

A sixth step (FIG. 5 (c)) of filling the second opening with the semiconductor material by depositing the semiconductor material through the first opening, and passing through the first opening. A seventh step of etching the first insulating layer until the surface of the semiconductor substrate is exposed, and selectively depositing a semiconductor material on the surface of the semiconductor substrate through the first opening. And an eighth step (FIG. 6 (a)) of depositing until the semiconductor material is filled with the opening.

Further, a method for manufacturing a semiconductor device according to a typical form of the present invention includes:

Forming a front body in which a first conductor layer (1 06) having a first opening is stacked on a main surface of a single crystal semiconductor substrate (1 03) via a first insulating film (105) And selectively depositing a semiconductor material on the main surface of the semiconductor substrate from the first opening to form a first semiconductor region (114, etc.) and contact with the first conductor layer. Process and Forming a second conductor layer containing impurities on the first semiconductor region; and diffusing the impurities from the second conductor layer into the first semiconductor region. Forming a second semiconductor region (118).

In the present invention, the first polycrystalline semiconductor graphite base 113 shown in FIG. Decrease in contact resistance of crystalline semiconductor graft base 113

The resistance of the polycrystalline semiconductor graft base 1 13 can be reduced. Therefore, if the sheet resistance of the base slaughter 114 is the same, the base resistance can be reduced as compared with the conventional example.

In addition, since the first polycrystalline semiconductor graft base 113 is on the silicon oxide film 105, the base collector capacitance in this region is equal to the capacitance of the silicon oxide film 105 and that of the low concentration collector layer 103. Yeah! : Series with! , Which can be reduced to about 12 or less as compared with the conventional case where only the low concentration collector layer 103 is used. Furthermore, the ratio of the planar projection area of this region to the emitter area increases as the emitter size decreases, and if the low-concentration collector layer 103 is made thinner for the purpose of speeding up, It depends on the invention! : The reduction effect is greatly increased, and the base-collector capacitance can be reduced to about 1 2.

As described above, according to the present invention, the base resistance can be reduced and the base collector capacitance can be reduced, and low power consumption and high speed operation can be achieved. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a sectional view of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional bipolar transistor.

Fig. 3 shows the parasite of the present invention! : Diagram showing the effect of extinction.

FIG. 4 is a first sectional view showing a manufacturing process of the bipolar transistor according to the first embodiment of the present invention.

FIG. 5 is a second sectional view showing the manufacturing process of the bipolar transistor according to the first embodiment of the present invention.

FIG. 6 shows a manufacturing process of the bipolar transistor according to the first embodiment of the present invention. Third sectional view.

FIG. 7 is a fourth sectional view showing the manufacturing process of the bipolar transistor according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view of a bipolar transistor according to a second embodiment of the present invention.

FIG. 9 is a first cross-sectional view showing a manufacturing process of the bipolar transistor according to the third embodiment of the present invention.

FIG. 10 is a second sectional view showing the manufacturing process of the bipolar transistor according to the third embodiment of the present invention.

FIG. 11 is a third sectional view showing the manufacturing process of the bipolar transistor according to the third embodiment of the present invention.

FIG. 12 is a fourth sectional view showing the manufacturing process of the bipolar transistor according to the third embodiment of the present invention.

FIG. 13 is a cross-sectional view of a bipolar transistor according to a fourth embodiment of the present invention. FIG. 14 is a first cross-sectional view showing a manufacturing process of the bipolar transistor according to the fifth embodiment of the present invention.

FIG. 15 is a second sectional view showing the manufacturing process of the bipolar transistor according to the fifth embodiment of the present invention.

FIG. 16 is a third sectional view showing the manufacturing process of the bipolar transistor according to the fifth embodiment of the present invention.

FIG. 17 is a front S-width circuit diagram of an optical transmission system according to a sixth embodiment of the present invention. FIG. 18 is a front-end module of an optical transmission system according to a seventh embodiment of the present invention.

FIG. 19 is a configuration diagram of an optical transmission system according to an eighth embodiment of the present invention.

FIG. 20 is a configuration diagram of an optical transmission system according to an eighth embodiment of the present invention.

FIG. 21 is a configuration diagram of a mobile radio portable device according to a ninth embodiment of the present invention.

FIG. 22 is a circuit diagram of a D flip-flop according to a tenth embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, various embodiments of ft for implementing the present invention will be described as examples. FIG. 1 shows a sectional view of a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a bipolar transistor according to the present embodiment, and is a cross-sectional view of a substantially completed stage although a final protective film and the like are omitted.

In FIG. 1, 101 is a p-type silicon substrate of a first conductivity type, 102 is an n-type high-concentration collector buried layer of a second conductivity type opposite to the first conductivity type, 3 is an n-type low concentration collector layer. In this embodiment, since the base region formed by selective epitaxy growth on the semiconductor substrate is used, the main surface of the collector region becomes the main surface of the semiconductor substrate and is formed in a substantially planar shape. A base region is formed.

Further, 104, 105, 106, 111, 116, 119 are insulating films such as silicon oxide films, and 107 is a silicon oxide film which is insulating films. Note that the material of the insulating film 105 and the insulating film 107 is not limited to the oxide film and the nitride film, and that the material of the cabinet is such that the insulating film 105 has a sufficiently high selectivity to the insulating film 107. An insulating film is sufficient. Reference numeral 110 denotes a base polycrystalline silicon electrode which is an extraction electrode of a base region formed of polycrystalline silicon. According to this embodiment, the base extraction S pole 110 is formed so as to be connected to the base region from the side surface via the later-described graft base regions 113 and 115. The base extraction electrode is formed on the substrate only through the insulating film 105 in the vicinity of the graft base region 113, but has a tapered shape as the distance from the graft base region 113 increases. Since the insulating film 106 having the inclined surface is formed via the insulating film 106, the structure is such that the distance from the semiconductor substrate gradually increases. By adopting such a configuration, as will be described later, the connection with the graph base region can be relatively easily performed in the vicinity of the graph base, and the distance from the semiconductor base 103 to the other portions is relatively small. And the parasitic capacitance between the lead electrode 106 and the semiconductor substrate 103! : Can be eliminated.

Reference numeral 113 denotes a first polycrystalline semiconductor graft base that electrically connects the intrinsic base region 114 and the base extraction electrode 110. The first graph base region is connected to the base extraction electrode 110 on the upper surface, and the collector region 103 is connected to the base region through the silicon oxide 105 which is an insulating film on the lower surface. Semiconductor substrate to be formed Is in contact with Further, one of the side surfaces is formed in contact with a second graft base region which is electrically connected to the base region 114, which will be described later, and the other is formed in contact with the silicon nitride layer 107. Although not shown in FIG. 1 which is a cross-sectional view, the base region 114 and the emitter region 118 are formed with a distance also in the depth direction of the drawing, and have a rectangular shape with rounded corners. Is formed. Similarly, the graph base areas 1 13 and 1 15 are shaped to surround the base castles 114. The base extraction electrode 110 also surrounds the base region, and is configured to be connected to the base region 114 via the graft base region.

Reference numeral 114 denotes a single-crystal semiconductor base layer, which is formed in the present embodiment in such a manner that it does not overlap with the base extraction electrode as described above. In this embodiment, the base region 114 can be made of a silicon single crystal, and can also be made of a so-called silicon germanium using a mixed material of silicon and germanium. is there. Generally, a single crystal with few crystal defects can be easily formed when formed only with silicon, and the characteristics of a transistor can be improved when silicon germanium is used. Reference numeral 115 denotes a second polycrystalline semiconductor substrate which electrically connects the base layer 114 and the base lead electrode 110 to each other, and has a contact area with the base region 114. In order to increase the resistance and reduce the resistance value, the semiconductor substrate is configured to be obliquely in contact with the main surface of the semiconductor substrate. In the present embodiment, the side surface of the base region is configured to have the (111) plane with respect to the semiconductor substrate 103 having the (100) plane.

Reference numeral 117 denotes an emitter polycrystalline silicon electrode, and reference numeral 118 denotes an emitter region. According to the embodiment shown in FIG. 1, the connection between the base lead-out electrode 110 and the epitaxial base region 114 does not come into contact with the collector region 103, and the side surface of the base region 114 does not come into contact with the collector region 103. Is being read from. Therefore, it is not necessary to increase the size of the base region, which was required in the past, in a planar manner for connection with the extraction electrode, and the base region can be formed with a minimum size for performing selective epitaxial growth. Base · Collector capacity can be reduced.

In addition, the graft base region 113 connecting the base extraction electrode 110 and the epi base region 114 is formed on the main surface of the semiconductor substrate forming the collector region. o is arranged via 5 g. Therefore, draw out the base

—The volume formed between the source region and the collector region! : Can also be reduced. As described above, according to the present embodiment, the parasitic capacitance ft between the base and the collector can be reduced, and a sufficient contact area can be secured by connecting the base region and the extraction electrode from the side. Elimination of resistance can also be achieved.

In addition, in the present embodiment, the base region is formed by selective epitaxial growth, so that the effects of the above-described embodiment and the effects of selective epitaxial growth are combined, so that higher speed operation and lower power consumption can be achieved. Things.

Next, the effects of the above-described embodiment will be described with reference to FIG.

In the graph of FIG. 3, the horizontal axis represents the thickness d _{e P} i of the low concentration collector layer (103 in FIG. 1 and 203 in FIG. 2), and the vertical axis represents the base-collector according to the above embodiment. Peripheral volume between SCTC and conventional base collector! : It is the ratio with CTC. The peripheral volume ft between the base and collector in the conventional example is formed by the base region 2 12 immediately below the graph base region 2 13, the low-concentration collector region 203 and the high-concentration collector region 202 It is i. This can be considered as a parasitic capacitance using the base region 211 and the high concentration collector region 202 as electrodes because the low concentration collector region 203 is depleted. The base-collector peripheral volume i CTC according to the present embodiment has a graft base region because the insulating film 105 is interposed between the graphite base 113 and the collector low-concentration layer 103. The parasitic capacitance Jt using the electrodes 113 and the high-concentration collector layer 102 as both electrodes can be considered. Note that Fig. 3 shows the case where the WE of the emitter in the emitter region is 0.1, 0.2, and 0.4 (where the value of 1 <^ (is in the range of 0.05 m to 0.15 μπι). The data up to is shown.

As is evident from FIG. 3, the value of the CTC according to the present embodiment divided by the value of the CTC according to the conventional example (vertical axis in FIG. 3) is less than 1 in all cases. It can be seen that the capacitance between the base and the collector has decreased. In particular, as the emitter width, for example, the emitter WE, becomes smaller, the graph becomes lower in the figure, indicating that the effect of this embodiment becomes more remarkable as the size becomes smaller. I have.

Next, FIGS. 4 to 7 show a manufacturing method of the first embodiment of the present invention. First, as shown in Fig. 4 (a), a high-concentration n-type collector buried layer 102 is formed on a silicon substrate 101 by thermal diffusion, and then a low-concentration n-type collector is formed by silicon epitaxial growth. The layer 103 is formed. The low-concentration collector layer 103 is formed in the shape of a semiconductor substrate, becomes a base portion of an element, and has a substantially planar surface. A trench having a depth of 3 / m is formed by dry etching so as to surround the periphery of the high-concentration n-type collector buried layer 102 on the plane, and the silicon oxide film 104 is buried. As a result, it is possible to form a collector region which is a base portion on which the bipolar transistor is formed, and which performs S-gas separation from another adjacent element.

Next, as shown in FIG. 4 (b), a low concentration n-type collector layer 103 is thermally oxidized to form a silicon oxide film 105 of about 30 nm. The thermal oxidation is preferably performed at a temperature as low as possible from the viewpoint of preventing the high-concentration collector layer 102 from rising, and in this embodiment, the thermal oxidation is performed at about 90 Ot. Next, a silicon oxide film 106 of 200 ηm is formed by the CVD method, and only a silicon oxide layer 106 is removed by wet etching at a place where an emitter is to be formed. This is because a step is formed in the silicon oxide film 106 in order to secure a space between a base lead electrode formed later and the semiconductor substrate and to facilitate connection with the base region. After that, approximately 50 nm of silicon nitride 107 is formed by the CVD method. Here, other materials can be used instead of the silicon nitride film 107. Since the silicon nitride film 107 is partly removed later by etching, it is necessary to use a material having a sufficient selectivity with respect to the silicon oxide film.

Next, as shown in FIG. 4 (c), the silicon oxide film 107, the silicon oxide film 106, and the silicon oxide film 105 are opened by dry etching, and n-type impurities are ion-implanted. , An n-type layer 108 is formed. Thereafter, a collector polycrystalline silicon electrode 109 is formed.

Next, as shown in FIG. 5 (a), a 200 nm p-type polycrystalline silicon film 110 is deposited and processed into a base polycrystalline silicon polarized pattern. The base extraction electrode 110 is processed into a size necessary to be connected to the base electrode later, and the silicon oxide film 106 formed by selective etching as shown in FIG. 4 (b). It is formed so as to straddle the step. On top of that, a 200 nm silicon The con oxide film 111 is laminated.

Next, as shown in FIG. 5 (b), the silicon oxide film 111 and the base polycrystalline silicon electrode 110 are etched using the resist film defining the intrinsic region of the transistor as a mask. . After that, a silicon oxide film 112 is deposited to a thickness of about 100 nm, and a side wall insulating film 112 is formed by dry etching. Next, as shown in FIG. 5 (c), the silicon nitride film 107 is side-etched by wet etching using hot phosphoric acid or the like. This side-etched portion is filled with polycrystalline silicon later to form a contact with the base lead electrode. Therefore, it is necessary to increase the sharpening point as much as possible from the point of sharpening of the contact surface, but it cannot be increased without limit in consideration of the capacitance between the base and collector. In the present embodiment, a side etch of about 100 nm is performed as a value satisfying both requirements.

After that, the first p-type polycrystalline semiconductor graft base 1 having the same thickness as the silicon nitride film 107 was formed by selective growth only on the portion of the base polycrystalline silicon electrode 110 exposed by the side-etching. Form 1 3. The selective growth is performed at a temperature of about 500 to 600 using monosilane, disilane, or a mixed gas of these and germane depending on the material to be deposited. By the treatment under such conditions, the polycrystal is grown using the polycrystal base extraction electrode as a seed, and the graft base region 113 is formed.

Next, as shown in FIG. 6 (a), the silicon oxide film 105 is etched using an HF-based etchant, and the p-type single crystal semiconductor base layer 114 is formed by selective growth. A second p-type polycrystalline semiconductor graft base 1 15 is simultaneously formed. This selective growth can be performed under the same conditions as the selective growth of the graft base region 113 described above. The base region 1 14 is deposited on the low-concentration collector layer 103, which is a single crystal, while maintaining the single crystal. The gradient region 1 15 is a polycrystalline graphite base region 1 1 3 Is deposited in a polycrystalline state. If the surface of the low-concentration collector region 103 has the (100) plane, the side surface of the base region 114 growing as a single crystal becomes the (111) plane. As shown in a), the region to be a single crystal and the region to be a polycrystal are oblique along the (111) plane. In addition, The silicon region 114 can be made of either a silicon single crystal or a silicon-germanium single crystal, but generally, silicon-germanium has characteristics such as a larger current width ratio.

In this embodiment, the step of filling the graft base region 113 and the step of depositing the graft base region 115 and the base region 114 are performed separately. As a result, the graphite base region 113 can be sufficiently filled, the connection with the base extraction electrode 110 can be sufficiently achieved, and the impurity concentration can be set separately. In addition, the impurity concentration of the graft base region 113 can be increased, and the base resistance can be reduced. Of course, it is possible to fill the graft base region 113 simultaneously with the formation of the base region 114, but it is necessary to select the conditions for selective growth so that the graft base region 113 is sufficiently filled. . In such a process, at the step shown in FIG. 5 (b), an opening is formed up to the silicon oxide film 105, the silicon nitride film 107 is removed by wet etching, and then selective growth is performed. It can be realized.

Next, as shown in FIG. 6 (b), a silicon oxide film is again deposited on the entire surface by the CVD method, and the side wall insulating silicon oxide film 116 is removed by anisotropic dry etching. Form. After that, a high-concentration n-type polycrystalline silicon is deposited on the entire surface, and the periphery of the emitter region is etched using a resist mask having an S-shaped pattern to form a polycrystalline silicon emitter electrode 117. Next, heat treatment is performed at 900 for about 30 seconds, and n-type impurities are diffused from the polycrystalline silicon emitter electrode 117 to the surface of the base layer 114 to form an emitter region 118. . By such processing, the bipolar transistor according to the present embodiment has a collector region 103 formed by depositing on the semiconductor substrate and a base region 114 formed by projecting on the collector region. The base electrode is formed from an emitter region formed by diffusion in the base castle, and the base extraction electrode can be configured to be connected from the side surface of the base castle. In addition, by adopting such a manufacturing method, a portion deposited as the base region 114 and in contact with the collector slope remains in an open area for selective growth, so that the base-collector capacitance can be reduced.

Thereafter, as shown in FIG. 7, a silicon oxide film 119 is deposited, and an emitter and a base are deposited. Open the silicon oxide film 119 on the electrode of each source and collector by dry etching, and form the emitter electrode 120, the base electrode 121, and the collector ¾ 棰 122 with tungsten. . The structure shown in FIG. 1 is obtained by the above manufacturing method. The emitter electrode 120 and the like can be formed by a gold-extended material such as aluminum in addition to tungsten.However, when aluminum is used, it is necessary to consider the mutual diffusion of silicon with the polycrystalline silicon 117 and the like. It is necessary to use a barrier metal such as titanium nitride between them.

FIG. 8 is a sectional view of a second embodiment of the present invention. In this embodiment, the same parts as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.

In this embodiment, a silicon oxide film 130, which is an insulative material, is formed on a silicon substrate 101, and a single crystal silicon layer 131 serving as a semiconductor base portion on which elements are formed is formed thereon. In this embodiment, an SOI (silicon 'on' insulator) substrate is used, which is formed by using a manufacturing method similar to that of the first embodiment on an SOI substrate formed by known bonding or implantation of oxygen ions. Thus, the collector-to-substrate capacitance i is 1 Z2 compared to the first embodiment.In this embodiment, the reduction of the base-collector capacitance and the SOI substrate realized by the present invention can be achieved. It is possible to further reduce the parasitic capacitance S of the bipolar transistor by reducing the collector to substrate capacitance !.

Next, a third embodiment of the present invention will be described with reference to FIGS. 9 to 12.

FIG. 12 is a sectional view of a bipolar transistor according to a third embodiment of the present invention. The description of the parts of the present embodiment which are the same as those of the first and second embodiments will be omitted. In the present embodiment, a so-called LOCOS oxide film is used together with the groove 104 for element isolation.

In FIG. 12, reference numeral 134 denotes a local isolation oxide (OSC) oxide film for element isolation in which the area other than the element formation region is locally oxidized. 9 to 12 show a manufacturing method according to a third embodiment of the present invention.

First, as shown in Fig. 9 (a), a high concentration n-type collector buried layer 102 is formed on a silicon substrate 101 by thermal expansion, and then a low concentration n-type A collector layer 103 is deposited. Next, planarly high level n-type collector A 3 m deep is formed by dry etching so as to surround the periphery of the buried layer 102, the silicon oxide film 104 is buried, and a device for element separation for electrically separating the devices is formed. Form ¾.

Next, as shown in FIG. 9 (b), the surface of the low-concentration n-type collector layer 103, which is the semiconductor substrate formed by the epitaxial growth, is oxidized by thermal oxidation to form a silicon oxide film of about 20 nm. Form. Thereafter, a silicon nitride film 133, which is an oxidation-resistant film, is deposited on the entire surface by the CVD method to a thickness of about 200 nm, and dry etching is performed on portions other than those where the intrinsic region is to be formed, as shown in FIG. The silicon nitride film 133 is left.

Next, as shown in FIG. 9 (c), by thermally oxidizing the entire surface, the region where the silicon nitride film 133 does not remain is oxidized, and a LOCOS oxide film 134 of about 200 nm is formed. It is formed. After that, the silicon nitride film 133 and the silicon oxide film 132 are removed, and the entire surface is oxidized by about 30 nm.

Next, as shown in FIG. 10 (a), the silicon oxide film 107 and the LOCOS oxide film 134 are opened by dry etching, n-type impurities are ion-implanted, and contact with the collector electrode is made. An n-type layer 108 for reducing resistance is formed. Thereafter, a collector polycrystalline silicon electrode 109 is formed.

Next, as shown in FIG. 10 (b), a p-type polycrystalline silicon film 110 of about 200 nm is deposited and processed into a base polycrystalline silicon electrode pattern. At this time, as in Embodiment 1 described above, the base extraction electrode 110 is formed so that its end is formed on the LOCOS oxide film and has a step. A silicon oxide film 111, which is an interlayer insulating film of about 200 nm, is laminated thereon.

Next, as shown in FIG. 10 (c), using a resist film (not shown) for defining an intrinsic region of the transistor as a mask, the silicon oxide layer 111 and the base polycrystalline silicon electrode 110 are formed. Perform etching. Thereafter, in order to form a silicon oxide film 112 having a sidewall isolation, a silicon oxide is deposited to a thickness of about 100 nm and then dry-etched to form a side wall 112.

Next, as shown in FIG. 11A, the silicon nitride film 107 is side-etched with hot phosphoric acid by 100 nm. The side etch forms the graph base area described later. In order to secure a sufficient contact area with the base extraction electrode 110, the process is performed to the left and right in the figure to the bottom of the base extraction electrode 110, respectively. At this time, the base portion serving as the collector region is protected by the oxide film 134, and the side surface of the base lead electrode 110 is supported by the side wall oxide film 112. There is no undesired etching during side etching. After that, the first p-type polycrystalline semiconductor graph having the same thickness as the silicon nitride film 107 was formed only by the selective growth method on the portion exposed by the side etch under the base polycrystalline silicon electrode 110. Form the base 1 1 3

Next, as shown in FIG. 11 (b), the LOCOS oxide layer 134 is etched using an HF-based etchant, and the base layer 1 of the p-type single crystal semiconductor is formed by a selective growth method. 14 are deposited on the collector region 103. At this time, the second p-type polycrystalline semiconductor graft base 115 is simultaneously formed.

Next, as shown in FIG. 12, a silicon oxide film is deposited on the entire surface by the CVD method, and a silicon oxide film sidewall 16 is formed by anisotropic dry etching. Thereafter, high-concentration n-type polycrystalline silicon is deposited on the entire surface, and is etched using a resist mask having a pattern covering the periphery of the emitter region to form a polycrystalline silicon emitter electrode 117. Then, a heat treatment is performed at about 900 for about 30 seconds, and n-type impurities are diffused from the polycrystalline silicon emitter electrode 117 to the surface of the base layer 114 to selectively grow the base region 1. An emitter region 1 18 is formed in 14.

Further, a silicon oxide film 119 is deposited, and polycrystalline silicon of the emitter, base, and collector is opened. The silicon oxide film 119 on the electrode is opened by dry etching, and the emitter electrode 122 is made of tungsten. 0, base electrode 122, and collector electrode 122 are formed. The structure shown in FIG. 12 is obtained by the above manufacturing method.

In this embodiment, the thickness of the silicon oxide film 134 below the first graph base 114 is formed by the LOCOS method, so that the thickness increases as the distance from the emitter increases, and the base-collector capacitance becomes lower. Can be destroyed. In addition, since the process for forming the base extraction electrode 110 with a step can be formed by the process of forming the L〇COS oxide film, the silicon oxide film 106 as in the first embodiment can be formed.ゥ The etching step can be omitted.

Next, a fourth embodiment of the present invention is shown in FIG. Also in this embodiment, the description of the same parts as those in the above-described embodiment will be omitted.

In the present embodiment, a manufacturing method similar to that of the third embodiment is used by using an SOI substrate having a silicon oxide layer 130 as an insulating film and a single-crystal silicon layer 131 on a silicon substrate 101. . As a result, the capacitance between the collector substrates is about 1/2 that of the third embodiment. In this embodiment, since the above-described second and third embodiments are combined, it is possible to achieve the effects of both embodiments.

Next, a fifth embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 16 (b), the base extraction electrode 140 is formed of tungsten. Also in this embodiment, the description of the parts common to the above-described embodiments is omitted.

After forming the structure as shown in FIG. 4 (c) by the method described in the first embodiment, as shown in FIG. 14 (a), a 50 nm p-type polycrystalline silicon film 1 is formed. 35 is deposited and processed into a base polycrystalline silicon electrode pattern. On top of this, a 20 nm silicon oxide film 1336 and a 150 nm polycrystalline silicon film 1337 are stacked, and a 400 nm silicon oxide film 111 is further laminated.

Next, as shown in FIG. 14 (b), a silicon oxide film 111, a polycrystalline silicon film 1337, and a silicon oxide film 11 are used as a mask with a resist (not shown) defining an intrinsic region of the transistor. 1 36 and the p-type polycrystalline silicon film 1 35 are etched. After that, a silicon oxide layer 112 is deposited to a thickness of 100 nm, and a side wall is formed by dry etching.

Next, the polycrystalline silicon layer 117 is deposited on the entire surface through the steps shown in FIGS. 5 (c) to 6 (b) shown in the first embodiment and the like, and is shown in FIG. 15 (c). Such a structure is formed. Next, as shown in Fig. 16 (a), a silicon oxide film 1380 is deposited to a thickness of 300 nm, and a silicon oxide film 1380, an emitter polycrystalline silicon electrode 117 and a silicon oxide film 111 are formed. Is processed by dry etching into a pattern covering the emitter. Thereafter, a silicon oxide film 139 is deposited on the entire surface, and a silicon oxide film 139 is formed by anisotropic dry etching. The polycrystalline silicon 137 is removed by isotropic dry etching, and the silicon oxide film 136 is removed by wet etching. A base tungsten lead electrode 140 and a collector tungsten 141 are formed on the exposed p-type polycrystalline silicon 135 by a selective CVD method. After that, a silicon oxide film 119 is deposited, and the silicon oxide film 119 of the tungsten electrode of the base and collector is opened by dry etching on the polycrystalline silicon electrode of the emitter, and the emitter electrode 120 of tungsten is formed by tungsten. A base electrode 1 2 1 and a collector electrode 1 2 2 are formed. With the above manufacturing method, the structure shown in FIG. 16 (b) is obtained.

In this embodiment, by using tungsten for the base extraction electrode, the resistance of the base extraction electrode is reduced to about 1/10 as compared with the first embodiment. In addition, a bipolar transistor with low power consumption can be formed. In this embodiment, an LOCOS oxide film can be used for element isolation as in the third embodiment, and an SO1 substrate can be used as in the second and fourth embodiments.

As described above, according to the bipolar transistor of the present invention, the base-collector capacitance is reduced, and the capacity between the collector and the substrate! : It is possible to reduce the resistance and further reduce the resistance of the base lead-out electrode, and it is possible to configure a bipolar transistor that can operate at high speed and high frequency. Therefore, by using the bipolar transistor according to the present invention particularly in a circuit or a system that requires a high-speed operation, it is possible to improve the performance of the entire circuit and the system.

FIG. 17 shows a sixth embodiment of the present invention. The circuit shown in FIG. 17 is a circuit diagram showing a frontal hunting circuit used in the optical transmission system. As is well known, an optical transmission system requires high-speed transmission of several tens of Gbps, and its pre-width circuit requires particularly high-speed operation. Therefore, by employing the transistor according to the present invention as a transistor constituting this amplifying circuit, the performance of the entire width circuit can be remarkably improved.

In FIG. 17, reference numeral 300 denotes a semiconductor integrated circuit that constitutes a pre-arm circuit formed on a single semiconductor substrate. PD is a photodiode that is a light receiving element that receives an optical signal transmitted through an optical transmission cable, and 303 is a power line and a grounding line. This is a depletion capacitor connected to the internal circuit and short-circuiting the AC component, and is externally provided outside the semiconductor circuit 300. The bipolar transistors Q1 and Q2 are bipolar transistors forming a wide-width circuit, and the above-described device having the structure of the present embodiment is applied. Diode D1 is a diode for level shift, which can be formed by using the bipolar transistor of the present invention and short-circuiting between the base and the collector. Diodes can also be applied in series. Rl, R2, and R3 are resistors. OUT is an output terminal, and an output buffer circuit is inserted between the output terminal and the emitter of the transistor Q2 as necessary.

In this embodiment, the optical signal transmitted through the optical transmission cable is converted into an electric signal by the photodiode PD, and the signal is transmitted through the input terminal IN of the semiconductor circuit 300 to the width transistors Q1 and Q2. It operates so that it is output from the output terminal OUT after being amplified by 2.

By using the semiconductor device manufactured according to the above embodiment, the present circuit has a margin of 40 GHz or more.

FIG. 18 shows a front end module of an optical transmission system in which the photodiode PD and the pre-width circuit 300 shown in FIG. 17 are integrated. In the figure, 401 is an optical fiber, 402 is a lens, 403 is a photodiode, and 404 is a semiconductor integrated circuit on which a preamplifier is formed. Reference numeral 407 denotes a substrate on which a photodiode and a preamplifier 404 are mounted, which is connected to an output amplifier 406 via a wiring 406 for connecting a diode and a louver. Have been. Reference numeral 408 denotes a hermetically sealed package such as a metal case. Although not shown, the substrate 407 also has the capacitor 303 shown in FIG. 17 mounted thereon. In this way, by configuring the front-end photodiode and pre-amplifier in the same module, the signal path can be shortened, making it difficult for noise to occur and reducing the parasitic L and C components. Can be suppressed.

This embodiment is an example in which the semiconductor device manufactured according to the above embodiment is used for the preamplifier circuit of the sixth embodiment, which is used as an integrated circuit chip, and is applied to a front end module. The optical signal input from the optical fiber 401 is passed through the lens 402. The light is condensed and converted to an S-gas signal by the photo diode IC 403. Electrical signal is on the board

The signal is amplified by the preamplifier IC 404 through the wiring 405 on 407 and output from the output terminal 406.

FIGS. 19 and 20 show system configuration diagrams of the optical transmission system using the front-end amplifier and the front end module shown in FIGS. 17 and 18. FIG. 19 shows a transmitting system 500 of the optical transmission system. The gas signal 501 to be transmitted is input to the multiplexer MUX and multiplexed into, for example, 4: 1 and the output signal is transmitted to the driver 502. The semiconductor laser LD always emits light of a constant intensity, and an external modulator driven by a driver 502

503 is configured to absorb or not absorb light according to the output of the driver 502 and transmit the light to the optical fiber 504. The transmission module shown in Fig. 19 is what is called an external modulation type. In this embodiment, instead of this, it is possible to employ a direct modulation type which directly controls the light emission of the semiconductor laser, but in general, the transmission by the external modulation type is performed by a trap. Suitable for high-speed, long-distance transmission with no spread of vector oscillation.

FIG. 20 shows an optical receiving module 510 of the optical transmission system according to the present embodiment.

In this figure, reference numeral 52 denotes a front-end module to which the embodiment of the present invention shown in FIGS. 17 and 18 can be applied. The electric signal amplified by the preamplifier 522 in the front end module is input to the main amplifier 530 and amplified. The main amplifier 530 is input to an automatic gain adjuster 531 that sweeps the output of the main amplifier 532 to keep the output constant, avoiding variations due to optical transmission distances and manufacturing deviations. It is configured to: It should be noted that, in addition to the configuration for adjusting the gain, a limit amplifier for limiting the output amplitude may be employed for the main amplifier. The Iffi classifier 540 is configured to perform 1-bit analog-to-digital conversion in synchronization with a predetermined clock, digitizes the output of the main amplifier section, and uses a separator DMUX to output, for example, 1: 4. The signal is input to a digital signal processing circuit 560 of the subsequent stage, and a predetermined process is performed.

The mouth extraction unit 550 is the operation timing of the separator 540 and the separator DMU X The output of the main amplifier section 530 is rectified by the full-wave rectifier 551, and is filtered by the narrow-band filter 552 to become a clock signal. Extract the signal. The output of the filter 552 is a phase shifter for matching the phase of the filter output and the analog signal, and delays the filter output based on a predetermined delay 1 :. In the optical communication system according to the present embodiment, a circuit can be configured using the transistor element having the above-described configuration at various points. Similarly, the circuit constituting the main amplifier 532 can be constituted by the circuit shown in FIG.

Since the semiconductor device S manufactured in accordance with the embodiment can operate at a very high cutoff frequency and a large cutoff frequency of 100 GHz, it is possible to transmit and receive a signal of a large capacity of 40 Gbits per second at a very high speed. it can. In addition, for circuits that conventionally require such high-speed operation, inexpensive silicon transistors can be used in circuits that need to use GaAs transistors, which have higher operating speeds than silicon bipolar transistors. Therefore, the cost of the entire system can be reduced. FIG. 21 is a configuration diagram of a mobile radio portable device according to a ninth embodiment of the present invention. In this embodiment, a semiconductor device manufactured according to the above embodiment is manufactured by using a mobile radio such as a low-noise gun 603, a synthesizer 606, a PLL (Phase Locked Loop) 611, or the like. This is an example applied to the circuits that make up each block of a hand-held device.

In this embodiment, the input from the antenna is amplified by the low-noise amplifier 603, the frequency emitted from the synthesizer 606 is oscillated from the oscillator 605, and the signal from the low-noise amplifier 603 is used by using the signal oscillated from the oscillator 605. The down-mixer 604 down-compensates to a lower frequency. Further, the frequency generated from the PLL 611 is oscillated from the oscillator 610, and the signal from the down mixer 604 is oscillated from the oscillator 610, and the lowering device 609 is used to handle the lower frequency. Signal processing is performed by the baseband unit 6 13. Also, the signal emitted from the baseband unit 613 is modulated by the transformer 612 using the signal from the PLL 611, and furthermore, the upmixer 608 converts the signal by the synthesizer 606. The signal is up-converted to a high frequency based on this signal, amplified by the power amplifier 607, and transmitted from the antenna 601. Reference numeral 602 denotes a switch for switching between transmission and reception of a signal. The switch receives a control signal (not shown) from the base unit 613 and controls its transmission and reception. Further, the baseband unit 6 13 is connected to a microphone (not shown), which is not shown in the drawing, and is capable of inputting and outputting audio signals.

The semiconductor device manufactured according to the above-described embodiment may be applied to each block of the present embodiment, in particular, to the low-noise amplifier 603, the synthesizer 606, and the PLL 611 to configure respective circuits. it can. Since the transistor according to the present invention can reduce the base resistance and the base collector capacitance, the low-noise gun 603, the synthesizer 606, and the PLL 611 reduce noise and reduce power consumption. Can be achieved. This makes it possible to realize a mobile wireless portable device that can be used for a long time with low noise as a whole system.

FIG. 22 is a circuit diagram of a D flip-flop used in a PLL prescaler of a mobile radio portable device according to a tenth embodiment of the present invention.

This embodiment is an example in which the semiconductor device g manufactured according to the above-described embodiment is used for the transistors 71 to 72 on the circuit of FIG.

The input signal, the close signal, and the output signal have only two states, high potential and low potential. The input signal and inverted input signal are input to terminals 7 19 and 7 20, respectively, and the clock signal and inverted clock signal are input to terminals 7 2 1 and 7 22, respectively.Terminals 7 2 3 and 7 An output signal and an inverted output signal are obtained from 24. The current paths flowing through the current sources 718 and 719 are switched to one of the transistors 709 and 710 and 711 and 712 by a clock signal, respectively. Further, the on / off of the transistors 701 to 706 is determined by an input signal, a short-circuit signal, and a potential at a lower end of the resistor generated by a current flowing through the resistors 713 and 714. In this circuit, the output signal outputs an input value when the peak signal changes from a low level to a high potential, and otherwise holds the previous input value.

The semiconductor device manufactured according to the above-described embodiment can reduce the base resistance and the base no-collector volume 1: so that the power consumption of PLL of the mobile wireless portable device can be reduced.

The present invention, as explained above, uses a base plug without increasing the base resistance. The transistor capacity can be reduced, and a transistor that operates at high speed with low power consumption can be obtained. Applying this to a wide-bandwidth circuit and peripheral circuits of an optical transmission system makes it possible to transmit and receive large-capacity signals at ultra-high speed. In addition, by applying this to a mobile wireless portable device, a mobile wireless portable device that has low noise and can be used for a long time can be obtained. Industrial applicability

As described above, the present invention can be applied to a bipolar transistor and various semiconductor integrated circuit devices using the same. For example, the present invention is applicable to a semiconductor integrated circuit device forming an optical transmission system or a mobile wireless terminal. Can be.

Claims

The first conductivity type semiconductor substrate and a first conductivity type second conductivity type opposite to the first conductivity type and the opposite conductivity type second conductivity type formed in contact with the main surface of the semiconductor body. A semiconductor region, a second semiconductor region of a first conductivity type formed in the first semiconductor region, and a polycrystalline semiconductor layer deposited on the semiconductor substrate via an insulating film; A semiconductor device, wherein the semiconductor layer is configured so as to be connected to the first semiconductor region on a side surface thereof. The semiconductor device according to claim 1, wherein the semiconductor substrate is a collector region of a bipolar transistor, the first semiconductor region is a base region, and the second semiconductor region is an emitter region. Semiconductor device. 3. The semiconductor device according to claim 2, wherein said first semiconductor region is made of silicon-germanium. 3. The semiconductor device according to claim 2, wherein said polycrystalline semiconductor layer is a base lead electrode made of polycrystalline silicon. 2. The semiconductor device according to claim 1, wherein the bottom shape of the first semiconductor region is defined by the perfect opening. The first semiconductor region is made of trapezoidal single-crystal silicon whose bottom surface is defined by the opening of the insulating film, and the polycrystalline semiconductor layer is formed of the trapezoidal first semiconductor. 2. The semiconductor device according to claim 1, wherein the semiconductor device is configured to be connected to an inclined surface of the region. A semiconductor substrate; a first semiconductor region of a first conductivity type formed on the semiconductor substrate; a second semiconductor region of a second conductivity type having a conductivity type opposite to the first conductivity type; A third semiconductor region of a first conductivity type formed in the first semiconductor region; and a first wiring layer, wherein the second semiconductor region is located on a main surface of the first semiconductor region. A semiconductor device, wherein the first wiring layer is formed, and is formed on the first semiconductor region via an insulating film formed on a main surface of the first semiconductor region. The first conductivity type is n-type, the second conductivity type is p-type, and the semiconductor device is bipolar by the first semiconductor region, the second semiconductor region, and the third semiconductor region. 8. The semiconductor device according to claim 7, wherein a transistor is configured. 9. The semiconductor device according to claim 8, wherein said second semiconductor region is constituted by a single crystal silicon deposited on a main surface of said first semiconductor region. . 0. The insulating film is formed of silicon oxide, and the first wiring layer is configured such that the bottom surface is in contact with the insulating film and a second insulating film formed of silicon nitride. 9. The semiconductor device according to claim 8, wherein

1. a first semiconductor region of a first conductivity type;

A second semiconductor region of a second conductivity type deposited on the main surface of the first semiconductor region;

A third semiconductor region of the first conductivity type formed in the second semiconductor region; and a first insulator having a first opening formed on a main surface of the first semiconductor region. ,

A second insulating film formed on the first insulating film and having a second opening having an opening area larger than that of the first opening;

A wiring layer formed in contact with the second semiconductor region,

The bottom surface of the second semiconductor region is defined by the first opening, the wiring layer is connected to the first insulating film by the second opening, and the first opening Wherein the semiconductor device is connected to the second semiconductor region.

2. The first semiconductor region is a collector region of the bipolar transistor, the second semiconductor region is a base region of the bipolar transistor, and the third semiconductor region is an emitter region of the bipolar transistor. The semiconductor device according to claim 11, wherein:

3. The semiconductor device according to claim 11, wherein the first insulating film is an oxide film, and the second insulating film is a nitride film.

4. a first step of forming a first insulating film on a surface of a semiconductor substrate of a first conductivity type formed on a semiconductor substrate;

A second step of forming a second insulating film on the first insulating film;

A third step of forming a first conductor layer on the second insulating film,

A fourth step of forming a first opening by etching the first conductor layer and the second insulator;

A fifth step of forming a second opening by selectively etching the second insulating film through the first opening;

A sixth step of filling the second opening with semiconductor material by depositing a semiconductor material through the first opening;

A seventh step of etching the first insulating film through the first opening until the surface of the semiconductor substrate is exposed to β;

An eighth step of selectively depositing a semiconductor material on the surface of the semiconductor substrate through the first opening until the semiconductor material is brought into contact with the semiconductor material filling the second opening. A method for manufacturing a semiconductor device.

5. The semiconductor region of the first conductivity type is a collector region of the bipolar transistor, and the semiconductor material deposited in the eighth step forms a base region of the bipolar transistor. 15. The method for manufacturing a semiconductor device according to claim 14, further comprising a step of forming an emitter region of a bipolar transistor after the step.

6. The method for manufacturing a semiconductor device according to claim 14, wherein the first insulating film has a larger etching selectivity than the second insulating film.

7. The method of manufacturing a semiconductor device according to claim 15, further comprising, after the fourth step, a step of forming a sidewall oxide film covering a side surface of the first conductor layer. .

8. After the eighth step,

Impurities are included to connect with the semiconductor material deposited in the eighth step. 18. The method according to claim 17, wherein the step of forming the second conductive layer has a step of forming a semiconductor region serving as an emitter electrode of the bipolar transistor by diffusing impurities from the second conductive layer. A manufacturing method of the semiconductor device g described above.

9. A step of forming a front body in which a first conductor layer having a first opening is laminated on a main surface of a single crystal semiconductor substrate through a first insulator;

Selectively depositing a semiconductor material on the main surface of the semiconductor substrate from the first opening to form a first semiconductor region, and connecting with the first conductor layer; Forming a second conductive layer containing impurities on the semiconductor region;

Forming a second semiconductor region by diffusing impurities from the second conductor layer into the first semiconductor region.

10. The method of manufacturing a semiconductor device according to claim 19, wherein the step of contacting with the first conductor layer is a step of selectively and epitaxially growing a semiconductor material on the surface of the semiconductor substrate. Method.

1. A semiconductor device having a first bipolar transistor having a light receiving element connected to its base,

The first bipolar transistor is

A first conductivity type semiconductor substrate serving as a collector region;

A first semiconductor region of a second conductivity type having a conductivity type opposite to the first conductivity type formed in contact with a main surface portion of the semiconductor substrate;

A second semiconductor region of a first conductivity type formed in the first semiconductor region; and a polycrystalline semiconductor layer deposited on the semiconductor substrate via an insulating film. The castle is a base region of the bipolar transistor, the second semiconductor region is an emitter region of the bipolar transistor,

A semiconductor device, wherein the polycrystalline semiconductor layer is formed so as to be connected to the first semiconductor region on a side surface thereof.

2. The base of the second bipolar transistor is connected to the collector of the first bipolar transistor, and the first and second bipolar transistors are connected to the collector of the first bipolar transistor. While being formed on the same semiconductor substrate,

The second bipolar transistor is

A first conductive type second semiconductor region of opposite conductivity type to the first conductivity type formed in contact with the main surface of the semiconductor substrate;

A second semiconductor region of a first conductivity type formed in the first semiconductor region; and a polycrystalline semiconductor layer deposited on the semiconductor substrate via an insulating film, wherein the first semiconductor region Is a base region of the bipolar transistor, the second semiconductor region is an emitter region of the bipolar transistor,

22. The semiconductor device according to claim 21, wherein said polycrystalline semiconductor layer is formed so as to be connected to said first semiconductor region on a side surface thereof.

3. A light receiving element that receives an optical signal and outputs an electric signal,

A first width circuit that receives an air signal from the light receiving element;

A second width circuit receiving an output of the first width circuit;

An optical receiving system comprising: a starving device that converts an output of the second bandwidth circuit into a digital signal in synchronization with a predetermined peak signal;

The first tongue circuit includes a first bipolar transistor having a base connected to the light receiving element, a base connected to a collector of the first bipolar transistor, and a collector connected to the first bipolar transistor. A second bipolar transistor connected to the input of the two hunting circuits,

At least one of the first and second bipolar transistors is constituted by a semiconductor device according to any one of claims 1, 7, and 11. Light receiving system.

4. A light characterized in that each of the first and second bipolar transistors is constituted by the semiconductor device according to any one of claims 1, 7, and 11. Receiving system.

5. The optical receiving system, wherein the second and second bipolar transistors are formed on a single semiconductor chip, and the light receiving element and the semiconductor chip are mounted on a single substrate.