JP4966949B2 - Semiconductor device, manufacturing method thereof, and superheterodyne communication device using the semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, and a superheterodyne communication device using the semiconductor device, and more particularly to a technique effective when applied to a semiconductor device having a bipolar transistor.

  In recent years, bipolar transistors having high-speed performance have been used in various application fields such as communication devices and storage systems. As a conventional high-speed bipolar transistor, for example, Patent Document 1 discloses a transistor example using single crystal silicon / germanium as an intrinsic base layer using an epitaxial growth technique.

Further, in Patent Document 2, in a bipolar transistor in which an emitter and a base are formed in a self-aligned manner, an emitter layer made of single crystal silicon is formed by an epitaxial growth technique in addition to a base using single crystal silicon / germanium. in the structure of the bipolar transistor is disclosed to improve the junction breakdown voltage between the cut-off frequency f _T and the collector-base at the same time.

  Furthermore, in the second embodiment of Patent Document 3, a low-concentration emitter layer exists between the base layer and the emitter layer, and the base layer to the emitter layer are continuously formed by an epitaxial growth technique to thereby form the base layer. A method for manufacturing a semiconductor device is disclosed, which does not require heat treatment at a high temperature that affects the diffusion of impurities in the semiconductor device and can reduce the emitter resistance.

  In Patent Document 4, a low-concentration emitter layer exists between the base layer and the emitter layer, and the low-concentration emitter layer is formed by a selective epitaxial growth technique, thereby increasing leakage current at the base-collector junction. A method for manufacturing a heterobipolar transistor that can prevent an increase in the thickness of the layer and that can reduce the base resistance in the link base region as compared with the related art is disclosed.

  Furthermore, in Patent Document 5, in a bipolar transistor in which a base and an emitter are continuously formed by epitaxial growth, an emitter layer is formed by selective epitaxial growth so as not to contact a peripheral insulating film, thereby forming an emitter-base junction. A manufacturing method that suppresses the occurrence of leakage current accompanying deterioration of crystallinity is disclosed.

JP-A-7-147287 JP-A-5-299429 JP-A-11-214401 Japanese Patent Laid-Open No. 7-31371 JP 2004-193454 A

  In recent years, communication devices are required to improve high-speed performance that can cope with an increase in the amount of data and to reduce power consumption accompanying the spread of mobile devices such as mobile phones. Along with this, the bipolar transistor incorporated in the communication circuit is required to simultaneously improve the cutoff frequency and the low current drive performance. In order to satisfy these two requirements at the same time, it is necessary to reduce both the base travel time, which controls the speed of high-speed operation, and the charge / discharge time of the carrier at the emitter-base junction, which most affects the transistor operating speed at low current. There is a need.

  FIG. 2 shows a cross-sectional structure of a transistor in which single crystal silicon germanium described in Patent Document 1 is used for an intrinsic base layer. A high-concentration n-type buried layer 102, a collector 103 made of low-concentration n-type silicon, and an element isolation insulating film 104 are formed on a semiconductor substrate 101, and the upper part is surrounded by a collector / base isolation insulating film 105. A collector 109 made of low-concentration n-type silicon / germanium and a base 110 made of p-type silicon / germanium are formed. The base 110 is connected to a base electrode 106 made of polycrystalline silicon by a connecting base electrode 111 made of a polycrystalline p-type silicon / germanium layer.

  An insulating film 108 for separating the base and the emitter is formed on the base 110 and connected to the base electrode 106 made of polycrystalline p-type silicon / germanium. An insulating film 108 for separating the base and the emitter is formed on the base 110, and an emitter electrode 113 made of high-concentration n-type polycrystalline silicon is formed in the opening surrounded by the insulating film 108. . In FIG. 2, 115 is a high-concentration n-type collector lead electrode, 116a to 1116c are metal electrodes, and 107 is an emitter-base isolation insulating film.

  The emitter 112 is formed in the base 110 by impurity diffusion from the emitter electrode 113. In the above conventional example, since the silicon / germanium base layer is formed by epitaxial growth, the composition ratio of germanium can be easily controlled, and the internal electric field into the base can be controlled by changing the germanium composition ratio. Application is possible.

  Therefore, it is possible to increase the drift electric field of a silicon heterojunction bipolar transistor having a SiGe collector, improve the carrier mobility in the base layer, and increase the speed by accelerating the base-collector junction region carriers. Have

  As a second conventional example using single crystal silicon / germanium for the intrinsic base layer, a transistor described in Patent Document 2 can be given.

  FIG. 3 shows a sectional structure of the second conventional example. 3 is different from FIG. 2 in that the emitter 212 is formed above the base 210 and in an opening surrounded by an insulating film 208 that separates the base and the emitter. This conventional example is characterized in that the emitter 212 is formed by epitaxial growth of high-concentration n-type silicon. The thermal load before and after the epitaxial growth can be made sufficiently smaller than that in the case of the impurity diffusion described in Patent Document 1. Therefore, impurity diffusion in the base 210 can be suppressed, and a thin film base that is advantageous for increasing the speed of the transistor can be formed.

  In FIG. 3, 213 is an emitter electrode, 216a to 216c are metal electrodes, 215 is a high-concentration n-type collector lead electrode, 202 is a high-concentration n-type buried layer, and 207 is an emitter-base isolation insulating film. is there.

  As another example of a bipolar transistor having an emitter formed by epitaxial growth, there is a transistor described in Patent Document 3. FIG. 4 shows the cross-sectional structure. This conventional example is characterized in that an emitter composed of single crystal n-type silicon is composed of two layers of an emitter 312 and an emitter 313, and the impurity concentration of the emitter 312 is lower than the impurity concentration of the emitter 313. Have. By inserting the low-concentration emitter 312 between the high-concentration emitter 313 and the base 310, formation of a high-concentration emitter-base junction can be prevented, and current leakage due to the carrier tunnel effect can be suppressed. Has the advantage. In FIG. 4, 308 is an insulating film for separating the base and emitter, 305 is a collector-base separating insulating film, 307 is an emitter-base separating insulating film, 306 is a base extraction electrode, 316 is a high-concentration n-type layer, 315 is an interlayer insulating film, 314 is an emitter electrode (high-concentration n-type polycrystalline silicon), and 317a to 317c are metal electrodes.

As another example of a bipolar transistor using a low-concentration emitter layer between an emitter layer and a base layer, there is a transistor described in Patent Document 4. This transistor is characterized in that a link base layer formed on the base is opened, and a low-concentration emitter layer is formed therein by selective growth. Since the low-concentration emitter layer can suppress the occurrence of a high-concentration junction between the emitter layer and the link base layer, the link base layer can be formed while keeping the base layer thin, and high-speed performance can be achieved. The base resistance can be reduced.
Patent Document 5 describes an example in which a bipolar transistor having an emitter formed by epitaxial growth is formed by a selective growth method so that the emitter is not in contact with the insulating film. Unlike the case where the emitter is grown along the insulating film, it is possible to suppress the generation of dangling bonds that cause the base current leakage, and the effect of improving the breakdown voltage can be obtained.

  From the above viewpoint of achieving both shortening of the base transit time and reduction of the charge / discharge time of the carrier at the emitter-base junction that has the greatest influence on the transistor operating speed at a low current, the conventional bipolar transistor is first shown in FIG. In the example shown, there is a concern about an increase in base width due to impurity diffusion when the emitter 112 is formed.

  The impurity diffusion is performed, for example, by performing a heat treatment for about 10 seconds at a temperature of 850 to 900 degrees. At this time, boron, which is an impurity of the base, is also diffused at the same time, and the base width increases toward the collector side. Therefore, there has been a problem that the base travel time of the carrier is increased and the high speed operation of the transistor is hindered.

  Next, in the conventional example shown in FIG. 3, since the emitter is formed by epitaxial growth, the load can be significantly reduced compared to the example of FIG. 2, and a transistor with a short base running time can be manufactured.

  However, since the high impurity concentration emitter is directly grown on the high impurity concentration base, a high concentration emitter-base junction is formed, and the emitter-base junction capacitance is increased. This increases the charge / discharge time of carriers in the emitter-base junction, and causes a problem that high-speed operation of the transistor at low current becomes difficult.

  There is also concern about the occurrence of current leakage due to the carrier tunnel effect due to the high-concentration junction.

  In FIG. 4 showing the cross-sectional structure of Patent Document 3, a low-concentration n-type silicon layer is formed between an emitter 313 composed of high-concentration n-type silicon and a base 310 composed of high-concentration p-type silicon / germanium. Therefore, tunnel current leakage can be suppressed. However, since the low-concentration emitter 312 grows in contact with the insulating film 308, a large number of carrier recombination levels exist at the silicon / insulating film interface due to the reaction between the dangling bond of silicon and the insulating film. To do. When the low-concentration emitter 312 is completely depleted in order to reduce the emitter-base junction capacitance, a large number of recombination levels exist in the depletion layer, which may cause a base current leak.

  Patent Document 4 has a structure obtained by growing a low-concentration emitter along an insulating film, and has the same problem.

  In Patent Document 5, in order to suppress current leakage, the emitter layer is formed so as not to contact the insulating film. Taking FIG. 3 as an example, the surface of the base layer 210 is always lower than the lower surface of the insulating film 208. It is required to be located above. For this reason, the base layer cannot be made thinner than a certain thickness, and the base running time cannot be reduced. Further, since the gap generated between the emitter layer and the insulating film 208 is covered with another insulating film, the area of the emitter electrode is reduced and the emitter resistance is also increased.

  The present invention has been made in consideration of the above-mentioned various problems. The object of the present invention is to reduce the base transit time and the emitter-base junction capacitance in the bipolar transistor, that is, to improve the cutoff frequency. An object of the present invention is to provide a semiconductor device that can improve low-current driving performance and realize good transistor operation characteristics without leakage current, and a method for manufacturing the same.

  In order to solve the above problems, a semiconductor device according to the present invention includes a first semiconductor layer of a first conductivity type provided on a semiconductor substrate, and a first conductivity type provided on the first semiconductor layer. The second semiconductor layer, the second semiconductor layer of the second conductivity type provided on the second semiconductor layer, and the first semiconductor layer provided on the third semiconductor layer and having an opening. An insulating film; a first conductive type fourth semiconductor layer provided in the opening; and a first conductive type fifth semiconductor layer provided on the fourth semiconductor layer. The impurity concentration of the fourth semiconductor layer is lower than that of the fifth semiconductor layer, and the fourth semiconductor layer is formed so as not to contact the sidewall of the first insulating film, and at least the fourth semiconductor layer is formed. It is characterized by having a cavity surrounded by a layer and the first insulating film.

  The semiconductor device according to the present invention further includes a second insulating film provided on the first insulating film and having an opening narrower than the first insulating film, and at least the fourth semiconductor layer and the It is desirable to have a cavity surrounded by the first insulating film. The fourth semiconductor layer has a predetermined oblique facet surface starting from an edge of the lower surface of the first insulating film, and the facet surface is (111) or (311). Is preferred. Furthermore, in the semiconductor device according to the present invention, the first semiconductor layer and the second semiconductor layer are the collector, the third semiconductor layer is the base, and the fourth semiconductor layer and the fifth semiconductor layer are the emitter. Preferably, the first semiconductor layer is made of single crystal silicon, single crystal silicon germanium, or single crystal silicon germanium carbon, and the second semiconductor layer and the base are More preferably, it is made of single crystal silicon / germanium or single crystal silicon / germanium / carbon.

  Preferably, the first insulating film is a silicon oxide film, and the second insulating film is a silicon nitride film. The forbidden band width in the third semiconductor layer decreases stepwise or continuously as it goes from the fourth semiconductor layer toward the second semiconductor layer.

  A method of manufacturing a semiconductor device according to the present invention includes a step of forming a first conductive type first semiconductor layer on a semiconductor substrate, and a first conductive type second semiconductor layer on the first semiconductor layer. Forming a second conductive type third semiconductor layer on the second semiconductor layer, forming a first insulating film on the third semiconductor layer, Forming an opening in the first insulating film; forming a first conductivity type fourth semiconductor layer in the opening; and a first conductivity type fifth on the fourth semiconductor layer. Forming a semiconductor layer, wherein the impurity concentration of the fourth semiconductor layer is lower than the impurity concentration of the fifth semiconductor layer, and at least the fourth semiconductor layer and the first insulating film A cavity surrounded by is formed.

  A step of forming the second insulating film on the first insulating film; and a step of forming an opening in the second insulating film, wherein the second insulating film is surrounded by the second insulating film. It is preferable that the opening has a smaller diameter than the opening surrounded by the first insulating film.

  According to the semiconductor device and the method of manufacturing the same according to the present invention, it is possible to provide a bipolar transistor that can shorten the base travel time and reduce the emitter-base junction capacitance, and is excellent in high speed performance and low power drive performance. .

  Preferred embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described below in detail using specific examples with reference to the accompanying drawings.

  FIG. 1 is a cross-sectional structure showing a first embodiment of a semiconductor device according to the present invention. In FIG. 1, reference numeral 1 indicates a silicon substrate, and 2 indicates a collector buried layer made of high impurity concentration n-type silicon formed on the silicon substrate. Reference numerals 3 and 4 respectively denote an element isolation insulating film and a collector-base isolation insulating film. On the collector buried layer 2 and the collector-base insulating film 4, a collector 5 made of low-concentration n-type silicon or silicon germanium is provided. A collector 6 made of low-concentration n-type silicon / germanium and a base 7 made of p-type silicon / germanium are sequentially formed. These three layers have a single crystal state on the collector buried layer 2 and a polycrystalline state on the collector-base isolation insulating film 4. An emitter-base isolation insulating film 9 having an opening is formed on the base layer 7, and an insulating film 10 is also formed on the insulating film 9 with an opening. Here, the opening of the insulating film 10 is narrower than the opening of the insulating film 9, and the insulating film 10 forms a ridge with the insulating film 9.

The broken line shown in cross-sectional structural view of FIG. 1 has p ⁺ turned into an ion implantation of p-type impurity layer and the n ^- represents the boundary between the phased layer. 8 (b)-(c), FIG. 9 (a)-(c), FIG. 14, FIG. 15, FIG. 17, FIG. 17, 18, FIG. 19 (a)-(b) and FIG. Similar boundaries are shown.

  A high-concentration p-type region 8 is formed outside the opening, that is, the external base region by ion implantation of p-type impurities such as boron, and serves as a base lead electrode.

  An emitter 11 made of low impurity concentration n-type silicon or silicon-germanium is formed in the opening on the base 7. As shown in FIG. 18, the emitter 11 is formed with facets obliquely from the edge of the bottom surface of the insulating film 9, and is in contact with the insulating film 10 on the bottom surface of the ridge. Therefore, the emitter 11 forms a cavity 12 between the insulating film 9 and the insulating film 10.

  On the low-concentration emitter 11 and the insulating film 10, respectively, an emitter 13 made of n-type single crystal silicon or silicon-germanium with a high impurity concentration and n-type polycrystalline silicon or silicon-germanium with a high impurity concentration are formed. An emitter electrode 14 is formed.

  This embodiment is characterized in that the low-concentration emitter 11 is formed without being in contact with the insulating film 10 and further has a stable surface such as (111) or (311) in the facet. For this reason, the low-concentration emitter 11 is a single-crystal region having no carrier trap levels due to an irregular atomic arrangement and no carrier recombination levels due to dangling bonds formed by reaction with an oxide film. Thus, even in the case of complete depletion, the occurrence of current leakage due to carrier recombination can be greatly suppressed.

  In addition, since the emitter 11 has an inclined facet shape and further includes a cavity, the emitter 11 is formed in contact with the insulating film 10 or the gap between the emitter 11 and the insulating film 10 is filled with the insulating film. Compared to the above, it is possible to reduce the emitter-base junction capacitance.

  FIG. 5 shows the impurity concentration (FIG. 5A) and the distribution of germanium composition ratio (FIG. 5B) in the main part of the transistor. The horizontal axes of FIGS. 9A and 9B are shown in a uniform manner, and it is easy to understand the correspondence between the germanium distribution and the impurity concentration.

In this embodiment, the germanium composition ratio of the p-type silicon / germanium base and the low-concentration n-type silicon / germanium collector is about 15%. The impurity concentration of the high-concentration n-type emitter and the base is about 1 × 10 ¹⁹ cm ⁻³ to 2 × 10 ²⁰ cm ⁻³ , and the impurity concentrations of the low-concentration n-type emitter and the low-concentration n-type collector are It is desirable to set it to about 5 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ . When the impurity concentration of the low-concentration n-type emitter is 1 × 10 ¹⁸ cm ⁻³ or less, the low-concentration emitter 11 having a thickness of about 15 nm can be completely depleted even when a forward bias of about 1 V is applied. In this case, the emitter-base junction concentration per unit area can be reduced from 1/3 to 1/5, compared with the case where the low-concentration emitter 11 is not provided.

  FIG. 6 shows the reciprocal of the cutoff frequency at different collector current densities. The reciprocal ½ · fT of the cutoff frequency is determined by a plurality of time constants as represented by the following equation.

ここで、τＢ、τＥ、τＣは、それぞれベース、エミッタ−ベース間空乏層、及びコレクタ−ベース間空乏層のキャリア走行時間を表し、τＣ_＿chargeとτE_＿chargeは、それぞれエミッタ−ベース間空乏層とコレクタ−ベース間空乏層のキャリアの充放電時間を表している。

Here, τB, τE, τC the base respectively, the emitter - base between the depletion layer, and the collector - represents a carrier transit time of the depletion layer between the base, .tau.C _{_Charge} and _τE _charge each emitter - base between the depletion layer and the collector -Represents the charge / discharge time of carriers in the depletion layer between bases.

and τC_ _charge, τE_ _charge each emitter - base between the depletion layer, TauCR the collector - base junction capacitance and collector resistance, a time constant determined by the emitter resistor. When the collector current density is high, that is, as shown in FIG. 6A, the base travel time τB can be reduced by applying the technique of the present invention, and the total time constant is reduced.

In contrast, when the collector current density shown in FIG. 6 (b) is _low, τE _charge which accounted for most of the prior art time constant, have been significantly reduced by the technique applied in the present invention, this It can be seen that the reduction in _{τE_charge} reduces the total time constant. That is, the cutoff frequency can be improved in a wide collector current density range by reducing the time constant that varies depending on the collector current density.

  FIG. 7 is a plot of the cut-off frequency fT against the collector current density. The characteristic line A shows the result obtained by applying the technology of the present invention, and the characteristic line B shows a conventional example. From the figure, in the wide frequency range, the collector current density is reduced from about 1/3 to 1/5 of the characteristic line A compared to the characteristic line B of the conventional example, showing the effect of the present invention. ing.

  Next, with reference to FIGS. 8A to 8F and FIGS. 9D to 9F, a specific method for manufacturing the semiconductor device in this embodiment will be described in detail.

  First, a high-concentration n-type single crystal silicon layer 2 containing arsenic, antimony, or phosphorus as an impurity is formed on a silicon substrate 1. The high-concentration silicon layer may be deposited on the silicon substrate 1 by epitaxial growth or may be formed by an ion implantation method.

  Next, except for the transistor formation region and the collector lead electrode region, an insulating film 3 made of, for example, a silicon oxide film is selectively formed and element isolation is performed to obtain the structure shown in FIG. As a method for forming the element isolation structure, the silicon layer may be selectively oxidized, or the element isolation region is etched (for example, using a dry etching method), and the insulating film 3 is embedded to perform chemical mechanical polishing. The surface may be planarized by (Chemical Mechanical Polishing: CMP) or the like. Further, it is also possible to deposit the insulating film 3 on the silicon substrate and form the high-concentration silicon layer 2 selectively by epitaxial growth or the like after forming the opening.

  Next, a collector-base isolation insulating film 4 is deposited on the entire surface, and an opening is formed in the transistor intrinsic part formation region by a technique such as dry etching or wet etching.

  The insulating film 4 is preferably a silicon oxide film or a silicon nitride film, but may be a laminated film of a silicon oxide film and a silicon nitride film.

  Next, a collector 5 made of low-concentration n-type silicon or silicon germanium containing phosphorus or arsenic as an impurity, a collector 6 made of low-concentration n-type silicon germanium containing phosphorus or arsenic as an impurity, and boron, for example, as impurities The base 7 made of p-type silicon / germanium was sequentially deposited by epitaxial growth or the like. At this time, the three layers have a single crystal state in the opening and a polycrystalline state on the insulating film 4.

  Next, a p-type impurity such as boron is implanted outside the emitter formation region to form a high-concentration p-type base electrode region 8, thereby obtaining the structure shown in FIG. 8B.

  Next, an insulating film 9 and an insulating film 10 are deposited on the structure of FIG. 8B, and an opening corresponding to the emitter formation region is processed in the insulating film 9 to obtain the structure shown in FIG. .

  At this time, for example, the insulating film 9 is preferably a silicon oxide film and the insulating film 10 is preferably a silicon nitride film, and the opening is preferably processed using an anisotropic etching method such as dry etching.

  From the structure of FIG. 8C, the insulating film 9 is processed as shown in FIG. 9A by isotropic etching such as wet etching. At this time, for example, when the insulating film 9 is made of a silicon oxide film and the insulating film 10 is made of a silicon nitride film, hydrofluoric acid may be used as an etchant, and the insulating film 9 is made of a silicon nitride film and is insulated. When the film 10 is composed of a silicon oxide film, the structure shown in FIG. 9A can be obtained by using about 160 ° phosphoric acid.

  Next, an emitter 11 made of low-concentration n-type silicon or silicon-germanium containing phosphorus or arsenic as an impurity is selectively formed in the opening formed by the insulating film 9 and the insulating film 10 by epitaxial growth or the like. As a result, the structure shown in FIG. Here, by adjusting the growth conditions, the emitter 11 is formed to have a (111) or (311) facet on the side wall, and the lower surface of the insulating film 10 exposed in a bowl shape and the upper surface of the emitter 11 are in contact with each other. Since the size adjustment is performed, a cavity 12 surrounded by the emitter 11, the insulating film 9, and the insulating film 10 is formed.

  Here, the growth method for obtaining the emitter 11 shown in FIG. 9B will be described in detail.

  The crystal growth of the emitter 11 is performed by a gas source molecular beam epitaxy (MBE) method, a chemical vapor deposition (CVD) method, or the like. In the present invention, it is required to reduce the thermal load in the growth process and to improve the growth selectivity on the silicon substrate and the insulating film.

  First, as a main thermal load in the growth process, there is a cleaning process in which the substrate is heated before growth to remove a natural oxide film on the surface of the substrate. In order to reduce the thermal load in the cleaning process, it is effective to superheat the substrate by adding molecular or atomic hydrogen during cleaning. Thereby, the reduction reaction is promoted, and oxygen can be desorbed even at a low substrate temperature. For example, 10 ml / min. By adding the above hydrogen, the interface oxygen concentration can be suppressed to a low value even when the cleaning temperature is reduced to 750 ° C. and the cleaning time is reduced to 2 minutes. The silicon selection ratio with respect to the insulating film during crystal growth can be maintained at a high value by optimizing the temperature, gas flow rate, and pressure in the growth chamber in accordance with the source gas used.

  FIGS. 10 and 11 show the selectivity to the insulating film when disilane (Si2H6) and monosilane (SiH4) are used as the silicon source gas in the silicon crystal growth using the chemical vapor deposition method, respectively. This shows the relationship between the maximum possible film thickness and the germanium composition ratio. 10 uses Si2H6 and the gas flow rate is 2 ml / min. This is the case where the growth temperature is 550 ° C. and the growth pressure is 1 Pa. When the Ge composition ratio is 0, that is, single crystal Si, the maximum thickness of silicon that can be grown without being deposited on the silicon oxide film and the silicon nitride film is about 30 nm.

  As described above, the low-concentration emitter film thickness for reducing the carrier charge / discharge time of the emitter-base depletion layer is sufficient if it is 15 nm. Therefore, the low power driving performance of the transistor can be improved under the conditions shown in FIG. is there. FIG. 11 uses SiH4 and the gas flow rate is 10 ml / min. In this case, the growth temperature is 700 degrees and the growth pressure is 1000 Pa. SiH4 requires a slightly higher temperature because it has a higher activation energy than Si2H6, but the selectivity is improved accordingly, and a silicon emitter that can grow without being deposited on the silicon oxide film and silicon nitride film. The maximum film thickness is about 150 nm. As described above, since the optimum growth conditions and the maximum film thickness of silicon that can be selectively grown differ depending on the source gas, it is preferable to use different conditions depending on the desired transistor performance. For example, when importance is attached to the high-speed performance of a transistor, Si2H6 that can be processed at a lower growth temperature is used, and when low-current drive performance is important, a large margin is provided for the maximum film thickness of silicon that can be selectively grown. It is preferable to use SiH4 that can be maintained. After forming the low-concentration silicon emitter layer 11 shown in FIG. 9B, an emitter 13 made of high-concentration n-type single crystal silicon or silicon-germanium using phosphorus or arsenic as an impurity is grown. At this time, the growth conditions are adjusted so that the emitter 14 made of high-concentration n-type polycrystalline silicon or silicon-germanium grows simultaneously on the insulating film 10, that is, non-selective growth.

  In order to deposit polycrystalline silicon on the insulating film, it is effective to lower the growth temperature and increase the growth pressure. The structure shown in FIG. 9C is obtained by adjusting the growth conditions. Thereafter, the emitter electrode 14 and the base lead electrode 8 are processed, an insulating film 15 is formed on the side wall, an interlayer insulating film 16 is deposited on the entire surface, and the surface is flattened. Finally, the base lead electrode 8 and the emitter are formed. When the electrodes 14 and the surface portions of the high-concentration n-type silicon layer 2 are opened to form the metal electrodes 17a, 17b, and 17c, the structure shown in FIG. 1 is obtained.

  In this embodiment, in order to reduce the spread of the base width in the base layer 9 caused by the redistribution of impurities due to the heat treatment during emitter formation, one of the collector layer 6, the base layer 7, and the low-concentration emitter layer 11 is reduced. Carbon may be added to the part. The same applies to these layers in the following examples.

  12A and 12B are diagrams showing a second embodiment of the semiconductor device according to the present invention. FIG. 12A shows the distribution of impurity concentration, and FIG. 12B shows the distribution of germanium composition ratio. It is. The present embodiment is characterized in that the p-type base (between D2 and D3) includes a region where the Ge composition ratio increases stepwise as it goes from the emitter to the collector. When the Ge composition ratio increases in the base, an electric field from the emitter to the collector is generated, and electrons, which are minority carriers traveling in the base, are accelerated, and the base traveling time is shortened.

  This embodiment is obtained by changing the Ge composition ratio in the embodiment shown in FIG. 1, and can be applied to all the embodiments of the present invention.

  13A and 13B are diagrams showing a third embodiment of the semiconductor device according to the present invention. FIG. 13A shows the impurity concentration distribution, and FIG. 13B shows the germanium composition ratio distribution. Is. The feature shown in FIG. 13 is that the germanium composition ratio of the low-concentration n-type emitter layer (between D1 and D2) is a finite value. Here, the germanium composition ratio in the low-concentration n-type emitter is about 3 to 5%, and the germanium composition ratio between the base layer and the low-concentration collector layer is about 10 to 15%. In this embodiment, the low-concentration emitter is made of silicon germanium having higher selectivity with respect to the insulating film, so that the thickness of the low-concentration emitter can be increased and the emitter-base capacitance can be further reduced. is there.

In addition, when the low-concentration emitter layer is made of silicon-germanium having a narrow forbidden band width compared to silicon, an energy barrier can be formed against holes directed from the low-concentration emitter to the high-concentration emitter. By forming a heterojunction consisting of a silicon-germanium / silicon interface near the depletion layer / emitter interface in the n-type region, all the difference in the forbidden band width can be used as a barrier for valence electrons, so at least due to holes In terms of current suppression, it is more efficient than forming a heterojunction near the pn junction.
For this reason, by applying this embodiment, the base current can be further reduced and the current gain can be improved. Since this embodiment is obtained by changing the composition ratio of Ge in the embodiment shown in FIG. 1, it can be applied to all the embodiments in the present invention. In particular, by combining with the germanium profile of Example 2, both the current gain and the cut-off frequency fT can be improved.

FIG. 14 is a cross-sectional view of a semiconductor device showing a fourth embodiment according to the present invention. This embodiment is characterized in that an n-type region 18 is formed by ion implantation of arsenic or phosphorus in the region of the low concentration collectors 6 and 7 immediately below the emitter. The ion implantation is desirably performed in the state shown in FIG. 9D described in the manufacturing process of the first embodiment. In this case, ions are implanted into the region of the emitter opening. By adjusting the impurity concentration of the ion implantation region 18 to 5 × 10 ¹⁷ cm ^{−3 to} 3 × 10 ¹⁸ cm ⁻³ , the Kirk effect at the time of applying a high current can be suppressed, The peak value of the cutoff frequency can be improved.

  This embodiment is effective when transistor operation at a higher frequency is required, and since the presence or absence of implementation can be selected for each transistor, the performance of the transistor can be adjusted according to the application. There are advantages. Needless to say, the present embodiment is applicable to all embodiments of the present invention.

FIG. 15 is a sectional view of a semiconductor device showing a fifth embodiment according to the present invention. The present embodiment is characterized in that a low-concentration p-type silicon or silicon-germanium layer 19 having, for example, boron as an impurity is provided on the entire surface of the base 7. If the silicon-germanium layer is exposed on the surface during the formation of the emitter as in the first embodiment, there is a concern that the surface shape may deteriorate due to the surface migration of germanium atoms due to the cleaning process before the formation of the emitter. In particular, when the cleaning at a certain high temperature is necessary, or when the germanium composition ratio of the base is increased because a high current gain is required, the above-described deterioration is likely to occur. In such a case, the above-described deformation can be suppressed by inserting a low concentration p-type layer 19 formed so that the surface is covered with silicon atoms. FIG. 16A shows the distribution of the impurity concentration of the transistor intrinsic part in this embodiment, and FIG. 16B shows the distribution of the germanium composition ratio. The impurity concentration of the low concentration p-type layer 19 is preferably controlled in the range of 5 × 10 ¹⁶ cm ⁻³ to 1 × 10 ¹⁸ cm ⁻³ , and the film thickness of the low concentration p-type layer 19 is preferably about 10 nm or less. In this case, even when a forward bias is applied, most of the low-concentration p-type layer 19 can be depleted, and an increase in base width can be minimized. Further, as shown in FIG. 16B, the low-concentration p-type layer 19 has a finite germanium composition ratio, and the composition ratio decreases toward the surface side, at the interface with the low-concentration emitter. It may be adjusted so that it becomes zero.

  By controlling the germanium composition ratio, an internal electric field for accelerating electrons can be applied in the low-concentration p-type layer 19, and an increase in base width due to insertion of the low-concentration p-type layer 19 can be compensated.

  In addition, the insertion of the low-concentration layer 19 serving as a buffer layer against the deformation of the silicon-germanium layer makes it possible to increase the germanium composition ratio of the base layer and the low-concentration collector layer, thereby improving the current gain. I can do it. For this reason, it is possible to achieve a high current gain while maintaining a high cutoff frequency and a low current driving performance. The present embodiment can be applied to all embodiments of the present invention except the tenth embodiment.

  FIG. 17 is a cross-sectional view of the vicinity of the transistor intrinsic portion of the semiconductor device according to the sixth embodiment of the present invention. In this embodiment, the high-concentration n-type emitter 13 made of single-crystal silicon or silicon-germanium formed on the low-concentration emitter 11 is in contact with the insulating film 10 and has an opening surrounded by the insulating film 10. It is formed to fill. Further, a polycrystalline silicon or silicon-germanium layer 14 serving as an emitter electrode is formed on the high-concentration n-type emitter 13 and the insulating film 10. In the present embodiment, the growth pressure and temperature are adjusted, and the growth conditions are optimized so that the high-concentration n-type emitter 13 grows along the side wall of the insulating film 10 while maintaining selectivity with respect to the surface of the insulating film 10. Do.

  The effect of this embodiment is that the emitter resistance can be reduced by filling the opening formed by the insulating film 10 with a single crystal layer having a resistivity lower than that of the polycrystalline layer. The emitter resistance contributes to the above-mentioned time constant τCR, and the cutoff frequency can be further improved by reducing the emitter resistance. This embodiment can be applied to all the embodiments of the present invention except Embodiment 7, Embodiment 9, and Embodiment 10.

  FIG. 18 is a cross-sectional view of the vicinity of the transistor intrinsic portion of the semiconductor device in the seventh embodiment of the present invention. In this embodiment, the emitter-base isolation insulating film has a three-layer structure including the insulating film 9, the insulating film 10, and the insulating film 20, and the insulating film 20 further has a sidewall having an inclination angle. It is characterized by that. FIG. 19 shows a schematic method for manufacturing a semiconductor device in this example. First, the insulating film 9, the insulating film 10, and the insulating film 20 are successively deposited on the base 7, and an opening is formed in the transistor intrinsic part. The film structure of the three-layer insulating film is preferably that the insulating film 9 and the insulating film 20 are silicon oxide films and the insulating film 10 is a silicon nitride film.

  Alternatively, the insulating film 9 and the insulating film 20 can be silicon nitride films, and the insulating film 10 can be a silicon oxide film. Here, for example, when isotropic dry etching is performed and the upper two layers are removed by etching, the structure shown in FIG. 19A is obtained. In FIG. 19A, reference numeral 22 denotes a resist mask used in the lithography process.

  Next, when, for example, isotropic wet etching is performed with the resist mask 22 left, the structure shown in FIG. 19B is obtained. For the wet etching, for example, when the insulating film 9 and the insulating film 20 are silicon oxide films, hydrofluoric acid is used, and when the insulating film 9 and the insulating film 20 are silicon nitride films, for example, about 160 degrees. When phosphoric acid is used, the insulating film 9 and the insulating film 20 can be selectively etched with respect to the insulating film 10.

  In FIG. 19B, as a result of the wet etching, the opening formed by the insulating film 9 and the insulating film 20 has a diameter larger than that of the opening formed by the insulating film 10, and the insulating film 20 has a side wall having an inclination angle, and the diameter of the opening formed by the insulating film 20 increases toward the upper side. When the low-concentration emitter 11 is selectively grown from the state of FIG. 19B and then the high-concentration single crystal emitter 13 and the high-concentration polycrystalline emitter electrode 14 are grown simultaneously, the structure of FIG. 18 is obtained. In the present embodiment, the thickness of the insulating film 10 can be reduced without reducing the distance between the emitter electrode 14 and the base electrode 8, and the emitter opening diameter formed by the insulating film 20 is sufficiently widened in the upper part. Therefore, the emitter resistance can be greatly reduced.

  Further, since the insulating film has a three-layer structure, the distance between the emitter electrode 14 and the base electrode 8 can be increased, and the emitter-base capacitance can be reduced. As a result, the cutoff frequency and the low current drive performance can be further improved. The present embodiment can be applied to all embodiments of the present invention except the sixth embodiment and the tenth embodiment.

  FIG. 20 is a cross-sectional view of the vicinity of the transistor intrinsic portion of the semiconductor device according to the eighth embodiment of the present invention. This embodiment is characterized in that the low-concentration emitter 11 is not in contact with the insulating film 10 and the high-concentration polycrystalline emitter electrode 14 is formed so as to cover all of the top, side and bottom surfaces of the insulating film 10. To do.

  The cavity 12 is formed in a region surrounded by the low-concentration emitter 11, the insulating film 9, and the high-concentration polycrystalline emitter electrode 14. The crystal growth conditions of the high-concentration single crystal emitter 13 and the high-concentration polycrystalline emitter 14 in this embodiment are that the high-concentration emitter and the emitter electrode grow around the low-concentration emitter 11 and the insulating film 10, and are on the insulating film 9. Needs to be adjusted to not grow. For example, in the case of crystal growth using Si2H6 shown in FIG. 10, if silicon is used for the high-concentration emitter, the thickness of the high-concentration emitter should be between about 30 nm and 50 nm in order to obtain the structure of FIG. good.

  When it becomes necessary to increase the film thickness of the high-concentration emitter electrode 14, it is preferable to adjust the appropriate conditions by reducing the growth temperature or increasing the growth pressure. In this embodiment, since it is not necessary to make the thickness of the insulating film 9 thinner than that of the low-concentration emitter 11, it is possible to reduce the emitter-base capacitance by increasing the thickness of the insulating film 9. Further, since it is not necessary to sufficiently lengthen the ridge formed by the insulating film 10, the opening of the insulating film 10 can be widened, and the emitter resistance can be reduced. The present embodiment can be applied to all embodiments of the present invention except for the sixth and seventh embodiments and the tenth embodiment.

  FIG. 21 is a sectional view of a semiconductor device according to the ninth embodiment of the present invention. In this embodiment, the configuration except for the emitter peripheral portion is almost the same as that of the conventional example 1 to the conventional example 3, so that the detailed description is omitted, but the collector 410 and the base 411 are replaced by the collector-base isolation insulating film 405. A self-aligned bipolar transistor is characterized by being selectively grown in the enclosed opening. In this embodiment, the emitter-base isolation insulating film 408 is L-shaped, and an insulating film 409 is formed on the insulating film 408, and the bottom surface of the insulating film 409 is formed on the insulating film 408. A protruding ridge structure is formed. In the opening surrounded by the insulating film 408, a low-concentration emitter 413 made of low-concentration n-type single crystal silicon or silicon-germanium is formed by selective growth. The low-concentration emitter 413 includes the insulating film 408 and the insulating film. A cavity 414 is formed by a region surrounded by 409.

  On the low-concentration emitter 413 and on the insulating film 408 and the insulating film 409, high-concentration emitter 415 made of high-concentration n-type single crystal silicon or silicon-germanium and high-concentration n-type polycrystalline silicon or silicon-germanium, respectively. A high concentration emitter electrode 416 is formed at the same time. The main manufacturing method of the semiconductor device in this embodiment will be described with reference to FIG.

  First, a high-concentration n-type buried layer 402, a low-concentration n-type collector 403, an element isolation insulating film 404, and a collector extraction electrode 418 are formed on a silicon substrate 401, thereby obtaining the structure shown in FIG. Since the formation method so far is published in Patent Document 1 to Patent Document 3, the details are omitted.

  Next, an insulating film 405, a high-concentration base electrode 406 made of high-concentration p-type polycrystalline silicon or silicon-germanium, and an insulating film 407 are sequentially formed on the entire surface, and the periphery of the transistor intrinsic portion shown in FIG. Get the structure. Subsequently, the insulating film 407 and the base electrode 406 are opened by, for example, anisotropic dry etching, and the lowermost insulating film 405 is processed by wet etching to obtain the structure of FIG.

  At this time, for example, the insulating film 407 can be a silicon oxide film, and the insulating film 405 can be a silicon nitride film. In this case, wet etching may be performed using about 160 ° phosphoric acid. In the structure of FIG. 22C, the exposed side wall of the base electrode 406 is oxidized by a thermal oxidation method or the like, and a low concentration n-type collector 410 is selectively grown in the opening. At this time, by selecting an appropriate growth condition as described in the first embodiment, the low-concentration n-type collector 410 has facets and grows without contacting the sidewall insulating film 405. Further, by optimizing the growth conditions, it is possible to suppress the growth of the polycrystalline base electrode 406 exposed at the bottom of the ridge.

  Next, a base layer 411 made of high impurity concentration p-type single crystal silicon / germanium is selectively grown in the opening. At this time, by simultaneously selecting the base layer 411, the growth conditions are selected so that the connecting base electrode 412 made of high-concentration p-type polycrystalline silicon / germanium is deposited on the polycrystalline base electrode 406 exposed at the bottom of the ridge. The base 411 and the base electrode 406 are connected by the high-concentration p-type polycrystalline layer 412 to obtain the structure of FIG. Subsequently, after the sidewall oxide film 421 of the base electrode 406 is removed by wet etching or the like, an insulating film 408 and an insulating film 409 are sequentially deposited, and the insulating film 409 is processed by anisotropic etching such as dry etching, and further insulated. When the film 408 is processed by isotropic etching such as wet etching, the structure shown in FIG. 23B is obtained.

  Here, for example, the insulating film 408 may be a silicon oxide film and the insulating film 409 may be a silicon nitride film. In this case, the insulating film 408 can be etched with hydrofluoric acid. Subsequently, a low-concentration emitter 413 made of low-impurity concentration n-type silicon or silicon-germanium is formed in the opening formed by the insulating films 408 and 409 by selective growth. If the growth conditions at this time are optimized as described in Embodiment 1, the low-concentration n-type emitter 413 has facets and can grow without contacting the sidewall insulating film 408. A high-concentration emitter 415 made of high-concentration n-type single crystal silicon or silicon-germanium and a high-concentration emitter electrode 416 made of high-concentration n-type polycrystalline silicon or silicon-germanium are simultaneously formed on the low-concentration n-type emitter 413. By processing the high-concentration emitter electrode 416, the structure of FIG. 23C is obtained. In this embodiment, since the collector opening is formed in a self-aligned manner with respect to the emitter opening, the collector area can be reduced and the parasitic capacitance of the collector-base junction can be greatly reduced. Similarly to the reduction of the emitter-base junction capacitance, the reduction of the collector-base junction capacitance can greatly improve the low current driving performance. Therefore, in this embodiment, the emitter-base junction capacitance and the collector-base junction capacitance are reduced. By reducing both of these, further improvement in low current drive performance can be expected.

  Note that the insulating film 409 described in this embodiment can be replaced with polycrystalline silicon having an n-type high impurity concentration. In this case, the emitter resistance can be reduced. However, since the selectivity during the growth of the low-concentration emitter is reduced, it is necessary to use it separately from the insulating film depending on the application.

  A tenth embodiment of the present invention will be described with reference to FIG. FIG. 24 is a diagram showing a configuration of a superheterodyne receiver in which the bipolar transistors of Examples 1 to 9 are applied to the transistors of the amplifier circuit. The receiver of this embodiment includes an amplifier circuit with an unnecessary wave suppression function (LNAIR) 501 that amplifies an RF signal Sig-RF input from an RF input terminal, and an output signal from the amplifier circuit 501 as a local oscillator circuit (LOVCO). ) A receiving mixer (MIX) 502 that converts the output signal of 506 into an IF frequency signal, a bandpass filter (IFBPF) 503 for removing unnecessary waves from the output signal of the receiving mixer 502, and an IF frequency band An IF amplification circuit (IFAMP) 504 that performs amplification and a demodulation circuit (DEMOD) 505 that demodulates a baseband signal component from the IF signal are included. The receiver according to this embodiment includes a bipolar transistor that can operate at high speed and can perform signal amplification with low power, so that the power of the entire receiver can be reduced.

  An eleventh embodiment of the present invention will be described with reference to FIG. FIG. 25 is a diagram showing a configuration of a superheterodyne transmitter in which the bipolar transistors of Examples 1 to 9 are applied to the transistors of the amplifier circuit. The transmitter of this embodiment includes a modulation circuit (MOD) 601 that digitally modulates a baseband signal Sig-BB input from a Sig-BB signal input terminal, and an output signal from the modulation circuit 601 as a local oscillation circuit (LOVCO). ) A transmission mixer (MIX) 602 that converts the output signal of 605 into an IF frequency signal, an amplifier circuit with an unnecessary wave suppression function (AMPIR) 603 that amplifies the output signal of the transmission mixer 602 and suppresses unnecessary waves; A power amplifying circuit (PA) 604 for further amplifying the output signal of the amplifying circuit 603 is further included. The transmitter according to the present embodiment includes a bipolar transistor that can operate at high speed and can amplify a signal with low power, so that the power of the entire transmitter can be reduced.

1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. It is sectional drawing which shows the bipolar transistor of the prior art example 1. It is sectional drawing which shows the bipolar transistor of the prior art example 2. It is sectional drawing which shows the bipolar transistor of the prior art example 3. It is the figure which showed distribution of the impurity concentration (a) and germanium composition ratio (b) of the transistor main part in 1st Example of the semiconductor device which concerns on this invention. It is the figure which compared the reciprocal number of the cutoff frequency in the constant collector current density in the 1st Example of the semiconductor device concerning the present invention with the conventional example, and (a) is a case where collector current density is ² mA / micrometer ² (B) is a figure which shows the case where a collector current density is 0.3 mA / micrometer < ² >. It is the figure which showed the relationship between the cutoff frequency and collector current density in the 1st Example of the semiconductor device which concerns on this invention in the form compared with this invention A and the prior art example B. It is sectional drawing which showed the manufacturing method of the 1st Example of the semiconductor device which concerns on this invention as (a) (b) (c) in order of the process. It is sectional drawing which showed the process following the process of the manufacturing method shown in FIG. 8 as (a) (b) (c) in the order of the process. Critical film pressure for selective growth when disilane (Si2H6) is used as a silicon source gas in silicon crystal growth using chemical vapor deposition in the manufacturing method of the first embodiment of the semiconductor device according to the present invention. It is a figure which shows the relationship between thickness and a germanium composition ratio. Selectivity for an insulating film when monosilane (SiH4) is used as a silicon source gas in silicon crystal growth using chemical vapor deposition in the manufacturing method of the first embodiment of the semiconductor device according to the present invention. It is the figure which showed the relationship between the maximum film thickness which can be maintained, and a germanium composition ratio. It is a figure which shows distribution of the impurity concentration (a) and germanium composition ratio (b) of the transistor main part in the 2nd Example of the semiconductor device based on this invention. It is a figure which shows distribution of the impurity concentration (a) and germanium composition ratio (b) of the transistor main part in the 3rd Example of the semiconductor device which concerns on this invention. It is sectional drawing which shows the 4th Example of the semiconductor device based on this invention. It is sectional drawing which shows the 5th Example of the semiconductor device based on this invention. It is a figure which shows distribution of the impurity concentration (a) and germanium composition ratio (b) of the transistor main part in the 5th Example of the semiconductor device based on this invention. It is sectional drawing of the transistor main part which shows the 6th Example of the semiconductor device based on this invention. It is sectional drawing of the transistor main part which shows the 7th Example of the semiconductor device based on this invention. It is sectional drawing which showed the manufacturing method of the 7th Example of the semiconductor device based on this invention as (a) (b) in order of the process. It is sectional drawing of the transistor main part which shows the 8th Example of the semiconductor device which concerns on this invention. It is sectional drawing which shows the 9th Example of the semiconductor device based on this invention. It is sectional drawing which showed the manufacturing method of the 9th Example of the semiconductor device based on this invention as (a) (b) (c) in order of the process. It is sectional drawing which showed the process following the process of the manufacturing method shown in FIG. 22 as (a) (b) (c) in the order of the process. It is a figure which shows one Example of the communication apparatus of the superheterodyne system of this invention, Comprising: It is a figure which shows the structural example of the receiver of the superheterodyne system which applied the semiconductor device of this invention to the transistor of the amplifier circuit. It is a figure which shows one Example of the communication apparatus of the superheterodyne system of this invention, Comprising: It is a figure which shows the structural example of the transmitter of the superheterodyne system which applied the semiconductor device of this invention to the transistor of the amplifier circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1, 101, 201, 301, 401 ... Silicon substrate, 2, 102, 202, 302, 402 ... High concentration n type buried collector layer, 103, 203, 303, 403 ... Low concentration n type collector layer (single crystal silicon Or single crystal silicon / germanium layer), 3, 104, 204, 304, 404... Element isolation insulating film, 4, 105, 205, 305, 405... Collector-base isolation insulating film, 5. Single crystal silicon or single crystal silicon / germanium layer), 6, 109, 209, 309, 410 ... Low concentration n-type collector layer (single crystal silicon / germanium layer), 106, 206, 306, 406 ... Base extraction electrode (high P-type polycrystalline silicon or high-concentration p-type polycrystalline silicon / germanium), 7, 1 0, 210, 310, 411 ... high-concentration p-type base layer (single crystal silicon / germanium layer), 8 ... p-type impurity ion implantation region, 9, 10, 20, 107, 108, 207, 208, 307, 308, 407, 408, 409 ... Emitter-base isolation insulating film, 111, 211, 311, 412 ... Base connecting electrode (high-concentration p-type polycrystalline silicon or high-concentration p-type polycrystalline silicon / germanium), 11, 312, 413 ... Low-concentration n-type emitter layer (low-concentration n-type single crystal silicon or low-concentration n-type single crystal silicon / germanium), 12, 414... Low-concentration n-type emitter layer-insulating film cavity, 13, 112, 212, 313, 415... High concentration n-type emitter layer (high concentration n-type single crystal silicon or high concentration n-type single crystal silicon / germanium) 14, 113, 213, 314, 416 ... Emitter electrode (high-concentration n-type polycrystalline silicon), 15 ... Side wall insulating film, 16, 114, 214, 315, 417 ... Interlayer insulating film, 115, 215, 316, 418 ... High-concentration n-type collector lead electrode, 17, 116, 216, 317, 419 ... Metal electrode, 22 ... Resist, 420 ... Low-concentration n-type collector layer-insulating film cavity, 421 ... Side wall insulating film, 501 ... Unwanted wave suppression Function amplifying circuit, 502 ... reception mixer, 503 ... band pass filter, 504 ... IF amplification circuit, 505 ... demodulation circuit, 506 ... local oscillation circuit, 601 ... digital modulation circuit, 602 ... transmission mixer, 603 ... unnecessary wave suppression Function amplifying circuit, 604... Power amplifying circuit, 605.

Claims (14)

A first semiconductor layer of a first conductivity type provided on a semiconductor substrate;
A second semiconductor layer of a first conductivity type provided on the first semiconductor layer;
A third semiconductor layer of a second conductivity type provided on the second semiconductor layer;
A first insulating film provided on the third semiconductor layer and having an opening;
A fourth semiconductor layer of a first conductivity type provided in the opening;
A fifth semiconductor layer of a first conductivity type provided on the fourth semiconductor layer,
The impurity concentration of the fourth semiconductor layer is smaller than that of the fifth semiconductor layer,
The fourth semiconductor layer is formed so as not to contact a sidewall of the first insulating film;
A semiconductor device having a cavity surrounded by at least the fourth semiconductor layer and the first insulating film. In claim 1,
Provided on the first insulating film;
Comprising a second insulating film having an opening narrower than the first insulating film;
A semiconductor device having a cavity surrounded by at least the fourth semiconductor layer, the first insulating film, and the second insulating film. In claim 2,
The fourth semiconductor layer has a facet surface starting from an edge of the lower surface of the first insulating film, and the facet surface is (111) or (311). In claim 3,
Forming a bipolar transistor having the first semiconductor layer and the second semiconductor layer as a collector, the third semiconductor layer as a base, and the fourth semiconductor layer and the fifth semiconductor layer as an emitter; A semiconductor device characterized by the above. In claim 4,
The first semiconductor layer includes one of single crystal silicon, single crystal silicon / germanium, and single crystal silicon / germanium / carbon,
The second semiconductor layer and the base are configured to include any one of single crystal silicon / germanium and single crystal silicon / germanium / carbon,
2. The semiconductor device according to claim 1, wherein the emitter includes any one of single crystal silicon, single crystal silicon / germanium, and single crystal silicon / germanium / carbon. In claim 5,
The semiconductor device according to claim 1, wherein the first insulating film is a silicon oxide film. In claim 6,
The semiconductor device, wherein the second insulating film is a silicon nitride film. In claim 7,
The forbidden band width in the third semiconductor layer decreases stepwise or continuously as it goes from the fourth semiconductor layer toward the second semiconductor layer. Forming a first semiconductor layer of a first conductivity type on a semiconductor substrate;
Forming a second semiconductor layer of a first conductivity type on the first semiconductor layer;
Forming a second conductivity type third semiconductor layer on the second semiconductor layer;
Forming a first insulating film on the third semiconductor layer;
Forming an opening in the first insulating film;
Forming a fourth semiconductor layer of a first conductivity type in the opening;
Forming a fifth semiconductor layer of the first conductivity type on the fourth semiconductor layer,
The impurity concentration of the fourth semiconductor layer is lower than that of the fifth semiconductor layer, and a cavity surrounded by at least the fourth semiconductor layer and the first insulating film is formed. A method for manufacturing a semiconductor device. In claim 9,
Further comprising the steps of forming the second insulating film on the first insulating film, and forming an opening in the second insulating film;
The method for manufacturing a semiconductor device, wherein the opening surrounded by the second insulating film has a smaller diameter than the opening surrounded by the first insulating film. In claim 10,
Forming the fourth semiconductor layer with facets starting from the edge of the lower surface of the opening surrounded by the first insulating film;
The method of manufacturing a semiconductor device, wherein the facet is (111) or (311). A superheterodyne communication device comprising a semiconductor device in which an amplifier circuit is formed,
The semiconductor device includes:
A first semiconductor layer of a first conductivity type provided on a semiconductor substrate;
A second semiconductor layer of a first conductivity type provided on the first semiconductor layer;
A third semiconductor layer of a second conductivity type provided on the second semiconductor layer;
A first insulating film provided on the third semiconductor layer and having an opening;
A fourth semiconductor layer of a first conductivity type provided in the opening;
A fifth semiconductor layer of a first conductivity type provided on the fourth semiconductor layer,
The impurity concentration of the fourth semiconductor layer is smaller than that of the fifth semiconductor layer,
The fourth semiconductor layer is formed so as not to contact a sidewall of the first insulating film;
A superheterodyne communication device characterized by having a cavity surrounded by at least the fourth semiconductor layer and the first insulating film. In claim 12,
The superheterodyne communication device is
A first amplifier circuit for amplifying an RF signal input from an RF input terminal;
A receiving mixer that converts the output signal of the first amplifier circuit into an IF frequency signal using the output signal of the local oscillation circuit;
A bandpass filter for reducing unnecessary waves of the output signal of the reception mixer;
A second amplifier circuit for amplifying the IF frequency band;
A superheterodyne receiver comprising a demodulation circuit for demodulating a baseband signal component from an IF signal,
A superheterodyne communication apparatus, wherein at least one of the first and second amplifier circuits is formed in the semiconductor device as the amplifier circuit. In claim 12,
The superheterodyne communication device is
A modulation circuit that digitally modulates the baseband signal Sig-BB input from the baseband signal input terminal;
A transmission mixer that converts the output signal of the modulation circuit into an IF frequency signal using the output signal of the local oscillation circuit;
A third amplifier circuit for amplifying the output signal of the transmission mixer and suppressing unwanted waves;
A superheterodyne transmitter comprising a fourth amplifier circuit for further power amplification of the output signal of the third amplifier circuit;
A superheterodyne communication apparatus, wherein at least one of the third and fourth amplifier circuits is formed in the semiconductor device as the amplifier circuit.

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