JP2008027964A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which has high performance enough to exhibit together the performance of each element with different uses that is mounted to a semiconductor device such as BiCMOS, etc. <P>SOLUTION: High-concentration phosphor ions are implanted into the formation area A of a high-speed HBT on a p-type Si substrate 1, and a silicon oxide film 3 is formed on the Si substrate 1. After an n-type Si layer is epitaxially grown, the silicon oxide film 3 is first evaporated in the formation area A of the high-speed HBT and it is removed therefrom, and then the n-type Si layer is grown. Therefore, the n-type Si layer that is thinner than a lateral pnp, a pn junction varactor, a high breakdown voltage HBT transistor or the like can be obtained, and the performance of each element with different uses can be together established. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device on which various elements such as bipolar transistors, MOS transistors, and varactors are mounted.

  Conventionally, heterojunction bipolar transistors (hereinafter referred to as HBTs) have superior high-speed operability and high current drive capability compared to Si homojunction bipolar transistors, so mobile communications that require high-speed and high-integration, etc. It is used as a communication device. In particular, by incorporating a heterojunction structure such as Si / SiGe or Si / SiGeC in a bipolar transistor, an HBT is realized even with a cutoff frequency exceeding 100 GHz.

  In recent years, HBTs excellent in high-speed performance are integrated with CMOS, lateral PNP transistors, PN junction varactor elements, and the like, and are used for communication devices and the like. As a conventional example of BiCMOS in which a high-speed HBT and a high breakdown voltage HBT are mixedly mounted on the same substrate, a semiconductor device disclosed in Patent Document 1 is known.

In this conventional example, since a concave depression is formed on the surface of the collector layer of the high-speed HBT, the collector layer immediately below the SiGe base layer of the high-speed HBT is relatively thin, and the SiGe. The collector layer directly below the base layer can be made relatively thick, and the optimum CE breakdown voltage can be achieved for each, thus realizing a high-performance semiconductor device that achieves both high breakdown voltage characteristics and high-speed characteristics. Is done.
JP 2002-208641 A (FIG. 1)

  In the structure of the above-described conventional example, in order to further reduce the collector layer of the high-speed HBT, the concave depression must be formed deeply as the performance of the HBT increases. However, if the concave depression is deepened, the surface step of the collector layer increases, and the crystallinity and film composition of the SiGe • base layer formed across the step deteriorates. Further, it is difficult to finely process the emitter electrode formed on the recess.

  Therefore, in view of the above problems, an object of the present invention is to provide a method for manufacturing a high-performance semiconductor device capable of achieving both the performance of each element having a different application mounted on a semiconductor device such as BiCMOS.

  In order to achieve the above object, the present invention is characterized in that an epitaxial layer is formed after a silicon oxide film is formed on the surface of a high concentration buried layer such as a high-speed HBT.

  In other words, the semiconductor device manufacturing method of the first invention is a method of manufacturing a semiconductor device in which elements having different uses, each having a single crystal silicon layer, are formed in a first region and a second region of a silicon substrate. Then, a silicon oxide film is formed on the surfaces of the first region and the second region, and the silicon oxide film formed on the surface of the second region is removed, so that the silicon oxide film is formed only on the surface of the first region. After the film is formed, a silicon layer is epitaxially grown on the silicon substrate.

  Specifically, after implanting phosphorus (P) ions into a desired element region on a P-type silicon (Si) substrate, for example, a high-speed HBT, a PN junction varactor, a lateral PNP transistor, or a high-voltage HBT formation region, In this configuration, a silicon oxide film is formed only on the surface of the high-concentration buried layer in the high-speed HBT formation region, and then a low-concentration N-type Si layer is formed on the Si substrate.

The N-type Si layer is epitaxially grown by supplying a silicon-based gas such as silane to a semiconductor substrate heated in a vacuum vessel. Here, the silicon oxide film is a very stable substance. However, when Si and SiO ₂ constituting the semiconductor substrate react with each other at the semiconductor substrate-oxide film interface to generate SiO, the volatility of SiO is high. A paper by Hirayama et al. Is that it is effective to cause SiO _{2 to} be lost and to supply a gas containing Si such as silane to accelerate the removal of the oxide film to cause the formation reaction of SiO on the oxide film surface ( 1987, Applied Physics Letters, No. 51, p. 2213).

  Therefore, when a semiconductor substrate on which a silicon oxide film is formed only on the surface of the high-concentration buried layer in the high-speed HBT formation region is heated in a vacuum vessel and a silicon-based gas such as silane is supplied, in the high-speed HBT formation region, A removal reaction of the silicon oxide film occurs, and then epitaxial growth proceeds. On the other hand, in other formation regions such as a PN junction varactor, a lateral PNP transistor, or a high breakdown voltage HBT, epitaxial growth proceeds from the beginning. For this reason, since the film thickness of the low-concentration N-type Si layer is reduced in the high-speed HBT formation region, the high-frequency characteristics of the high-speed HBT are not degraded without degrading the performance of the PN junction varactor, lateral PNP transistor, or high-voltage HBT Can be improved. In addition, since the recess of the epitaxial layer is not deeply formed, the crystallinity and film composition of the SiGe base layer are not deteriorated.

  A method for manufacturing a semiconductor device according to a second invention is a method for manufacturing a semiconductor device in which elements having different uses, each having a single crystal silicon layer, are formed in a first region and a second region of a silicon substrate, A first silicon oxide film is formed on the surface of the first region, a second silicon oxide film having a thickness smaller than that of the first silicon oxide film is formed on the surface of the second region, and then formed on the silicon substrate. The silicon layer is epitaxially grown.

  Specifically, after implanting phosphorus (P) ions into a desired element region on a P-type silicon (Si) substrate, for example, a high-speed HBT, a PN junction varactor, a lateral PNP transistor, or a high-voltage HBT formation region, A silicon oxide film is formed on the surface of the high concentration buried layer in the formation region of the high-speed HBT. In this case, the silicon oxide film is formed thicker than the other formation regions on the surface of the high concentration buried layer in the high-speed HBT formation region, and then the low concentration N-type Si layer is formed on the Si substrate.

  When a semiconductor substrate is heated in a vacuum vessel and a silicon-based gas such as silane is supplied, the removal reaction of the silicon oxide film first occurs and then the epitaxial growth proceeds. However, the silicon oxide is oxidized only on the surface of the high concentration buried layer in the high-speed HBT formation region. Since the film is formed thick, it takes time to remove the oxide film as compared with other elements such as a PN junction varactor, a lateral PNP transistor, or a high breakdown voltage HBT. Since the film thickness of the low-concentration N-type Si layer is small, the high-frequency characteristics of the high-speed HBT can be improved without degrading the performance of the PN junction varactor, lateral PNP transistor, or high-voltage HBT. Further, since the entire surface is covered with the silicon oxide film, the cleanliness of the interface between the epitaxial layer and the substrate can be increased.

  According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method according to the second aspect of the present invention, in which the first silicon oxide film is removed after the second silicon oxide film is removed when the silicon layer is epitaxially grown. The silicon layer having the first impurity concentration is epitaxially grown in the second region until the first silicon oxide film is removed, until the first region and the second region are removed. A silicon layer having a high second impurity concentration different from the first impurity concentration is epitaxially grown.

  Specifically, after implanting phosphorus (P) ions into a desired element region on a P-type silicon (Si) substrate, for example, a high-speed HBT, a PN junction varactor, a lateral PNP transistor, or a high-voltage HBT formation region, A silicon oxide film is formed on the surface of the high concentration buried layer in the formation region of the high-speed HBT. At this time, after the silicon oxide film is formed thicker than the other formation regions on the surface of the high-concentration buried layer in the high-speed HBT formation region, an N-type Si layer having a first impurity concentration is formed on the Si substrate. After the thick silicon oxide film on the surface of the high-concentration buried layer in the high-speed HBT formation region is removed, an N-type Si layer having a second impurity concentration is epitaxially grown on the entire surface of the Si substrate.

  When a semiconductor substrate is heated in a vacuum vessel and a silicon-based gas such as silane is supplied, the removal reaction of the silicon oxide film first occurs and then the epitaxial growth proceeds. However, the silicon oxide is oxidized only on the surface of the high concentration buried layer in the high-speed HBT formation region. Since the film is formed thick, it takes time to remove the oxide film as compared with other elements such as a PN junction varactor, a lateral PNP transistor, or a high breakdown voltage HBT, and the epitaxial growth is delayed. Then, the N-type Si layer having the second impurity concentration is epitaxially grown at the stage where the silicon oxide film in the formation region of the high-speed HBT is also removed. Thereby, the impurity concentration of the N-type Si layer of the PN junction varactor, the lateral PNP transistor, or the high breakdown voltage HBT and the high speed HBT can be changed, so that the former high breakdown voltage characteristic and the latter high frequency characteristic can be further improved. it can.

  A method for manufacturing a semiconductor device according to a fourth aspect of the present invention is the method for manufacturing a semiconductor device according to the first, second or third aspect, wherein silane or disilane is used as a silicon source gas when the silicon layer is epitaxially grown.

According to this configuration, Si contained in silane and disilane reacts with SiO ₂ to improve the generation efficiency of SiO, so that the removal of the silicon oxide film is accelerated.

  According to the method for manufacturing a semiconductor device of the present invention, after the silicon oxide film is formed only on the surface of the first region or on the surface of the second region, the second silicon oxide thinner than the first silicon oxide film is formed. Since the silicon layer is epitaxially grown on the silicon substrate after the film is formed, it takes longer to remove the silicon oxide film than the second region in the first region where the high-speed HBT or the like is formed, and the epitaxial growth is delayed. Thus, the epitaxial layer can be thinly formed. For this reason, unlike the prior art, it is not necessary to form a concave depression on the surface of the epitaxial layer in the high-speed HBT formation region, so that the crystallinity and film composition of the SiGe base layer of the high-speed HBT are deteriorated. In addition, fine processing of the emitter electrode is facilitated. As described above, since Si epitaxial layers having different film thicknesses can be formed depending on desired elements, it is possible to simultaneously improve the characteristics of each element having different applications mounted on a semiconductor device such as BiCMOS. A high-performance semiconductor device capable of improving the performance of the element can be realized.

(First embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. FIG. 1A to FIG. 2B are cross-sectional views showing a manufacturing process of a bipolar transistor according to the first embodiment of the present invention. Note that a description of the resist film removal step is omitted.

  In the manufacturing method of the present embodiment, when forming different elements having the single crystal silicon layer 4 in the first region A and the second region B of the silicon substrate 1, respectively, After forming a silicon oxide film only on the surface of the first region A by forming a silicon oxide film on the surface of the second region B and removing the silicon oxide film formed on the surface of the second region B A silicon layer 4 is epitaxially grown on the silicon substrate 1.

In this case, first, as shown in FIG. 1A, an N-type buried impurity layer 2 is formed on the upper surface of the P-type Si substrate 1 having the (001) plane as a main surface by using photolithography. A resist film (not shown) having openings in the regions to be intended (the high-speed HBT formation region A and the lateral PNP transistor formation region B) is formed. Next, phosphorus ions are implanted into the Si substrate 1 under conditions of an acceleration energy of about 30 keV and a dose of about 1 × 10 ¹⁵ cm ⁻² using the resist film as an implantation mask. Next, heat treatment is performed at a temperature of about 1000 ° C. for about 30 minutes.

  Subsequently, a silicon oxide film having a thickness of about 3 to 5 nm is formed on the surface of the Si substrate 1 (not shown). After opening other than the high-speed HBT formation region A by lithography, the silicon oxide film is etched to form a Si oxide film 3 on the surface of the high-speed HBT formation region A as shown in FIG. Form.

Next, the Si single crystal layer 4 is epitaxially grown on the P-type Si substrate 1 while in-situ doping with N-type impurities. At this time, for example, assuming that the growth temperature is 800 ° C. and the flow rate of the source gas Si ₂ H ₆ is 1 SCCM, the silicon oxide film 3 of about 3 to 5 nm formed in the high-speed HBT formation region A as shown in FIG. Is removed in about 12 to 20 minutes, and in the other region B, the Si single crystal layer 4 is formed to about 200 to 300 nm. As shown in FIG. 2B, in the high-speed HBT formation region A, the growth of the Si single crystal layer starts after the removal of the silicon oxide film, so that the lateral PNP transistor formation region B is higher in the high-speed HBT formation region A. Thus, the Si single crystal layer 4 can be formed to be about 200 to 300 nm thicker.

  Further, since the concave layer is not deeply formed on the surface of the epitaxial layer in the high-speed HBT formation region A, the crystallinity and film composition of the SiGe base layer are not deteriorated.

In this embodiment, the growth condition of the Si single crystal layer 4 is set to a temperature of 800 ° C., but about 700 to 1000 ° C., and the source gas is Si ₂ H ₆ , but SiH ₄ or the like may be used. Further, the case where the high-speed HBT and the lateral PNP transistor are integrated is shown, but it is also effective when the high-voltage HBT, the PN junction varactor and the like are integrated with the high-speed HBT.
(Second Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 3A to FIG. 4B are cross-sectional views showing a manufacturing process of the bipolar transistor according to the second embodiment of the present invention. Note that a description of the resist film removal step is omitted.

  In the manufacturing method of the present embodiment, the surface of the first region A is formed when elements having different uses having the single crystal silicon layer 4 are formed in the first region A and the second region B of the silicon substrate 1, respectively. After forming a first silicon oxide film on the surface of the second region B and forming a second silicon oxide film having a thickness smaller than that of the first silicon oxide film, a silicon layer 4 is formed on the silicon substrate 1. Epitaxial growth.

In this case, first, as shown in FIG. 3A, an N-type buried impurity layer 2 is formed on the upper surface of the P-type Si substrate 1 having the (001) plane as a main surface by photolithography. A resist film (not shown) having openings in the regions to be formed (the high-speed HBT formation region A and the lateral PNP transistor formation region B) is formed. Next, phosphorus ions are implanted into the Si substrate 1 under conditions of an acceleration energy of about 30 keV and a dose of about 1 × 10 ¹⁵ cm ⁻² using the resist film as an implantation mask. Next, heat treatment is performed at a temperature of about 1000 ° C. for about 30 minutes.

  Subsequently, a silicon oxide film of about 10 nm is formed on the surface of the Si substrate 1 (not shown). After opening other than the high-speed HBT formation region A using lithography, the silicon oxide film is etched by about 5 nm, so that the surface portion of the high-speed HBT formation region A is about 10 nm as shown in FIG. In the other region B, an Si oxide film 3 of about 5 nm is formed.

Next, the Si single crystal layer 4 is epitaxially grown on the P-type Si substrate 1 while in-situ doping with N-type impurities. At this time, for example, if the growth temperature is 800 ° C. and the flow rate of the source gas Si ₂ H ₆ is 1 SCCM, the silicon oxide film of about 5 nm formed outside the high-speed HBT formation region A is removed in about 20 minutes (not shown). Then, after about 40 minutes, as shown in FIG. 4A, the silicon oxide film 3 in the high-speed HBT formation region A is also removed, and in the other region B, the Si single crystal layer 4 is formed in about 200 to 300 nm. ing. In the high-speed HBT formation region A, as shown in FIG. 4B, after the silicon oxide film is removed, the growth of the Si single crystal layer starts, so that the lateral PNP transistor formation region B is approximately less than the HBT formation region. The Si single crystal layer 4 can be formed with a thickness of 200 to 300 nm.

  Further, since the entire surface is covered with the silicon oxide film 3, the cleanliness of the interface between the epitaxial layer and the substrate can be increased.

In this embodiment, the growth condition of the Si single crystal layer 4 is set to a temperature of 800 ° C., but about 700 to 1000 ° C., and the source gas is Si ₂ H ₆ , but SiH ₄ or the like may be used. Further, the case where the high-speed HBT and the lateral PNP transistor are integrated is shown, but it is also effective when the high-voltage HBT, the PN junction varactor and the like are integrated with the high-speed HBT.
(Third embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. 3 to 10 are cross-sectional views showing the manufacturing steps of the bipolar transistor according to the third embodiment of the present invention. Note that a description of the resist film removal step is omitted.

  In the manufacturing method of the present embodiment, when the silicon layer is epitaxially grown in the second embodiment, after the second silicon oxide film is removed and until the first silicon oxide film is removed, After the silicon layer 4a having the first impurity concentration is epitaxially grown in the second region B and the first silicon oxide film is removed, the first impurity concentration is added to the first region A and the second region B. A silicon layer 4b having a higher second impurity concentration is epitaxially grown.

In this case, first, as shown in FIG. 5A, an N-type buried impurity layer 2 is formed on the upper surface of the P-type Si substrate 1 having the (001) plane as a main surface by using photolithography. A resist film (not shown) having openings in the regions to be formed (the high-speed HBT formation region A and the lateral PNP transistor formation region B) is formed. Next, phosphorus ions are implanted into the Si substrate 1 under conditions of an acceleration energy of about 30 keV and a dose of about 1 × 10 ¹⁵ cm ⁻² using the resist film as an implantation mask. Next, heat treatment is performed at a temperature of about 1000 ° C. for about 30 minutes.

  Subsequently, a silicon oxide film of about 10 nm is formed on the surface of the Si substrate 1 (not shown). After opening other than the high-speed HBT formation region A using lithography, the silicon oxide film is etched by about 5 nm, so that the surface portion of the high-speed HBT formation region A is about 10 nm as shown in FIG. In the other region B, an Si oxide film 3 of about 5 nm is formed.

Next, an Si single crystal layer is epitaxially grown on the P-type Si substrate 1 while in-situ doping with N-type impurities. At this time, for example, if the growth temperature is 800 ° C. and the flow rate of the source gas Si ₂ H ₆ is 1 SCCM, the silicon oxide film of about 5 nm formed outside the high-speed HBT formation region A is removed in about 20 minutes and about 40 minutes. Thereafter, as shown in FIG. 6A, the silicon oxide film 3 in the high-speed HBT formation region A is removed, and in the other region B, the Si single crystal layer 4a having the first impurity concentration is formed to be about 200 to 300 nm. Has been. Thereafter, the Si single crystal layer 4b having the second impurity concentration is grown by changing the concentration of the N-type impurity. In the high-speed HBT formation region A, as shown in FIG. 6B, after the silicon oxide film is removed, the growth of the Si single crystal layer starts. Therefore, in the lateral PNP transistor formation region B, the first about 200 to 300 nm is formed. The Si single crystal layer 4a having the second impurity concentration and the Si single crystal layer 4b having the second impurity concentration can be formed only in the region where the high-speed HBT is formed.

  Next, in the step shown in FIG. 7, a shallow trench 5 in which a silicon oxide film is embedded and a deep trench 6 including an undoped polysilicon film 7 and a silicon oxide film 8 surrounding the undoped polysilicon film 7 are formed as isolation layers. . The depths of the trenches 5 and 6 are about 0.3 μm and about 3 μm, respectively.

Next, as shown in FIG. 8, a resist film (not shown) having an N ⁺ -type collector lead layer 9 is formed, and using the resist film as an implantation mask, the acceleration energy is about 60 keV and the dose amount is 3 × 10. After selectively implanting phosphorus (P) ions into the Si single crystal layer 3 under the condition of ¹⁵ cm ⁻² , the resist film is removed using oxygen plasma ashing. Subsequently, a heat treatment is performed at a temperature of about 850 ° C. for about 30 minutes. Further, arsenic is implanted under the conditions of an acceleration energy of about 50 keV and a dose amount of 3 × 10 ¹⁵ cm ⁻² , and the N ⁺ -type collector extraction layer 9 Form.

  Next, as shown in FIG. 9, after forming a silicon oxide film of about 5 nm and a polysilicon film 10 of about 250 nm on the substrate, etching is performed using a resist film (not shown) having an opening other than the base region as a mask. A base region is formed.

  Next, as shown in FIG. 10, a silicon oxide film having a thickness of about 110 nm is deposited on the substrate by a low pressure CVD method, and a resist film (not shown) having openings in the emitter 12 and collector 13 portions of the lateral transistor is formed. Etching is performed as a mask to form sidewalls 11. Thereafter, As is implanted to remove the resist. Further, boron implantation is performed using a resist film (not shown) having an opening in the extraction electrode portion 14 at the base of the lateral transistor as a mask.

  Next, as shown in FIG. 11, a silicon oxide film 15 having a thickness of about 50 nm is deposited on the substrate by a low pressure CVD method. Subsequently, a polycrystal having a thickness of about 100 nm is formed on the silicon oxide film 15 by a low pressure CVD method. A silicon film 16 is deposited.

  Next, as shown in FIG. 12, a resist film (not shown) having an opening in the high-speed HBT formation region A is formed by photolithography, and the polysilicon film is etched by using the resist film as an etching mask. 16 is patterned to open a region for forming the external base layer. Next, the resist film is removed using oxygen plasma ashing, and subsequently, the silicon oxide film 15 exposed in the opening of the polysilicon film 16 is removed with hydrofluoric acid, and phosphorus is implanted into the Si single crystal layer. The surface of 4 is exposed.

  Next, as shown in FIG. 13, after a Si buffer layer having a thickness of about 70 nm is grown on the substrate by UHV-CVD, an SiGeC film and a Si film are sequentially epitaxially grown. At this time, an Si / SiGeC layer 17a having a thickness of about 100 nm made of a SiGeC film having a thickness of about 70 nm and a Si film having a thickness of about 30 nm is grown on the Si single crystal layer 4, and the shallow trench 5 (silicon On the oxide film) and the polysilicon film 16, a polycrystal having a thickness of about 80 nm comprising a polycrystal Si having a thickness of about 30 nm, a polycrystal SiGeC film having a thickness of 35 nm, and a polycrystal Si film having a thickness of about 15 nm. The Si / SiGeC layer 17b is grown. Further, boron (B) is introduced into the SiGeC film by in-situ doping, and the SiGeC film is P-type.

Next, as shown in FIG. 14, by a low pressure CVD method, a silicon oxide film 18 having a thickness of about 30 nm and a polycrystal containing phosphorus having a thickness of about 50 nm and a concentration of about 3 × 10 ¹⁵ cm ⁻³ are formed on the substrate. A silicon film 19 is continuously deposited. Thereafter, using photolithography, a resist film (not shown) having an emitter formation region opened is formed, and using the resist film as an etching mask, the polysilicon film 19 is patterned by dry etching to form an emitter opening. 20 is formed. Thereafter, the silicon oxide film 18 in the emitter opening 20 is removed by wet etching.

Next, as shown in FIG. 15, N-type impurities (phosphorus) having a film thickness of about 400 nm and a concentration of about 1 to 5 × 10 ²⁰ cm ⁻³ are formed on the substrate by low pressure CVD with in-situ doping. Deposit N ⁺ type polysilicon. Subsequently, a resist film covering the emitter electrode portion is formed on the N ⁺ type polysilicon film 21 by photolithography. Then, using the resist film as an etching mask, the polysilicon film is patterned by anisotropic etching to form the emitter electrode 21. Subsequently, using the resist film and the emitter electrode 21 as an etching mask, a portion of the silicon oxide film 18 not covered with the emitter electrode 21 is removed by wet etching.

Next, in order to reduce the resistance of the external base, the acceleration energy is about 5 keV from the direction substantially perpendicular to the substrate surface (the direction having only an inclination not to cause channeling) to the Si / SiGeC layers 17a and 17b. Additional boron is implanted under the condition of a dose of 2 × 10 ¹⁵ cm ⁻² .

  Next, as shown in FIG. 16, the resist film used for patterning the emitter electrode 21 is removed by oxygen plasma ashing. Thereafter, a resist film is formed by photolithography to cover the emitter electrode 21 and the polycrystalline Si / SiGeC layer 17b, the region serving as the external base layer, and using the resist film as an etching mask, the polycrystalline Si / SiGeC layer A portion of 17b located outside the outer base layer is removed.

Next, as shown in FIG. 17, after a silicon oxide film having a thickness of about 30 to 100 nm is deposited on the substrate by low pressure CVD, the temperature is about 900 ° C. and the time is about 10 to 15 seconds. The emitter layer 22 is formed by diffusing phosphorus from the emitter electrode 21 into the Si film in the Si / SiGeC layer 17a. Subsequently, after depositing a silicon oxide film on the substrate, the silicon oxide film is anisotropically etched to form sidewalls 23 on the side surfaces of the emitter electrode 21. At this time, the silicon layer is exposed on the upper surface of the emitter electrode 21 of the HBT, the upper surface of the Si / SiGeC layer 17b, and the upper surface of the N ⁺ -type collector extraction layer 9.

Next, as shown in FIG. 18, after a Co film is formed on the substrate by sputtering, the Co and Si are reacted by heating to react with the upper part of the emitter electrode 21 of the HBT and the upper part of the Si / SiGeC layer 17a. A Co silicide layer is formed on the N ⁺ -type collector lead layer 9. Thereafter, the unreacted layer of Co and Si is removed, and then the Co silicide layer is annealed to reduce the resistance of the Co silicide layer. Thus, a part of the Si / SiGeC layer 17a, an external base layer constituted by the Si / SiGeC layer 17b and the Co silicide layer is formed.

In the subsequent steps, a well-known multilayer wiring process is used. That is, after depositing an interlayer insulating film 24 made of a silicon oxide film on the substrate, it penetrates through the interlayer insulating film 24 to each Co silicide layer of the emitter electrode 21 of the HBT, the external base layer, and the N ⁺ -type collector lead layer 9. A reaching connection hole is formed. Thereafter, a W film is embedded in each connection hole to form a W plug 25, an aluminum alloy film is formed on the interlayer insulating film 24, and a resist film having a predetermined region opened is used as a mask to form an aluminum alloy. By patterning the film, a metal wiring 26 connected to each W plug 25 and extending on the interlayer insulating film 24 is formed. In this way, the semiconductor device of this embodiment is completed.

  When a semiconductor substrate is heated in a vacuum vessel and a silicon-based gas such as silane is supplied, the removal reaction of the silicon oxide film first occurs and then the epitaxial growth proceeds. However, silicon is formed only on the surface of the high-concentration buried layer in the high-speed HBT formation region A. Since the oxide film is formed thick, it takes time to remove the oxide film as compared with other elements such as a PN junction varactor, a lateral PNP transistor, or a high breakdown voltage HBT, and the epitaxial growth is delayed. Then, when the silicon oxide film in the high-speed HBT formation region A is also removed, an N-type Si layer having the second impurity concentration is epitaxially grown. Thereby, the impurity concentration of the N-type Si layer of the PN junction varactor, the lateral PNP transistor, or the high breakdown voltage HBT and the high speed HBT can be changed, so that the former high breakdown voltage characteristic and the latter high frequency characteristic can be further improved. it can.

In this embodiment, the growth condition of the Si single crystal layer 4 is set to a temperature of 800 ° C., but about 700 to 1000 ° C., and the source gas is Si ₂ H ₆ , but SiH ₄ or the like may be used. Further, the case where the high-speed HBT and the lateral PNP transistor are integrated is shown, but it is also effective when the high-voltage HBT, the PN junction varactor and the like are integrated with the high-speed HBT.

  Since the semiconductor device manufacturing method according to the present invention can simultaneously improve the characteristics of each element having different applications mounted on a semiconductor device such as BiCMOS, it is possible to improve the performance of all the elements. The present invention is useful for information / communication devices that can implement a device and require good high-frequency characteristics.

It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing of the next process of FIG. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 4 is a cross-sectional view of the next step of FIG. 3. It is sectional drawing which shows the manufacturing process of the semiconductor device which concerns on the 3rd Embodiment of this invention. FIG. 6 is a cross-sectional view of the next step of FIG. 5. FIG. 7 is a cross-sectional view of the next step of FIG. 6. FIG. 8 is a cross-sectional view of the next step of FIG. 7. FIG. 9 is a cross-sectional view of the next step of FIG. 8. FIG. 10 is a cross-sectional view of the next step of FIG. 9. FIG. 11 is a cross-sectional view of the next step of FIG. 10. FIG. 12 is a cross-sectional view of the next step of FIG. 11. FIG. 13 is a cross-sectional view of the next step of FIG. 12. FIG. 14 is a cross-sectional view of the next step of FIG. 13. FIG. 15 is a cross-sectional view of the next step of FIG. 14. FIG. 16 is a cross-sectional view of the next step of FIG. 15. FIG. 16 is a cross-sectional view of the next step of FIG. 15. FIG. 18 is a cross-sectional view of the next step of FIG. 17.

Explanation of symbols

1 P-type Si substrate 2 N ⁺ buried impurity layer 3 silicon oxide film 4 Si single crystal layer 4a first impurity concentration Si single crystal layer 4b second impurity concentration Si single crystal layer 5 shallow trench 6 deep trench 7 Undoped polysilicon film 8 Silicon oxide film 9 N ⁺ type collector lead layer 10 Polysilicon film 11 Side wall 12 Emitter layer 13 Collector layer 14 Base lead electrode 15 Silicon oxide film 16 Polysilicon film 17a Single crystal Si / SiGeC layer 17b Crystalline Si / SiGeC layer 18 Silicon oxide film 19 Polysilicon film 20 Emitter opening 21 Emitter electrode 22 Emitter layer 23 Side wall 24 Interlayer insulating film 25 W plug 26 Metal wiring

Claims (4)

A method of manufacturing a semiconductor device in which elements having different uses and having a single crystal silicon layer are formed in a first region and a second region of a silicon substrate, respectively,
A silicon oxide film is formed on the surfaces of the first region and the second region, and the silicon oxide film formed on the surface of the second region is removed, so that only the surface of the first region is formed. A method of manufacturing a semiconductor device, comprising: epitaxially growing the silicon layer on the silicon substrate after forming the silicon oxide film. A method of manufacturing a semiconductor device in which elements having different uses and having a single crystal silicon layer are formed in a first region and a second region of a silicon substrate, respectively,
After forming a first silicon oxide film on the surface of the first region and forming a second silicon oxide film having a thickness smaller than that of the first silicon oxide film on the surface of the second region, A method of manufacturing a semiconductor device, comprising epitaxially growing the silicon layer on a silicon substrate. When epitaxially growing the silicon layer, the first region has a first impurity concentration after the second silicon oxide film is removed and until the first silicon oxide film is removed. Epitaxially growing the silicon layer,
3. A silicon layer having a second impurity concentration different from the first impurity concentration is epitaxially grown in the first region and the second region after the first silicon oxide film is removed. Semiconductor device manufacturing method.   4. The method of manufacturing a semiconductor device according to claim 1, wherein silane or disilane is used as a silicon source gas when epitaxially growing the silicon layer.

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