JP2006310590A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high performance semiconductor device capable of balancing every performance of each element for various applications mounted on the semiconductor device such as a BiCMOS, and to provide its manufacturing method. <P>SOLUTION: A high concentration phosphoric ion is implanted into a region for forming a pn junction varactor on a p-type Si substrate, and after a carbon is implanted, a low concentration n-type Si layer is formed on the Si substrate. The epitaxial growth of the n-type Si layer at temperatures ranging from approximate 1,000 to 1,200°C causes an impurity in an embedded type impurity layer to rise at the n-type Si layer side, however, the impurity diffusion from the embedded impurity layer in the varactor-forming region with the carbon introduced on its surface is suppressed to suppress the rise of the phosphorous. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device on which various elements such as a bipolar transistor, a MOS transistor, and a varactor are mounted, and a manufacturing method thereof.

  Conventionally, heterojunction bipolar transistors (hereinafter referred to as HBTs) have superior high-speed operability and high current drive capability compared to Si homojunction bipolar transistors, so mobile communications that require high-speed and high-integration, etc. It is used as a communication device. In particular, by incorporating a heterojunction structure such as Si / SiGe or Si / SiGeC into a bipolar transistor, an HBT having a cutoff frequency exceeding 100 GHz has been realized.

  In recent years, HBTs excellent in high-speed performance are integrated with CMOS, lateral PNP transistors, PN junction varactor elements, and the like, and are used for communication devices and the like. As a conventional example of BiCMOS in which a high-speed HBT and a high breakdown voltage HBT are mixedly mounted on the same substrate, a semiconductor device disclosed in Patent Document 1 is known.

In this conventional example, since a concave depression is formed on the surface of the collector layer of the high-speed HBT, the collector layer immediately below the SiGe base layer of the high-speed HBT is relatively thin, and the SiGe. The collector layer directly below the base layer can be made relatively thick, and the optimum CE breakdown voltage can be achieved for each, thus realizing a high-performance semiconductor device that achieves both high breakdown voltage characteristics and high-speed characteristics. Is done.
JP 2002-208641 A (FIG. 1)

  In the structure of the above-described conventional example, in order to further reduce the collector layer of the high-speed HBT, the concave depression must be formed deeply as the performance of the HBT increases. However, if the concave depression is deepened, the surface step of the collector layer increases, and the crystallinity and film composition of the SiGe • base layer formed across the step deteriorates. Further, it is difficult to finely process the emitter electrode formed on the recess.

  In view of the above-described problems, the present invention devised the structure of a high-concentration buried impurity layer and formed an effective epitaxial layer thickness on the buried impurity layer to be different depending on the element. It is an object of the present invention to provide a high-performance semiconductor device capable of making the performance of each element having a different application mounted on the semiconductor device compatible and a method for manufacturing the same.

  The present invention is characterized in that high-concentration buried impurity layers having different amounts of rising impurities are formed. The configuration and principle of the present invention will be described below.

  A first semiconductor device and a method of manufacturing the same according to the present invention implant a high concentration phosphorus (P) ion into a desired element region on a P-type silicon (Si) substrate, for example, a region where a PN junction varactor is formed, After implanting (C), a low concentration N-type Si layer is formed on the Si substrate. Since the N-type Si layer is epitaxially grown at about 1000 to 1200 ° C., the impurities in the buried impurity layer rise to the N-type Si layer side, but the varactor forming region doped with carbon on the upper side is the buried impurity layer. Impurity diffusion from the substrate is suppressed, and the rise of phosphorus can be suppressed.

  The impurity diffusion mechanism of phosphorus in the Si layer containing carbon is described in H.B. Reported by Rucker et al. (IEDM 1999, p. 345). When carbon is present in Si, carbon is present at interstitial positions, and phosphorus cannot move between the interstitial positions, and diffusion can be suppressed.

  As a result, since the diffusion coefficient of phosphorus in the Si layer containing carbon is small, the rising of phosphorus in the varactor formation region is suppressed when forming a low-concentration N-type Si layer thereafter, and the upper position of the buried impurity layer However, since the varactor formation region is relatively lower than the high-speed HBT formation region and the film thickness of the effective low-concentration N-type Si layer is increased, the performance of the PN junction varactor can be improved. Similarly, when a means for suppressing the rise of phosphorus by injecting carbon is applied to the formation region of the lateral PNP transistor and the high breakdown voltage HBT, the lateral PNP transistor and the high breakdown voltage HBT can be improved in performance.

  Next, the second semiconductor device and the manufacturing method thereof according to the present invention inject phosphorus into a desired element region on the P-type silicon substrate, for example, a region where a PN junction varactor, a lateral PNP transistor or a high breakdown voltage HBT is formed. After arsenic (As) or antimony (Sb) is implanted into the high-speed HBT formation region, a carbon-doped Si layer is grown on the P-type silicon substrate, and then a low-concentration N-type Si layer is formed. Since the N-type Si layer is epitaxially grown at about 1000 to 1200 ° C., impurities in the buried impurity layer rise to the N-type Si layer side, but carbon exists on the interface side below the N-type Si layer. Thus, the diffusion of phosphorus is suppressed, and conversely, arsenic or antimony has no or little effect of suppressing this diffusion, so that the amount of arsenic or antimony injection in the region is larger than that of phosphorus.

  As a result, the effective N-type Si layer thickness on the phosphorus implantation region becomes larger than the effective N-type Si layer thickness on the arsenic or antimony implantation region. The PN junction varactor, the lateral PNP transistor or the high breakdown voltage HBT can be improved in performance without lowering.

  As described above, according to the semiconductor device and the manufacturing method thereof according to the present invention, by forming Si epitaxial layers having different thicknesses effectively depending on desired elements, the semiconductor device such as BiCMOS can be used. Since the characteristics of different elements can be improved at the same time, it is possible to realize a high-performance semiconductor device that can improve the performance of all elements.

(First embodiment)
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described in detail with reference to the drawings. The semiconductor device of this embodiment includes a high-speed HBT and a PN junction varactor. FIG. 1 is a cross-sectional view of a high-speed HBT and a PN junction varactor according to this embodiment.

As shown in FIG. 1, a P-type Si substrate 1 and a high-concentration N ⁺ buried impurity layer 2 formed on the surface portion of the P-type Si substrate 1 are provided, and ions are formed only in the formation region of the PN junction varactor. It has a carbon-doped Si layer 4 formed by implantation. On the high-concentration N ⁺ buried type impurity layer 2, a Si single crystal layer 3 is formed by epitaxial growth and functions as a collector. Here, as will be described later, the effective thickness of the N-type Si single crystal layer 3 is larger in the varactor formation region than in the HBT formation region. Further, a shallow trench 5 made of a silicon oxide film, a deep trench 6 formed below the shallow trench 5 and made of a silicon oxide film 8 and a polysilicon film 7, and a collector are spaced apart from each other across the shallow trench 5. And an N ⁺ -type collector extraction layer 9 formed.

Furthermore, a single crystal Si / SiGeC layer 30a and a polycrystalline Si / SiGeC layer 30b formed on the Si single crystal layer 3 and a single crystal Si / SiGeC layer 30a are formed, and an emitter opening is formed. A silicon oxide film 31, an emitter electrode 33 made of a polysilicon film that fills the emitter opening and contacts the single crystal Si / SiGeC layer 30 a, and silicon formed on the side surfaces of the emitter electrode 33 and the silicon oxide film 31. And a sidewall 36 made of an oxide film. A silicide layer (not shown) is formed on the emitter electrode 33, the polycrystalline Si / SiGeC layer 30 b and the N ⁺ -type collector lead layer 9. Here, the opening region of the silicon oxide film 31 in the portion sandwiched between the emitter electrode 33 and the N-type Si single crystal layer 3 (collector layer) in the single crystal Si / SiGeC layer 30a is the intrinsic base layer. . Further, an external base layer is constituted by a portion of the Si / SiGeC layer 30a excluding the intrinsic base layer and the polycrystalline Si / SiGeC layer 30b. Note that the SiGeC film of this embodiment has a graded composition so that the band gap gradually decreases from the emitter side to the collector side. Further, on the P-type Si substrate 1, an interlayer insulating film 38 made of a silicon oxide film covering the emitter electrode 33 and the external base layer, and the HBT emitter electrode 33, the external base layer and the NBT through the interlayer insulating film 38 are provided. W plugs 39 filling the connection holes reaching the respective Co silicide layers of the ⁺ type collector lead layer 9, and metal wirings 40 formed on the interlayer insulating film 38 and made of an aluminum alloy film connected to the respective W plugs 39, Is provided.

  Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. 2 to 12 are cross-sectional views showing manufacturing steps of the bipolar transistor according to the first embodiment of the present invention. Note that a description of the resist film removal step is omitted.

First, as shown in FIG. 2A, an N-type buried impurity layer 2 is formed on the upper surface of a P-type Si substrate 1 having a (001) plane as a main surface by using photolithography. A resist film (not shown) having openings in the regions to be formed (HBT formation region and varactor formation region) is formed. Next, using the resist film as an implantation mask, phosphorus ions are implanted into the Si substrate 1 under conditions of an acceleration energy of about 30 keV and a dose of about 1 × 10 ¹⁵ cm ⁻² . Thereafter, heat treatment is performed at a temperature of about 1000 ° C. for about 30 minutes. Subsequently, only the varactor formation region is opened using lithography, and carbon ions are implanted under the conditions of an acceleration energy of about 45 keV and a dose amount of 1 × 10 ¹⁵ cm ⁻² , and the carbon-doped Si layer 4 is formed on the surface of the varactor formation region. Form.

Next, as shown in FIG. 2B, the Si single crystal layer 3 is epitaxially grown on the P-type Si substrate 1 while in-situ doping with N-type impurities. At this time, the concentration of the N-type impurity in the Si single crystal 3 is about 1 × 10 ¹⁵ cm ⁻³ , the peak concentration of phosphorus in the embedded impurity layer 2 is about 6 × 10 ¹⁷ cm ⁻³ , and carbon-doped Si The carbon concentration in the layer 4 is about 1 × 10 ¹⁷ cm ⁻³ .

  Here, as shown in FIG. 2B, in the HBT formation region and the varactor formation region, the position of the upper portion of the buried impurity layer is higher in the HBT formation region. This is due to the effect that the carbon introduced into the varactor forming region suppresses the rise of phosphorus to the Si single crystal layer 3. Therefore, the effective thickness of the N-type Si single crystal layer 3 is about 100 to 150 nm thicker in the varactor formation region than in the HBT formation region.

  Further, at the bottoms of the HBT formation region and the varactor formation region, the buried impurity layer 2 has the same diffusion depth, or the HBT formation region embedded with a large amount of impurity rise due to the effect of suppressing the diffusion of phosphorus. The diffusion depth of the type impurity layer 2 is larger than the diffusion depth of the buried type impurity layer 2 in the varactor formation region where the amount of rising impurities is small.

  Next, in the process shown in FIG. 3, a shallow trench 5 in which a silicon oxide film is embedded and a deep trench 6 constituted by an undoped polysilicon film 7 and a silicon oxide film 8 surrounding the undoped polysilicon film 7 are formed as isolation layers. . The depths of the trenches 5 and 6 are about 0.3 μm and about 3 μm, respectively.

Next, as shown in FIG. 4, a resist film (not shown) having openings in the formation regions of the N ⁺ -type collector extraction layer 9 and the N ⁺ -type extraction layer 10 is formed, and the resist film is used as an implantation mask. After selectively implanting phosphorus (P) ions into the Si single crystal layer 3 under conditions of an acceleration energy of about 60 keV and a dose of 3 × 10 ¹⁵ cm ⁻² , the resist film is removed using oxygen plasma ashing. Subsequently, a heat treatment is performed at a temperature of about 850 ° C. for about 30 minutes. Further, arsenic is implanted under the conditions of an acceleration energy of about 50 keV and a dose amount of 3 × 10 ¹⁵ cm ⁻² to form an N ⁺ -type collector extraction layer 9. N ⁺ type extraction layer 10 is formed.

Next, phosphorus is implanted into the PN junction varactor using photolithography and ion implantation under conditions of an acceleration energy of about 50 to 640 keV and a dose of 1 × 10 ¹² cm ⁻² to 1 × 10 ¹³ cm ^−2. Then, boron (B) is implanted under the conditions of an N type diffusion layer 12 and an acceleration energy of about 5 keV and a dose of about 2 × 10 ¹⁵ cm ⁻² to form a P type diffusion layer 11. Subsequently, heat treatment is performed at a temperature of about 1000 ° C. for a time of about 10 to 15 seconds to activate the impurities.

  Next, as shown in FIG. 5, a silicon oxide film 28 having a thickness of about 50 nm is deposited on the substrate by a low pressure CVD method. Subsequently, a polycrystal having a thickness of about 100 nm is formed on the silicon oxide film 28 by a low pressure CVD method. A silicon film 29 is deposited.

  Next, as shown in FIG. 6, a resist film (not shown) having an HBT formation region opened is formed using photolithography, and the polysilicon film 29 is patterned by etching using the resist film as an etching mask. Then, a region for forming the external base layer is opened. Next, the resist film is removed using oxygen plasma ashing, and subsequently, the silicon oxide film 28 exposed at the opening of the polysilicon film 29 is removed with hydrofluoric acid, and phosphorus is implanted into the Si single crystal layer. The surface of 3 is exposed.

  Next, as shown in FIG. 7, after a Si buffer layer of about 70 nm is grown on the substrate by UHV-CVD, a SiGeC film and a Si film are sequentially epitaxially grown. At this time, a Si / SiGeC layer 30a having a thickness of about 100 nm made of a SiGeC film having a thickness of about 70 nm and a Si film having a thickness of about 30 nm is grown on the Si single crystal layer 3, and the shallow trench 5 (silicon On the oxide film) and the polysilicon film 29, a polycrystal having a thickness of about 80 nm comprising a polycrystal Si having a thickness of about 30 nm, a polycrystal SiGeC film having a thickness of 35 nm, and a polycrystal Si film having a thickness of about 15 nm. The Si / SiGeC layer 30b is grown. Further, boron (B) is introduced into the SiGeC film by in-situ doping, and the SiGeC film is P-type.

Next, as shown in FIG. 8, by a low pressure CVD method, a silicon oxide film 31 having a thickness of about 30 nm and a polycrystal containing phosphorus having a thickness of about 50 nm and a concentration of about 3 × 10 ¹⁵ cm ⁻³ are formed on the substrate. A silicon film 32 is continuously deposited. Thereafter, using photolithography, a resist film (not shown) having an emitter forming region opened is formed, and using the resist film as an etching mask, the polysilicon film 32 is patterned by dry etching to form an emitter opening. 45 is formed. Thereafter, the silicon oxide film 31 in the emitter opening 45 is removed by wet etching.

Next, as shown in FIG. 9, N-type impurities (phosphorus) having a film thickness of about 400 nm and a concentration of about 1 to 5 × 10 ²⁰ cm ⁻³ are formed on the substrate by low pressure CVD with in-situ doping. N ⁺ type polysilicon containing is deposited. Subsequently, a resist film covering the emitter electrode portion is formed on the N ⁺ type polysilicon film 32 by photolithography. Then, using the resist film as an etching mask, the polysilicon film is patterned by anisotropic etching to form the emitter electrode 33. Subsequently, using the resist film and the emitter electrode 33 as an etching mask, a portion of the silicon oxide film 31 that is not covered with the emitter electrode 33 is removed by wet etching.

Next, in order to reduce the resistance of the external base, the acceleration energy is about 5 keV from the direction substantially perpendicular to the substrate surface (the direction having only an inclination not to cause channeling) to the Si / SiGeC layers 30a and 30b. Additional boron is implanted under the condition of a dose amount of 2 × 10 ¹⁵ cm ⁻³ .

  Next, as shown in FIG. 10, the resist film used for patterning the emitter electrode 33 is removed by oxygen plasma ashing. Thereafter, a resist film is formed by photolithography to cover the emitter electrode 33 and the polycrystalline Si / SiGeC layer 30b as a region serving as an external base layer, and the polycrystalline Si / SiGeC layer is formed using the resist film as an etching mask. A portion of 30b located outside the outer base layer is removed.

Next, as shown in FIG. 11, after a silicon oxide film having a thickness of about 30 to 100 nm is deposited on the substrate by low pressure CVD, the temperature is about 900 ° C. and the time is about 10 to 15 seconds. The emitter layer 35 is formed by diffusing phosphorus from the emitter electrode 33 into the Si film in the Si / SiGeC layer 30a. Subsequently, after depositing a silicon oxide film on the substrate, the silicon oxide film is anisotropically etched to form sidewalls 36 on the side surfaces of the emitter electrode 33. At this time, the silicon layer is exposed on the upper surface of the emitter electrode 33 of the HBT, the upper surface of the Si / SiGeC layer 30b, and the upper surface of the N ⁺ -type collector extraction layer 9.

Next, as shown in FIG. 12, after a Co film is formed on the substrate by sputtering, the Co and Si are reacted by heating to react with the upper part of the emitter electrode 33 of the HBT and the upper part of the Si / SiGeC layer 30b. A Co silicide layer is formed on the N ⁺ -type collector lead layer 9. Thereafter, the unreacted layer of Co and Si is removed, and then the Co silicide layer is annealed to reduce the resistance of the Co silicide layer. Thus, a part of the Si / SiGeC layer 30a, an external base layer composed of the Si / SiGeC layer 30b and the Co silicide layer is formed.

In the subsequent steps, a well-known multilayer wiring process is used. That is, after depositing an interlayer insulating film 38 made of a silicon oxide film on the substrate, it penetrates through the interlayer insulating film 38 and is applied to each Co silicide layer of the emitter electrode 33 of the HBT, the external base layer, and the N ⁺ -type collector lead layer 9. A reaching connection hole is formed. Thereafter, a W film is embedded in each connection hole to form a W plug 39, an aluminum alloy film is formed on the interlayer insulating film 38, and a resist film having a predetermined region opened is used as a mask to form an aluminum alloy film. By patterning the film, metal wiring 40 connected to each W plug 39 and extending on the interlayer insulating film 38 is formed. In this way, the semiconductor device of this embodiment shown in FIG. 1 is completed.

In this embodiment, the case where the PN junction varactor is integrated in the high-speed HBT has been described. However, the present embodiment is also effective in the case where a high breakdown voltage HBT, a lateral PNP transistor, and the like are integrated with the high-speed HBT. That is, by suppressing the rising of the buried impurity layer in the formation region of the lateral PNP transistor and the high breakdown voltage HBT by introducing carbon, the current amplification factor (h _FE ) of the lateral PNP transistor and the breakdown voltage of the high breakdown voltage HBT are reduced. Can be improved.

Further, in this embodiment, carbon is implanted into the entire surface of the PN junction varactor formation region, but it may be implanted only into the formation portion of the P-type diffusion layer 11 excluding the formation portion of the N ⁺ extraction layer 10. This increases the amount of the buried impurity layer 3 that rises in the portion where the N ⁺ -type extraction layer 10 is formed, and the parasitic resistance in this portion can be reduced.

(Second Embodiment)
Next, a semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described. The semiconductor device of this embodiment includes a high-speed HBT and a PN junction varactor.

First, as shown in FIG. 13A, an N-type buried impurity layer is to be formed on the upper surface of the P-type Si substrate 1 having the (001) plane as a main surface by using photolithography. A resist film (not shown) having an open region is formed. Next, using the resist film as an implantation mask, arsenic is implanted into the HBT formation region of the Si substrate 1 under conditions of an acceleration energy of about 30 keV and a dose of about 4 × 10 ¹⁵ cm ⁻² , and the varactor formation region is accelerated energy. Phosphorus is implanted under conditions of about 30 keV and a dose of about 1 × 10 ¹⁵ cm ⁻² . Thus, N-type buried impurity layers 2a and 2b having a depth of about 1 μm are formed in the HBT formation region and the varactor formation region, respectively. Thereafter, heat treatment is performed at a temperature of about 1000 ° C. for about 30 minutes.

Next, the Si single crystal layer 4 is grown by in-situ doping with carbon under the conditions of a pressure of 200 Pa and a growth temperature of about 1000 ° C. using trichlorosilane (SiHCl ₃ ) and propane (C ₃ H ₈ ) by CVD. Then, as shown in FIG. 13B, the Si single crystal layer 3 is epitaxially grown while in-situ doping with N-type impurities. At this time, the film thickness of the carbon doped layer 4 is preferably in the range of 1 nm or more and 20 nm or less, and more preferably about 5 nm in this range. The film thickness of the n-type impurity epitaxial layer 3 is about 450 nm. At this time, the concentration of arsenic in the embedded impurity layer 2a is about 6 × 10 ¹⁹ cm ⁻³ , the concentration of phosphorus in the embedded impurity layer 2b is about 6 × 10 ¹⁷ cm ⁻³ , and the carbon in the Si single crystal layer 4 is The concentration is about 1 × 10 ¹⁷ cm ⁻³ . Further, in the HBT formation region and the varactor formation region, the position of the upper portion of the buried impurity layer is higher in the HBT formation region.

  This is due to the effect that the diffusion coefficients of arsenic and phosphorus implanted in the buried layer differ greatly depending on the carbon doping. Due to this effect, the amount of N-type impurities rising to the Si single crystal layer 3 is different, and the upper portion of the buried impurity layer in the HBT formation region and the varactor formation region is higher in the HBT formation region. Therefore, the effective thickness of the N-type Si single crystal layer 3 is about 100 to 150 nm thicker in the varactor formation region than in the HBT formation region.

  In the subsequent steps, the high-speed HBT and the PN junction varactor are formed using the same manufacturing steps as those in the first embodiment. In this way, the semiconductor device of this embodiment shown in FIG. 14 is completed.

  As described above, the present invention is useful for information / communication devices that require good high-frequency characteristics.

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Explanation of symbols

1 P-type Si substrate 2 N ⁺ buried impurity layer 3 Si single crystal layer 4 carbon-doped Si layer 5 shallow trench 6 deep trench 7 undoped polysilicon film 8 silicon oxide film 9 N ⁺ -type collector extraction layer 10 N ⁺ type extraction layer 11 P-type diffusion layer 12 N-type diffusion layer 28 Silicon oxide film 29 Polysilicon film 30a Monocrystalline Si / SiGeC layer 30b Polycrystalline Si / SiGeC layer 31 Silicon oxide film 32 Polysilicon film 33 Emitter electrode 35 Emitter layer 36 Side Wall 38 Interlayer insulating film 39 W plug 40 Metal wiring 45 Emitter opening

Claims (10)

A semiconductor device having two or more semiconductor elements having different uses,
Two or more high-concentration buried impurity layers formed on a semiconductor substrate;
A low-concentration epitaxial layer formed on the buried impurity layer,
A semiconductor device, wherein at least the first buried impurity layer and the second buried impurity layer have different amounts of rising impurities. The impurity in the buried impurity layer is phosphorus,
2. The semiconductor device according to claim 1, wherein carbon is doped on an upper portion of the second buried impurity layer. The diffusion depth of the first embedded impurity layer is the same as that of the two or more buried impurity layers, or the amount of rise of the impurity is large. 3. The semiconductor device according to claim 2, wherein the depth is larger than a diffusion depth of the buried impurity layer. The impurity in the first buried impurity layer is arsenic or antimony,
The impurity in the second buried impurity layer is phosphorus,
2. The semiconductor device according to claim 1, wherein carbon is doped in a lower portion of the epitaxial layer. A high-speed bipolar transistor is disposed in the formation region of the first buried impurity layer with a large amount of impurities rising,
5. The high breakdown voltage bipolar transistor, lateral PNP transistor, or PN junction varactor is disposed in the formation region of the second buried impurity layer in which the amount of rising impurities is small. 2. The semiconductor device according to claim 1. The semiconductor device according to claim 1, wherein at least a part of the two or more buried impurity layers are connected to each other. A method of manufacturing a semiconductor device having two or more semiconductor elements having different uses,
Forming a buried impurity layer having a high concentration of 2 or more on a semiconductor substrate;
Forming a low-concentration epitaxial layer on the buried impurity layer,
A method of manufacturing a semiconductor device, wherein at least the first buried impurity layer and the second buried impurity layer have different amounts of rising impurities. The step of forming the buried impurity layer includes a step of implanting phosphorus into the formation region of the buried impurity layer and a step of implanting carbon into the formation region of the second buried impurity layer. A method for manufacturing a semiconductor device according to claim 7. The step of forming the buried impurity layer includes a step of implanting arsenic or antimony into the formation region of the first buried impurity layer and a step of implanting phosphorus into the formation region of the second buried impurity layer. Including
8. The method of manufacturing a semiconductor device according to claim 7, wherein the epitaxial layer forming step forms the low-concentration epitaxial layer after forming a semiconductor layer doped with carbon. Forming a high-speed bipolar transistor in the formation region of the first buried impurity layer having a large amount of impurities;
10. A high-voltage bipolar transistor, a lateral PNP transistor, or a PN junction varactor is formed in a formation region of the second buried impurity layer with a small amount of impurities rising. A method for manufacturing the semiconductor device according to the item.

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