JP2004311971A - Bipolar transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a hetero-junction bipolar transistor having high-speed operation properties/high-current driving force, and to provide its manufacturing method. <P>SOLUTION: A bipolar transistor is provided with an Si single crystal layer 3 functioning as a collector, a single crystal Si/SiGeC layer 30a and a polycrystalline Si/SiGeC layer 30b formed on the Si single crystal layer 3, an oxide film 31 having an emitter opening part, an emitter electrode 50, and an emitter layer 35. An intrinsic base layer 52 is formed in the single crystal Si/SiGeC layer 30a, and an external base layer 51 is formed of a part of the single crystal Si/SiGeC layer 30a, the polycrystalline Si/SiGeC layer 30b, and a Co silicide layer 37b. The thickness of the emitter electrode is set in such a manner that boron implanted in the emitter electrode 50 does not diffuse in the emitter electrode 50 to reach an emitter-base joint. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a bipolar transistor and a method of manufacturing the same, and more particularly, to a structure of a high-performance bipolar transistor having a heterojunction such as Si / SiGe or Si / SiGeC and a method of manufacturing the same.

  Conventionally, heterojunction bipolar transistors have superior high-speed operability and high current driving capability compared to Si homojunction bipolar transistors, so they are used as communication devices such as mobile communication that require high speed and high integration. Have been. In particular, in recent years, a heterojunction structure such as Si / SiGe or Si / SiGeC has been incorporated into a bipolar transistor to realize a heterojunction bipolar transistor (hereinafter, referred to as an HBT) having a cutoff frequency exceeding 100 GHz.

  As a conventional example of a method of manufacturing such a heterojunction bipolar transistor, a method disclosed in Patent Document 1 is known.

The features of this conventional HBT manufacturing method are that ions are implanted into the external base layer (polycrystalline SiGe film) and the influence of the lateral spread of impurities implanted into the polysilicon emitter electrode (emitter contact layer). It is to reduce by a spacer. At this time, the polysilicon film thickness of the polysilicon emitter electrode is about 140 nm, and the conditions for additional implantation into the external base layer are as follows. In the case of boron (B), the acceleration energy is 60 keV and the dose is about 2 × 10 ¹⁵ cm ^−2. In the case of boron fluoride (BF ₂ ), the acceleration energy is about 30 keV and the dose is about 1 × 10 ¹⁵ cm ⁻² .
JP-A-9-186172

  However, in the above-described conventional HBT structure, when boron is additionally implanted into the external base layer using the emitter electrode as an implantation mask, boron, which is an impurity of the opposite conductivity type to that in the emitter, is also implanted into the emitter electrode. In order to avoid this, the amount of boron doped into the external base layer must be reduced, and the electric resistance of the external base layer increases. In addition, factors that determine the shape of the emitter electrode include processing limitations such as an alignment margin for a contact hole and the above-described electrical characteristics, and it is basically difficult to achieve both. Therefore, it has been difficult for conventional HBTs to achieve both high-speed operation and high-current driving capability.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a bipolar transistor and a method of manufacturing the bipolar transistor, which can achieve both high-speed operation and high current driving capability by improving the structure of an emitter electrode and the structure of an external base layer. .

  According to the bipolar transistor of the present invention, in the bipolar transistor in which the emitter-intrinsic base junction is a heterojunction, the emitter electrode is diffused such that the concentration of the external base-forming impurity implanted therein is lower at the lower portion. It has a film thickness.

  Thereby, the impurity concentration of the external base layer is increased and the base resistance is reduced while preventing the current driving force of the bipolar transistor from being reduced due to the diffusion of the impurity from the external base into the emitter-intrinsic base junction. Therefore, characteristics such as high-speed operability and high current driving force can be realized.

  When the thickness of the emitter electrode is in the range of 200 nm or more and 500 nm or less, a dent generated in a portion located above the emitter opening on the upper surface of the emitter electrode can be minimized, and the resistance of the silicide layer of the emitter electrode can be reduced. Increase can be suppressed.

  The aspect ratio of the recess on the upper surface of the emitter electrode is preferably 1/5 or less.

  Since the second conductivity type impurity is implanted into a region of the external base layer from a position below the side end of the emitter electrode to a position 230 nm away from the boundary between the emitter layer and the intrinsic base layer, the bipolar transistor is formed. The base resistance can be reduced without adversely affecting the characteristics of the device.

  Preventing the conductive plug formed through the interlayer insulating film from penetrating through the first semiconductor layer by being in contact with the separation layer of the external base layer Can be.

  According to the method of manufacturing a bipolar transistor of the present invention, a second semiconductor layer containing a second conductivity type impurity and a third semiconductor layer are formed on a first conductivity type first semiconductor layer surrounded by an isolation layer. An insulating film having an emitter opening and an emitter electrode containing a first conductivity type impurity are sequentially formed, and the emitter electrode and the insulating film are used as masks to form a second electrode from a direction inclined with respect to a direction perpendicular to the substrate surface. This is a method of injecting two conductivity type impurities into the second and third semiconductor layers.

  According to this method, the second conductivity-type impurity can be implanted into a portion of the second and third semiconductor layers close to the region directly below the emitter opening serving as the intrinsic base layer, so that the base resistance is reduced. be able to. Further, it is possible to independently optimize the electric characteristics and the layout of the emitter electrode.

  When the second conductivity type impurity is implanted into the second and third semiconductor layers, the second conductivity type impurity is not allowed to reach the emitter layer side more than 230 nm from the boundary between the emitter layer and the second semiconductor layer. By implanting impurities of the second conductivity type, adverse effects on the characteristics of the bipolar transistor can be avoided.

  The polycrystalline layer serving as the emitter electrode preferably has a thickness in a range from 200 nm to 500 nm.

  As described above, the characteristics of high-speed operability and high current driving capability can be realized by the bipolar transistor of the present invention or the method of manufacturing the same.

(1st Embodiment)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view of the bipolar transistor according to the first embodiment of the present invention.

  As shown in FIG. 1, a bipolar transistor (HBT) according to the present embodiment includes a P-type Si substrate 1, a sub-collector layer 2 formed on a surface of the Si substrate 1, and a sub-collector layer 2. A Si single crystal layer 3 formed thereon by epitaxial growth and functioning as a collector, a shallow trench 4 formed of a silicon oxide film, and a deep trench formed below the shallow trench 4 and formed of a silicon oxide film 7 and a polysilicon film 6 5 and the sub-collector layer 2 include an N + type collector lead-out layer 8 formed at a site separated from the shallow trench 4.

Further, the bipolar transistor is formed on a single-crystal Si / SiGeC layer 30a and a polycrystalline Si / SiGeC layer 30b formed on the Si single-crystal layer 3, and on a single-crystal Si / SiGeC layer 30a, An oxide film 31 having an emitter opening, a polysilicon film 32 formed on the oxide film 31 and having an emitter opening, and an emitter electrode 50 filling the emitter opening and contacting the single-crystal Si / SiGeC layer 30a. An emitter layer 35 formed on the single crystal Si / SiGeC layer 30a, a sidewall 36 formed of a silicon oxide film formed on the side surfaces of the emitter electrode 50, the polysilicon film 32, and the oxide film 31; Silicide formed on the emitter electrode 50, the Si / SiGeC layers 30a and 30b, and the N + type collector extraction layer 8. It is equipped with 37a, 37b, and 37c. Here, the portion between the emitter layer 35 and the Si single crystal layer 3 (collector layer) in the single crystal Si / SiGeC layer 30a is the intrinsic base layer 52. Further, an external base layer 51 is constituted by a portion of the Si / SiGeC layer 30a other than the intrinsic base layer 52, the polycrystalline Si / SiGeC layer 30b, and the Co silicide layer 37b. Incidentally, SiGeC film of the present embodiment, as will become gradually smaller band gap from the emitter side to the collector side has a graded composition, more precisely represented by Si _1-xy Ge _x C _y Things.

  Further, on the substrate, an interlayer insulating film 38 made of a silicon oxide film covering the emitter electrode 50 and the external base layer 51, an HBT emitter electrode 50, the external base layer 51 and an N + type collector penetrating the interlayer insulating film 38. A W plug 39 filling the connection hole reaching each Co silicide layer 37 of the extraction layer 8 and a metal wiring 40 formed on the interlayer insulating film 38 and made of an aluminum alloy film connected to each W plug 39 are provided. Have been.

  Next, a method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described. 2 to 12 are cross-sectional views illustrating the steps of manufacturing the bipolar transistor according to the first embodiment of the present invention.

First, as shown in FIG. 2, a region where an N-type subcollector layer is to be formed was opened in the upper surface of a P-type Si substrate 1 having a (001) plane as a main surface by using photolithography. A resist film (not shown) is formed. Next, arsenic (As) ions are implanted into the Si substrate 1 using the resist film as an implantation mask to form an N-type subcollector layer 2 having a depth of about 1 μm in the HBT formation region. At this time, the concentration of As in the subcollector layer 2 is about 6 × 10 ¹⁹ cm ⁻³ . Subsequently, the Si single crystal layer 3 (first semiconductor layer) is epitaxially grown on the Si substrate 1 while doping N-type impurities in-situ. At this time, the concentration of the N-type impurity in the Si single crystal 3 is about 1 × 10 ¹⁵ cm ⁻³ .

  Next, in the step shown in FIG. 3, a shallow trench 4 in which a silicon oxide film is buried and a deep trench 5 composed of an undoped polysilicon film 6 and a silicon oxide film 7 surrounding the same are formed as isolation layers. . The depths of the trenches 4 and 5 are about 0.3 μm and about 3 μm, respectively.

Next, in the step shown in FIG. 4, a resist film (not shown) having an opening in the region for forming the N + type collector lead-out layer is formed, and using the resist film as an implantation mask, acceleration energy of about 60 KeV and a dose of 3 × 10 5 After selectively implanting phosphorus (P) ions into the Si single crystal layer 3 under the condition of ¹⁵ cm ⁻² , the resist film is removed using oxygen plasma ashing. Subsequently, a heat treatment is performed at a temperature of about 850 ° C. for about 30 minutes to form an N + type collector extraction layer 8 between the shallow trenches 5 and 5.

Next, using photolithography and ion implantation, arsenic is implanted into the upper portion of the N + -type collector lead-out layer 8 under the conditions of an acceleration energy of about 50 KeV and a dose of 3 × 10 ¹⁵ cm ^−2. The impurities are activated by heat treatment at about 1000 ° C. for about 10 to 15 seconds.

  Next, in a step shown in FIG. 5, an oxide film 28 having a thickness of about 50 nm is deposited on the substrate by a low pressure CVD method, and subsequently, a polysilicon film of about 100 nm is formed on the oxide film 28 by a low pressure CVD method. 29 is deposited.

Next, in the step shown in FIG. 6, a resist film (not shown) having an HBT formation region opened is formed by photolithography, and the polysilicon film 29 is patterned by etching using the resist film as an etching mask. Then, the external base layer forming region is opened. Thereafter, in order to form a phosphorus profile of the collector, the oxide film 28 is converted to phosphorus under the conditions of an acceleration energy of 280 keV and a dose of about 5 × 10 ¹³ cm ⁻³ using the resist film and the polysilicon film 29 as an implantation mask. It is injected into the Si single crystal layer 3 by passing through. Thereby, a desired collector phosphorus profile is formed in Si single crystal layer 3. Next, the resist film is removed by using oxygen plasma ashing, and then the oxide film 28 exposed at the opening of the polysilicon film 29 is removed with hydrofluoric acid, and the Si single crystal layer 3 into which phosphorus is implanted is removed. Expose the surface.

  Next, in the step shown in FIG. 7, after a Si buffer layer of about 60 nm is epitaxially formed on the substrate by UHV-CVD, a SiGeC film (second semiconductor layer) and a Si film (third semiconductor layer) Layer) is epitaxially grown to form a Si / SiGeC layer. At this time, an Si / SiGeC layer 30a having a thickness of about 100 nm comprising a SiGeC film having a thickness of about 70 nm and a Si film having a thickness of about 30 nm is grown on the Si single crystal layer 3, and the shallow trench 4 (oxidized) is formed. Film) and a polysilicon film 29, a polycrystalline Si film having a thickness of about 30 nm, a polycrystalline SiGeC film having a thickness of 35 nm, and a polycrystalline Si film having a thickness of about 15 nm A Si / SiGeC layer 30b is grown. Further, boron (B) is introduced into the SiGeC film by in-situ doping, and the SiGeC film is P-type.

  Here, the UHV-CVD method in which a SiGeC film is epitaxially grown in a high vacuum state is a growth method in which the growth rate is strongly dependent on the plane orientation because the growth reaction occurs only on the surface. Using this phenomenon, the crystal growth rate differs between the surface of the Si single crystal layer (for example, the (100) plane) and the surface of the polysilicon layer or the oxide film. In other words, the growth rate on the surface of the polysilicon film having many crystal orientations or the insulating film which is an amorphous layer becomes slow. According to the experiment, the growth rate on the polysilicon layer and the oxide film was about half of that on the (100) plane of the Si single crystal layer. The same applies to a Si film grown in a high vacuum state following the SiGeC film. Therefore, the thickness of the Si / SiGeC layer 30b is about 50 nm. As described above, by using the UHV-CVD method, it is possible to grow the polycrystalline Si / SiGeC layer 30b, which is a main part of the external base layer, at a low growth rate, and among the external base layers, the electric resistance is high. The thickness of the polycrystalline SiGeC film is smaller than the thickness of the single crystal SiGeC film serving as the intrinsic base layer. As a result, the intrinsic base layer and the silicide film which will be a part of the external base layer to be formed later are continuously connected, the distance between them is further reduced, and the performance of the bipolar transistor can be improved by the low base resistance. Will be.

Next, in a step shown in FIG. 8, an oxide film 31 having a thickness of about 30 nm and a polysilicon containing phosphorus having a thickness of about 50 nm and a concentration of about 3 × 10 ¹⁵ cm ⁻³ are formed on the substrate by a low pressure CVD method. The film 32 is continuously deposited. Thereafter, a resist film (not shown) having an opening in the emitter formation region is formed by photolithography, and the polysilicon film 32 is patterned by dry etching using the resist film as an etching mask to form an emitter opening. 45 is formed. Thereafter, oxide film 31 in emitter opening 45 is removed by wet etching.

Next, in a step shown in FIG. 9, an N-type impurity (phosphorus) having a thickness of about 400 nm and a concentration of about 1 to 5 × 10 ²⁰ cm ⁻³ is deposited on the substrate by low-pressure CVD with in-situ doping. N + -type polysilicon 33 including the silicon is deposited. Subsequently, a resist film 46 covering the emitter electrode portion is formed on the N + type polysilicon film 33 by photolithography. Then, using the resist film 46 as an etching mask, the polysilicon films 33 and 32 are patterned by anisotropic etching to form an emitter electrode 50. Subsequently, using the resist film 46 and the emitter electrode 50 as an etching mask, a portion of the oxide film 31 that is not covered by the emitter electrode 50 is removed by wet etching. The thickness of the polysilicon film 33 is preferably in the range of 200 nm or more and 500 nm or less, and more preferably 300 nm or more in this range.

Next, in order to reduce the resistance of the external base, the Si / SiGeC layers 30a and 30b are provided with an acceleration energy of about 5 KeV, in a direction substantially perpendicular to the substrate surface (a direction having only an inclination that does not cause channeling). Additional implantation of boron is performed under the condition of a dose amount of 2 × 10 ¹⁵ cm ⁻³ .

  Next, in the step shown in FIG. 10, the resist film 46 is removed by oxygen plasma ashing. Thereafter, a resist film 47 is formed by photolithography to cover a region to be an external base layer in the emitter electrode 50 and the polycrystalline Si / SiGeC layer 30b, and the polycrystalline Si / SiGe / SiGeC layer is formed using the resist film 47 as an etching mask. A portion of the SiGeC layer 30b located outside the external base layer is removed.

  Next, in a step shown in FIG. 11, after depositing an oxide film having a thickness of about 30 to 100 nm on the substrate by a low pressure CVD method, the temperature is about 900 ° C. and the time is about 10 to 15 seconds. By performing a heat treatment, arsenic is diffused from the emitter electrode 50 into the Si film in the Si / SiGeC layer 30a to form the emitter layer 35. Subsequently, after an oxide film is deposited on the substrate, the oxide film is anisotropically etched to form a sidewall 36 on the side surface of the emitter electrode 50. At this time, the silicon layer is exposed on the upper surface of the emitter electrode 50 of the HBT, the upper surfaces of the Si / SiGeC layers 30a and 30b, and the upper surface of the N + type collector lead layer 8.

  Next, in the step shown in FIG. 12, after forming a Co film on the substrate by sputtering, Co and Si are reacted by heating to form an upper portion of the HBT emitter electrode 50, the Si / SiGeC layers 30a, 30b. And Co silicide layers 37a, 37b and 37c are formed on the upper portion of the N + type collector lead layer 8. Thereafter, the unreacted layer of Co and Si is removed, and then the Co silicide layers 37a, 37b, 37c are annealed to lower the resistance of the Co silicide layers 37a, 37b, 37c. Thus, an external base layer 51 composed of a part of the Si / SiGeC layer 30a, the Si / SiGeC layer 30, and the Co silicide layer 37b is formed.

  In the subsequent steps, a standard multilayer wiring process is used. That is, after depositing an interlayer insulating film 38 made of an oxide film on the substrate, the Co silicide layers 37a of the HBT emitter electrode 50, the external base layer 51, and the N + type collector lead layer 8 penetrate through the interlayer insulating film 38. A connection hole reaching 37b and 37c is formed.

  Thereafter, a W film is buried in each connection hole to form a W plug 39, and then an aluminum alloy film is formed on the substrate by sputtering, and the aluminum alloy film is formed using a resist film having a predetermined region opened as a mask. By patterning the film, a metal wiring 40 connected to each W plug 39 and extending above the interlayer insulating film 38 is formed.

  In the present embodiment, the impurity concentration profile in the Si single crystal from immediately below the base layer to the subcollector layer is formed by a single phosphorus implantation, but in order to optimize the impurity concentration profile, multi-stage implantation is performed. Alternatively, self-aligned implantation using an emitter opening mask (polysilicon film 32 shown in FIG. 8) may be used.

  According to the present embodiment, the following effects can be obtained.

  First, the emitter electrode 50 is formed of a polysilicon film having a thickness of about 400 nm. In the conventional bipolar transistor described in Patent Document 1, the thickness of the polysilicon film forming the emitter electrode is 140 nm, whereas in the present embodiment, the thickness of the polysilicon film 33 forming the emitter electrode 50 is reduced. The film thickness is 400 nm, which is extremely large.

  The thickness of the emitter electrode 50 (polysilicon film 33) is set so that the boron implanted into the emitter electrode 50 diffuses in the emitter electrode 50 and does not reach the emitter-base junction in the step shown in FIG. Have been.

  Further, since the polysilicon film constituting the emitter electrode is thick, the upper surface of the emitter electrode 50 in the present embodiment hardly has a concave portion corresponding to the emitter opening.

  FIG. 15 is a diagram showing the amount of depression on the upper surface of the emitter electrode with respect to the thickness of the emitter electrode polysilicon film. As shown in the figure, when the thickness of the polysilicon film is about 150 nm, the amount of depression on the upper surface of the emitter electrode is large. If there is a deep recess on the upper surface of the emitter electrode 50, the formation of the silicide layer 37c may cause the silicide layer 37c to become thinner, and the contact resistance may increase. On the other hand, in the emitter electrode 50 of the present embodiment, the contact resistance can be reliably kept low. Here, as shown in FIG. 15, in order to surely keep the contact resistance with respect to the emitter electrode 50 low, the aspect ratio of the recess on the upper surface of the emitter electrode 50 must be 1/5 or less, preferably 1/10 or less. Is preferred. In the present embodiment, since the width of the emitter electrode 50 is about 0.7 μm, the thickness of the polysilicon film 33 is preferably 200 nm or more, and more preferably 300 nm or more. On the other hand, since the thickness of the interlayer insulating film 38 is about 1 μm, it is preferable that the thickness of the polysilicon film be 500 nm or less in consideration of insulation and workability.

  Further, in the manufacturing method of the present embodiment, it is possible to form a polycrystalline SiGe film serving as an external base at a low growth rate by using the UHV-CVD method. The thickness of the Si / SiGeC layer 30b is smaller than the thickness of the single crystal Si / SiGeC layer 30a in the intrinsic base layer 52. As a result, the distance between the intrinsic base layer 52 and the silicide layer 37b of the external base layer 51 is shortened, and the performance of the bipolar transistor can be improved by the low base resistance.

(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. FIG. 13 and FIG. 14 are cross-sectional views showing a manufacturing process of the bipolar transistor according to the second embodiment of the present invention.

  Also in this embodiment, the steps from the step shown in FIG. 1 (the step of forming the subcollector layer 2 on the P-type Si substrate 1) to the step shown in FIG. 8 (the step of forming the emitter opening) in the first embodiment are performed. .

Next, in the present embodiment, a step shown in FIG. 13 is performed instead of the step shown in FIG. 9 in the first embodiment. That is, following formation of the emitter electrode 50 by patterning the polysilicon film 33, the oxide film 31 is patterned by wet etching with the resist film 46 left. Thereafter, an oblique implantation step of implanting boron into the Si / SiGeC layers 30a, 30b from a direction inclined by about 25 ° with respect to a direction perpendicular to the substrate is performed in four steps while rotating the substrate by 90 ° ( 4 step injection). As a result, boron is introduced into a region of the Si / SiGeC layer 30a located below the oxide film 31, that is, a region closer to the intrinsic base layer 52 than the end of the emitter electrode 50. At this time, the implantation energy is 10 KeV, and the total dose amount for four times is about 1.5 × 10 ¹⁴ cm ⁻³ .

Further, in order to reduce the resistance of the external base layer with the resist film 46 still attached, the acceleration energy is about 5 KeV and the dose is 2 × 10 from a substantially vertical direction (a direction having only an inclination that does not cause channeling). ^Under the condition of ¹⁵ cm ^-3 , additional implantation of boron is performed.

  Next, in the step shown in FIG. 14, the resist film 46 is removed by oxygen plasma ashing. Thereafter, a resist film 47 is formed by photolithography to cover a region to be an external base layer in the emitter electrode 50 and the polycrystalline Si / SiGeC layer 30b, and the polycrystalline Si / SiGe / SiGeC layer is formed using the resist film 47 as an etching mask. The portion of the SiGeC layer 30b located outside the external base layer and the oxide film 29 thereunder are removed. Thus, the external base layer 51 is formed as in the first embodiment. Thereafter, the same steps as those shown in FIGS. 10 to 12 of the first embodiment are performed.

  According to the manufacturing method of the present embodiment, as the boron implantation into the external base portion, the oblique implantation is performed in which the Si / SiGeC layers 30a and 30b are implanted from the direction inclined with respect to the direction perpendicular to the main surface of the substrate. Then, boron is introduced into a region of the Si / SiGeC layer 30a, which is a high resistance portion of the external base layer 51, located below the oxide film 31, that is, a region closer to the intrinsic base layer 52 than the end of the emitter electrode 50. can do. Therefore, the base resistance can be reduced. In addition, if the inclination angle of the oblique implantation is appropriately adjusted (for example, to 25 °) in terms of production, the external base layer 51 which affects the electrical characteristics can be removed from the emitter-base junction (the emitter layer 35 and the intrinsic base layer 52). It is possible to determine the shape of the emitter electrode from a processing point of view without worrying about the lateral spread of the high-concentration boron in the boundary region of the emitter electrode. This facilitates improvement in yield and application to large-scale integrated circuits. Therefore, high speed operation and high current driving force of the bipolar transistor can be realized.

  On the other hand, by obliquely implanting impurity ions, boron as a P-type impurity is also introduced into the emitter electrode 50 including an N-type impurity. Therefore, when the thickness of the polysilicon film constituting the emitter electrode is small, there is a concern that adverse effects on device characteristics such as penetration of boron and an increase in resistance of the emitter electrode may be caused. On the other hand, in the present invention, since the thickness of the polysilicon film constituting the emitter electrode is set to about 400 nm, which is thicker than usual, the total amount of N-type impurities is large, and the effects of boron penetration and resistance increase are compared. It is possible to make it difficult to target. That is, also in the present embodiment, the thickness of the emitter electrode 50 (polysilicon film 33) is such that the boron injected into the emitter electrode 50 diffuses in the emitter electrode 50 in the process shown in FIG. It is set not to reach the joint.

FIG. 16 is data showing the relationship between the implantation energy and the peak cutoff frequency f _T of the bipolar transistor when oblique implantation is performed at an inclination angle of 25 ° during base formation under the conditions of the present embodiment.

As shown in the figure, the implantation energy is higher than 20keV when the peak cut-off frequency f _T starts to decrease. This is considered to be due to an increase in boron concentration near the emitter layer. On the other hand, even when the implantation energy is less than 6 keV, the peak cutoff frequency f _T is reduced.

  Here, when boron is implanted under the conditions of an oblique implantation angle of 25 ° and an acceleration energy of 20 keV, boron is implanted to a depth of 70 nm, so that the lateral spread is about 30 nm. Therefore, the effects of the present embodiment can be obtained if the implantation conditions are such that the width extends about 30 nm or less from the end of the emitter electrode 50. On the other hand, when boron is implanted under the conditions of an oblique implantation angle of 25 ° and an acceleration energy of 6 keV, boron is implanted to a depth of 40 nm, so that the lateral spread is about 17 nm. Therefore, the effects of the present embodiment can be obtained if the implantation conditions are such that the width is about 30 nm or less from the end of the emitter electrode 50. In this embodiment, the processing from the emitter end to the outer end of the emitter electrode is designed to be 0.25 μm. Considering that a safe distance in which the obliquely implanted boron does not affect the operation of the base-emitter junction is a distance equivalent to “boron range + 6 × standard deviation”, when the implanted energy is 20 keV, this safe distance is obtained. Is 230 nm. Therefore, in consideration of performance variations, the lateral dimension of the emitter electrode is preferably designed to have a distance of 230 nm or more from the emitter-base junction. The penetration depth of boron in the lateral direction varies depending on the implantation energy and dose of the difference in ion implantation, and the lateral dimensions of the emitter electrode and the emitter layer vary depending on the design. It is preferable to set the dimensions and process conditions of each part so that the inclination angle has a distance of 230 nm or more from the emitter-base junction.

  Further, in the manufacturing method of the present embodiment, it is possible to form a polycrystalline SiGe film serving as an external base at a low growth rate by using the UHV-CVD method. The thickness of the Si / SiGeC layer 30b is smaller than the thickness of the single crystal Si / SiGeC layer 30a in the intrinsic base layer 52. As a result, the distance between the intrinsic base layer 52 and the silicide layer 37b of the external base layer 51 is shortened, and the performance of the bipolar transistor can be improved by the low base resistance.

  Note that the thickness of the polysilicon film constituting the emitter electrode and the lateral dimension of the emitter electrode in this embodiment are the same as those in the first embodiment, and are much larger than those of the conventional bipolar transistor. Therefore, similarly to the first embodiment, it is possible to exhibit effects such as reliably maintaining the contact resistance to the emitter electrode 50 low.

In the above embodiments has described a bipolar transistor having a Si / SiGeC heterojunction, instead of the SiGeC layer, Si _1-x Ge x film containing no C or, 0.1 in trace amounts (composition ratio (3.0%), the basic effect of each embodiment can be exhibited even if a Si _1-y C _y film containing C is provided.

  Further, in each of the above embodiments, the polysilicon film 32 containing phosphorus having the emitter opening is provided on the oxide film 31 having the emitter opening. However, the polysilicon film 32 is not always necessary. However, by providing the polysilicon film 32 containing the same conductivity type impurity as the emitter electrode, there is an advantage that the boron injected into the emitter electrode can be prevented from diffusing (penetrating) downward and inward as much as possible.

  In each of the above embodiments, the emitter electrode made of a polysilicon film is provided. However, the emitter electrode may be made of a polycrystalline SiGe film.

  Further, instead of the polysilicon film 32, a polycrystalline SiGe film or a polycrystalline SiGeC film may be provided.

  INDUSTRIAL APPLICABILITY The bipolar transistor of the present invention can be used as a transistor for amplifying a high-frequency signal or a power transistor mounted on a device for communication such as mobile communication.

FIG. 2 is a sectional view of the bipolar transistor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a process up to the formation of a Si single crystal layer in the manufacturing process of the bipolar transistor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a step of forming a trench in the manufacturing steps of the bipolar transistor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a step of forming an N + type collector lead layer in the manufacturing steps of the bipolar transistor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a step of depositing an oxide film and a polysilicon film for defining an external base region in the manufacturing process of the bipolar transistor according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a step of implanting impurities for a collector layer in the manufacturing steps of the bipolar transistor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a step of forming a Si / SiGeC layer in the manufacturing steps of the bipolar transistor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a step of forming an emitter opening in an oxide film and a polysilicon film in the manufacturing process of the bipolar transistor according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view showing a step of forming an emitter electrode and implanting boron into a Si / SiGeC layer in the manufacturing steps of the bipolar transistor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a step of patterning a Si / SiGeC layer in the manufacturing steps of the bipolar transistor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view showing a step of forming an emitter layer and a side wall in the manufacturing steps of the bipolar transistor according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating a step of forming a silicide layer in the manufacturing steps of the bipolar transistor according to the first embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a step of performing oblique ion implantation in the manufacturing steps of the bipolar transistor according to the second embodiment of the present invention. FIG. 11 is a cross-sectional view illustrating a step of patterning a Si / SiGeC layer in a manufacturing step of the bipolar transistor according to the second embodiment of the present invention. FIG. 7 is a diagram showing the amount of depression on the upper surface of the emitter electrode with respect to the thickness of the polysilicon film for the emitter electrode of the bipolar transistors of the first and second embodiments. 12 is data showing the relationship between the implantation energy when oblique implantation is performed under the conditions of the second embodiment and the peak cutoff frequency of the bipolar transistor.

Explanation of reference numerals

Reference Signs List 1 P-type Si substrate 2 Sub-collector 3 Single-crystal Si layer 4 Shallow trench 5 Deep trench 6 Undoped polysilicon film 7 Silicon oxide film 8 N + -type collector lead-out layer 9 P-type well 10 N-type well 11 Oxide film 28 Oxide film 29 Poly Silicon film 30 (monocrystalline) Si / SiGeC layer 30 (polycrystalline) Si / SiGeC layer 31 Oxide film 32 Polysilicon film 33 Polysilicon film 35 Emitter layer 36 Side wall 37 Co silicide layer 38 Interlayer insulating film 39 W plug Reference Signs List 40 aluminum metal wiring 45 emitter opening 50 emitter electrode 51 external base layer 52 intrinsic base layer

Claims (11)

A first semiconductor layer;
A collector layer formed in an upper surface region of the first semiconductor layer and containing a first conductivity type impurity;
Two separation layers formed of an insulating film and separated from each other with the collector layer interposed therebetween;
A second semiconductor layer grown on the first semiconductor layer and the separation layer and having a different band gap from the first semiconductor layer and containing a second conductivity type impurity;
A third semiconductor layer grown on the second semiconductor layer and having a different band gap from the second semiconductor layer;
An insulating film formed on the third semiconductor layer and having an emitter opening;
An emitter electrode formed of a polycrystalline semiconductor including a first conductivity type impurity, the emitter electrode being formed to fill the emitter opening;
A region of the third semiconductor layer in contact with the emitter electrode is an emitter layer containing a first conductivity type impurity,
A region of the second semiconductor layer sandwiched between the emitter layer and the collector layer is an intrinsic base layer containing a second conductivity type impurity,
A portion of the second semiconductor layer and the third semiconductor layer surrounding the intrinsic base layer is an external base layer containing a second conductivity type impurity,
The external base layer straddles the separation layer, and has a silicide layer on a surface thereof,
A bipolar transistor, wherein the emitter electrode has a film thickness that is diffused so that the concentration of the second base-type impurity for forming the external base, which is implanted therein, is lower at the lower portion. The bipolar transistor according to claim 1,
A bipolar transistor, wherein the thickness of the emitter electrode ranges from 200 nm to 500 nm. The bipolar transistor according to claim 1,
A bipolar transistor, wherein a portion of the upper surface of the emitter electrode located above the emitter opening has no recess having an aspect ratio exceeding 1/5. The bipolar transistor according to any one of claims 1 to 3,
The second conductivity type impurity is implanted into a region of the external base layer from a position below a side end of the emitter electrode to a position 230 nm away from a boundary between the emitter layer and the intrinsic base layer. Bipolar transistor. The bipolar transistor according to any one of claims 1 to 4,
An interlayer insulating film covering the emitter electrode and the external base layer;
A bipolar transistor formed through the interlayer insulating film and having a conductor plug in contact with the isolation layer in the external base layer. The bipolar transistor according to any one of claims 1 to 5,
The first semiconductor layer has a single Si composition,
The bipolar transistor, wherein the second semiconductor layer has a SiGe or SiGeC mixed crystal composition. On the first semiconductor layer of the first conductivity type surrounded by the separation layer, a second semiconductor layer having a band gap different from that of the first semiconductor layer and containing impurities of the second conductivity type is laid over the separation layer. (A) epitaxially growing
(B) epitaxially growing a third semiconductor layer having a band gap different from that of the second semiconductor layer on the second semiconductor layer;
(C) forming an insulating film having an emitter opening on the third semiconductor layer;
(D) forming a polycrystalline layer containing a first conductivity type impurity on the third semiconductor layer and the insulating film;
(E) patterning the polycrystalline layer and the insulating layer to form an emitter electrode;
(F) implanting impurities of the second conductivity type into the second and third semiconductor layers from a direction inclined with respect to a direction perpendicular to the substrate surface, using the emitter electrode and the insulating film as a mask. A method for manufacturing a bipolar transistor, comprising: The method for manufacturing a bipolar transistor according to claim 7,
A step of drive-in diffusion of the first conductivity type impurity from the emitter electrode into the third semiconductor layer to form an emitter layer in a region of the third semiconductor layer located below the emitter opening ( g), further comprising:
In the step (f), the second conductivity type impurity is implanted under the condition that the second conductivity type impurity does not reach the emitter layer side more than 230 nm from the boundary between the emitter layer and the second semiconductor layer. A method for manufacturing a bipolar transistor. The method for manufacturing a bipolar transistor according to claim 7 or 8,
After the step (f), a step (h) of forming an insulator sidewall on the side surface of the emitter electrode and the insulating film;
A method of manufacturing a bipolar transistor, further comprising a step (i) of silicidizing the third semiconductor layer and an upper portion of the emitter electrode using the insulator sidewall as a mask. The method for manufacturing a bipolar transistor according to any one of claims 7 to 8,
In the above step (d), a method for manufacturing a bipolar transistor, wherein a polycrystalline layer having a thickness in a range from 200 nm to 500 nm is formed. The method for manufacturing a bipolar transistor according to any one of claims 7 to 10,
The first semiconductor layer has a single Si composition,
In the step (a), a method of manufacturing a bipolar transistor for growing a second semiconductor layer having a SiGe or SiGeC mixed crystal composition.

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