JP4181450B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, and more particularly to measures for optimizing the concentration distribution of impurities in a heterobipolar transistor or a Bi-CMOS device including the same.
[0002]
[Prior art]
In recent years, a bipolar transistor formed on a silicon substrate includes a heterojunction structure such as Si / SiGe, Si / SiC, etc., so that a higher bipolar region transistor can be realized with better conduction characteristics. (HBT) is being developed at a rapid pace. In this HBT, a SiGe layer is epitaxially grown on a Si substrate and this Si / SiGe heterojunction structure is used. Until then, the transistor cannot be operated unless it is a transistor using a compound semiconductor substrate such as GaAs. In addition, a transistor that operates even in a high frequency region can be realized. Since this HBT is made of a material having a good affinity with a general-purpose silicon process such as a Si substrate and a SiGe layer, it has great advantages of high integration and low cost. In particular, by forming and integrating an HBT and a MOS transistor (MOSFET) on a common Si substrate, a high-performance Bi-CMOS device can be configured, and this Bi-CMOS device is used for communication. It is promising as a possible system LSI.
[0003]
Therefore, as a bipolar transistor in a Bi-CMOS device, Si / Si has been used so far. _1-x Ge _x And Si / Si _1-y C _y HBTs including such heterojunction structures have been proposed and prototyped. Above all, Si / Si _1-x Ge _x The type HBT is capable of continuously adjusting the band gap by utilizing the property that Si and Ge can be almost completely dissolved and the change in the band gap caused by strain. It seems promising. For this purpose, a MOSFET having only a Si layer and Si / Si _1-x Ge _x Many proposals have been made on SiGe-BiCMOS devices in which a type HBT is provided on a common Si substrate.
[0004]
FIG. 12 is a cross-sectional view showing a manufacturing process of a conventional SiGe-BiCMOS device. As shown in the figure, the upper part of the Si substrate 500 having (001) as the main surface includes a retrograde well 501 having a depth of 1 μm containing N-type impurities such as phosphorus introduced by an epitaxial growth method, an ion implantation method, or the like. It has become. The N-type impurity concentration in the region near the surface of the Si substrate 500 is 1 × 10 ¹⁷ atoms ・ cm ^-3 It is adjusted to the degree. Further, as element isolation, a shallow trench 503 in which silicon oxide is embedded, and a deep trench 504 including an undoped polysilicon film 505 and a silicon oxide film 506 surrounding the undoped polysilicon film 505 are provided. The depths of the trenches 503 and 504 are about 0.35 μm and 2 μm, respectively.
[0005]
Further, a collector layer 502 is provided in a region sandwiched by the trench 503 in the Si substrate 500, and a region separated from the collector layer 502 in the Si substrate 500 by the shallow trench 503 is interposed via a retrograde well 501. An N + collector lead layer 507 is provided for contacting the collector layer 502 electrode.
[0006]
On the Si substrate 500, a first deposited oxide film 508 having a collector opening 510 and having a thickness of about 30 nm is provided. An undoped layer (i-Si) having a thickness of about 20 nm is formed on the portion of the Si substrate 500 exposed at the collector opening 510 and the first deposited oxide film 508. _1-x Ge _x Layer) and about 40 nm thick doped layer (P + Si) doped with P-type impurities _1-x Ge _x Si) consisting of _1-x Ge _x A layer 511b is provided, and a Si cap layer 511a having a thickness of about 40 nm is further stacked thereon. This Si cap layer 511a and Si _1-x Ge _x With the layer 511b, Si / Si _1-x Ge _x Layer 511 is configured. Si / Si _1-x Ge _x The layer 511 has a single crystal structure epitaxially grown on the underlying Si substrate 500 in the collector opening 510, but has a polycrystalline structure on the deposited oxide film 508.
[0007]
Si / Si _1-x Ge _x A second deposited oxide film 512 for an etch stopper having a thickness of about 30 nm is provided on the layer 511. The second deposited oxide film 512 includes a base junction opening 514 and a base opening 518. Is formed. Then, a P + polysilicon layer 515 having a thickness of about 150 nm and a third deposited oxide film 517 are provided to fill the base junction opening 514 and extend on the second deposited oxide film 512.
[0008]
Of the P + polysilicon layer 515 and the third deposited oxide film 517, the portion of the second deposited oxide film 512 located above the base opening 518 is opened, and the P + polysilicon layer 515 A fourth deposited oxide film 520 having a thickness of about 30 nm is formed on the side surface, and a sidewall 521 made of polysilicon having a thickness of about 100 nm is further provided on the fourth deposited oxide film 520. . An N + polysilicon layer 529 is provided to fill the base opening 518 and extend on the third deposited oxide film 517, and this N + polysilicon layer 529 functions as an emitter lead electrode. The fourth deposited oxide film 520 electrically insulates the P + polysilicon layer 515 and the N + polysilicon layer 529 and removes impurities from the P + polysilicon layer 515 to the N + polysilicon layer 529. Diffusion is blocked. The upper surface of the P + polysilicon layer 515 and the N + polysilicon layer 529 are insulated from each other by the third deposited oxide film 517.
[0009]
Further, a Ti silicide layer 524 is formed on the surface of the collector lead layer 507, the P + polysilicon layer 515, and the N + polysilicon layer 529, respectively, and the outside of the N + polysilicon layer 529 and the P + polysilicon layer 515. The side surface is covered with a sidewall 523. The entire substrate is covered with an interlayer insulating film 525, penetrating through the interlayer insulating film 525, an N + collector extraction layer 507, a P + polysilicon layer 515 which is a part of the external base, and an N which is an emitter extraction electrode. + Connection holes reaching the Ti silicide layer 524 on the polysilicon layer 529 are respectively formed. A W plug 526 filling each connection hole and a metal wiring 527 connected to each W plug 526 and extending on the interlayer insulating film 525 are provided.
[0010]
Here, the structure of the emitter-base junction shown in the partially enlarged view of FIG. 12 will be described. Si _1-x Ge _x A portion of the layer 511b located below the base opening 518 functions as an internal base 519 (intrinsic base). In addition, a portion of the Si cap layer 511a that is located immediately below the base opening 518 and into which boron is introduced by diffusion from the N + polysilicon layer 529 functions as the emitter 530.
[0011]
And Si / Si _1-x Ge _x A portion of the layer 511 excluding the region below the base opening 518 and the P + polysilicon layer 515 constitute an external base 516. However, in the part shown in the partial enlarged view, Si / Si _1-x Ge _x A portion of the layer 511 excluding the region below the base opening 518 functions as the external base 516.
[0012]
With the structure as described above, an N + type emitter 530 made of Si single crystal and mainly Si _1-x Ge _x An Si / SiGe-based NPN heterobipolar transistor having a P + type internal base 519 made of single crystal and a collector layer 502 made of Si single crystal is formed. However, since the emitter / base / collector is partitioned by the impurity conductivity type rather than by the Si / SiGe crystal boundary, the emitter / base / collector boundary is precisely determined by the impurity profile. Will also change. In particular, when used as a high-frequency signal amplification device, the profile of boron (B), which is a P-type impurity in the internal base 519, is extremely important. _1-x Ge _x The layer 511b is deposited as follows.
[0013]
As shown in FIG. 13, undoped i-Si is formed on the collector layer (Si substrate). _1-x Ge _x After epitaxially growing a layer (x is constant), P + Si doped with boron (B) thereon _1-x Ge _x A layer (x varies) and a Si cap layer are epitaxially grown sequentially. The right side of FIG. 13 shows the distribution of B concentration and Ge content during crystal growth for forming the base layer. That is, P + Si _1-x Ge _x At the top of the layer, the Ge content is almost zero, and there is almost no difference in composition with the Si cap layer. In the subsequent process, high-temperature treatment is added, so that P + Si _1-x Ge _x Boron in the layer diffuses, and the Si cap layer and i-Si _1-x Ge _x A gentle B concentration distribution in which boron is spread also in a part of the layer is exhibited.
[0014]
[Patent Document 1]
JP 5-102170 (abstract)
[0015]
[Problems to be solved by the invention]
However, in the conventional Si / SiGe heterobipolar transistor, Si during the manufacturing process _1-x Ge _x It was difficult to suppress the spread of boron (B) in the layer 511b and finally stably maintain an appropriate B concentration profile. It has been found that the characteristics of the heterobipolar transistor in the high-frequency region deteriorate due to the spread of boron (B). Therefore, the present inventors conducted the following experiment in order to find out the cause of the collapse of the B concentration profile.
[0016]
FIG. 14 is a diagram showing SIMS measurement data on the concentration distribution of phosphorus (P) and boron (B) and the Ge content in the emitter / base region of a conventional Si / SiGe heterobipolar transistor. In the figure, the horizontal axis represents the relative depth with the 0 point defined for convenience, and the vertical axis represents the concentration of phosphorus (P) and boron (B) (atoms · cm ^-3 ) And the secondary ion intensity (count number) corresponding to the Ge content. As shown in the figure, it can be seen that the Ge content shows a steep inclined structure and a good composition is obtained. However, P + Si _1-x Ge _x It can be seen that the concentration distribution of boron (B) in the layer becomes gentle, and boron (B) spreads widely to most of the Si cap layer 511a. Here, types of boron (B) include 10B and 11B having different weights, and boron (B) is converted into Si by in-situ doping during epitaxial growth. _1-x Ge _x When introduced into the layer, Si _1-x Ge _x 10B and 11B are mixed in the layer, but boron (B) is converted into Si by ion implantation. _1-x Ge _x When introduced into the layer, Si _1-x Ge _x It has been found that there is only 11B in the layer. In the SIMS measurement, there is a certain width in the region where atoms such as impurities in the sample are sputtered. Therefore, the correspondence between the range of each region and the impurity concentration is not necessarily included in the SIMS measurement data. However, there is a general tendency between the range of each region and the concentration of impurities.
[0017]
As shown in FIG. 14, the fact that the concentration distribution of boron (B) spreads more than expected has not been completely clarified yet, but the facts revealed by the data shown in FIG. 14 and other experiments. There is a strong possibility that some correlation exists between the phosphorous concentration in the emitter layer and the boron (B) concentration. That is, the higher the concentration of phosphorus (P) in the emitter, the more P + Si _1-x Ge _x There was a tendency for the boron (B) concentration distribution in the layer to spread. And it is considered that point defects are involved in the fact that the diffusion of boron (B) is promoted when the concentration of phosphorus (P) is high. In other words, if point defects exist at a high concentration, it becomes possible not only to diffuse by substitution of B atoms with Si or Ge atoms, but also to move B atoms through point defects. It is considered that the diffusion rate of atoms is increased and the concentration distribution of boron (B) becomes gentle.
[0018]
This is derived from the following phosphorus (P) concentration distribution. In the concentration distribution of phosphorus (P) in the Si cap layer shown in FIG. 14, the region Re1 has a solid solubility limit (about 1 × 10 4) in the Si single crystal. ²⁰ atoms ・ cm ^-3 The above-mentioned phosphorus (P) is contained, and the portion of these phosphorus (P) that cannot be completely dissolved enters the interstitial position or forms vacancies, thereby causing point defects. It seems to give birth. That is, Si _1-x Ge _x If the phosphorus (P) concentration in the layer is high, the number of point defects increases, so that it is considered that the diffusion of boron (B) is promoted and the concentration distribution is widened.
[0019]
On the other hand, in the N + polysilicon layer 529 functioning as a conventional emitter lead electrode, as shown in FIG. ²⁰ ・ Atoms cm ^-3 About a degree of phosphorus (P) is doped, and the concentration is considerably higher than the solid solubility limit in the Si single crystal. This is because impurities in polysilicon have a strong tendency to segregate at the grain boundaries, so that the activity of impurities necessary for lowering the resistance is required unless high concentration of phosphorus (P) is doped as a whole. This is because the conversion rate cannot be obtained.
[0020]
The object of the present invention is to suppress the spread of P-type impurities such as boron (B) in the Si cap layer while maintaining the emitter lead electrode, the low resistance of the emitter, and the impurity concentration necessary for the desired operation of the bipolar transistor. By providing the above, a method for manufacturing a semiconductor device that functions as a bipolar transistor having excellent electrical characteristics such as high-frequency characteristics can be provided by appropriately maintaining the concentration distribution of P-type impurities in the base layer of the heterobipolar transistor. is there.
[0021]
[Means for Solving the Problems]
According to the first method for manufacturing a semiconductor device of the present invention, a P-type second single crystal semiconductor layer functioning as a base layer is formed on an N-type first single crystal semiconductor layer functioning as a collector layer on a substrate. Epitaxially growing (a), step (b) of epitaxially growing a third single crystal semiconductor layer on the second single crystal semiconductor layer, and on the third single crystal semiconductor layer The lower portion includes phosphorus having a concentration equal to or lower than the concentration at which the solid solubility limit of phosphorus of the third single crystal semiconductor layer is diffused into the third single crystal semiconductor layer, and the upper portion has a higher concentration of phosphorus than the lowermost portion. A step (c) of depositing a semiconductor layer containing the semiconductor layer, and a heat treatment for diffusing phosphorus in the semiconductor layer, and doping the upper portion of the third single crystal semiconductor layer with phosphorus at a concentration below the solid solubility limit. Emission of bipolar transistors And a step (d) of forming a.
[0022]
By this method, phosphorus exceeding the solid solubility limit to the third single crystal semiconductor layer is diffused from the lowermost part of the semiconductor layer such as the amorphous silicon layer or the polysilicon layer during the heat treatment in the step (d). Therefore, the occurrence of point defects in the third single crystal semiconductor layer is suppressed, so that a bipolar transistor having a base having a good P-type impurity concentration distribution is formed.
[0023]
In the step (c), the concentration of phosphorus doped in the semiconductor layer may be increased stepwise upward, or continuously increased upward.
[0024]
According to the second method for manufacturing a semiconductor device of the present invention, a P-type second single crystal semiconductor layer functioning as a base layer is formed on an N-type first single crystal semiconductor layer functioning as a collector layer on a substrate. Epitaxially growing (a), step (b) of epitaxially growing a third single crystal semiconductor layer on the second single crystal semiconductor layer, and P at least above the third single crystal semiconductor layer A step (c) of doping a type impurity, a step (d) of forming a semiconductor layer containing phosphorus on the third single crystal semiconductor layer, and a heat treatment for diffusing phosphorus in the semiconductor layer And (e) forming an emitter of a bipolar transistor by doping phosphorus on the upper portion of the third single crystal semiconductor layer with a higher concentration of phosphorus than the P-type impurity doped in the step (c). It is out.
[0025]
By this method, the presence of the P-type impurity doped in the upper part of the third single crystal semiconductor layer in step (c) empirically causes the P-type impurity in the second single crystal semiconductor layer during the subsequent heat treatment. Diffusion is suppressed. Therefore, a bipolar transistor having a base having a good P-type impurity concentration distribution is formed.
[0026]
In the step (c), simultaneously with the step (b), the third single crystal semiconductor layer is epitaxially grown while doping a P-type impurity, or the third single crystal semiconductor layer is formed after the step (b). This is done by implanting ions of P-type impurities.
[0027]
In addition, after the step (b) and before the step (c), a step of forming an insulating layer on the third single crystal semiconductor layer, and a P-type impurity is included on the insulating layer. Forming a semiconductor layer, and performing the step (c) by introducing a P-type impurity from the semiconductor layer through the insulating layer by heat treatment and introducing the P-type impurity into the third single crystal semiconductor layer. Also good.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 1 is a cross-sectional view of a semiconductor device which is a hetero bipolar transistor (HBT) according to a first embodiment of the present invention. However, although only the structure of the HBT is shown in the figure, a CMOS device is often provided on a common substrate. In this case, a MIS transistor of the CMOS device is formed in a region not shown. It shall be.
[0029]
As shown in the figure, the upper part of the Si substrate 100 having the (001) plane as a main surface is a retrograde well 101 having a depth of 1 μm containing N-type impurities such as phosphorus introduced by an epitaxial growth method, an ion implantation method or the like. It has become. The N-type impurity concentration in the region near the surface of the Si substrate 100 is 1 × 10 ¹⁷ atoms ・ cm ^-3 It is adjusted to the degree. Further, as element isolation, a shallow trench 103 in which silicon oxide is embedded, and a deep trench 104 including an undoped polysilicon film 105 and a silicon oxide film 106 surrounding the undoped polysilicon film 105 are provided. The depths of the trenches 103 and 104 are about 0.35 μm and 2 μm, respectively.
[0030]
Further, a collector layer 102 is provided in a region sandwiched by the trench 103 in the Si substrate 100, and a region separated from the collector layer 102 in the Si substrate 100 by the shallow trench 103 is interposed via a retrograde well 101. An N @ + collector extraction layer 107 for contacting the collector layer 102 electrode is provided.
[0031]
On the Si substrate 100, a first deposited oxide film 108 having a collector opening 110 and having a thickness of about 30 nm is provided. In addition, an undoped layer (i-Si) having a thickness of about 30 nm is formed on a portion of the upper surface of the Si substrate 100 exposed to the collector opening 110 and the first deposited oxide film 108. _1-x Ge _x Layer) and about 60 nm thick doped layer (P + Si) doped with P-type impurities _1-x Ge _x Si) consisting of _1-x Ge _x A layer 111b is provided, and a Si cap layer 111a having a thickness of about 30 nm is further stacked thereon. This Si _1-x Ge _x By the layer 111b and the Si cap layer 111a, Si / Si _1-x Ge _x Layer 111 is constructed (see partial enlarged view). Si / Si _1-x Ge _x The layer 111 has a single crystal structure along the crystal structure of the underlying Si substrate 100 on the portion of the Si substrate 100 exposed at the collector opening 110, and on the first deposited oxide film 108. Has a polycrystalline structure. And mainly Si _1-x Ge _x The lower part of the central portion (a region below a base opening 118 described later) of the layer 111b is an internal base 119, and the central portion of the Si cap layer 111a is an emitter layer. Si _1-x Ge _x Most of the layers are 2 × 10 2 by P-type impurities such as boron (B). ¹⁸ atoms ・ cm ^-3 Doped to a degree.
[0032]
Si / Si _1-x Ge _x A second deposited oxide film 112 for an etch stopper having a thickness of about 30 nm is provided on the layer 111 and the first deposited oxide film 108, and the second deposited oxide film 112 is used for base bonding. An opening 114 and a base opening 118 are formed. Further, a P + polysilicon layer 115 having a thickness of about 150 nm and filling the base junction opening 114 and extending on the second deposited oxide film 112, and a third deposited oxide film 117 are provided. Si / Si above _1-x Ge _x An external base 116 is constituted by a portion of the layer 111 excluding the region below the base opening 118 and the P + polysilicon layer 115.
[0033]
Of the P + polysilicon layer 115 and the third deposited oxide film 117, a portion of the second deposited oxide film 112 located above the base opening 118 is opened, and the P + polysilicon layer 115 A fourth deposited oxide film 120 having a thickness of about 30 nm is formed on the side surface, and a sidewall 121 made of polysilicon having a thickness of about 100 nm is provided on the fourth deposited oxide film 120. .
[0034]
Here, as a feature of the present embodiment, an N @-polysilicon layer 129b having a thickness of about 100 nm and filling the base opening 118 and extending on the third deposited oxide film 117, and an N @ + thickness of about 200 nm. An emitter lead electrode 129 made of a polysilicon layer 129a is provided (see a partially enlarged view). Thus, without providing the P polysilicon layer 129a directly on the Si cap layer 111a, by interposing the N @-polysilicon layer 129b between them, the Si cap layer 111a has an excessively high concentration of phosphorus ( P) is configured to suppress doping. In this embodiment, the Si cap layer 111a has a depth of 7 × 10 toward the depth of the substrate by diffusion of phosphorus (P) from the N + polysilicon layer 129a. ²⁰ atoms ・ cm ^-3 To 1 × 10 ²⁰ atoms ・ cm ^-3 Phosphorus (P) is doped with a distribution to the extent.
[0035]
The fourth deposited oxide film 120 electrically insulates the P + polysilicon layer 115 and the emitter lead electrode 129 and prevents diffusion of impurities from the P + polysilicon layer 115 to the emitter lead electrode 129. ing. Further, the third deposited oxide film 117 insulates the upper surface of the P + polysilicon layer 115 from the emitter lead electrode 129. Further, the outer surfaces of the emitter lead-out electrode 129 and the P + polysilicon layer 115 are covered with a sidewall 123.
[0036]
Further, Ti silicide layers 124 are formed on the surfaces of the collector lead layer 107, the P + polysilicon layer 115, and the emitter lead electrode 129, respectively. The structure of the outer surface of the P + polysilicon layer 115 is different from the structure of the conventional HBT shown in FIG. 12, but this is due to the difference in the patterning order between the P + polysilicon layer 115 and the emitter lead electrode 129. Is.
[0037]
Further, the entire substrate is covered with an interlayer insulating film 125, penetrating through the interlayer insulating film 125, on the N + collector extraction layer 107, the P + polysilicon layer 115 which is a part of the external base, and the emitter extraction electrode 129. Connection holes reaching the Ti silicide layer 124 are respectively formed. A W plug 126 filling each connection hole and a metal wiring 127 connected to each W plug 126 and extending on the interlayer insulating film 125 are provided.
[0038]
The thickness of each layer as described above shows a typical value, and an appropriate thickness can be used according to the type and application of the HBT.
[0039]
Here, the structure of the emitter-base junction shown in the partially enlarged view of FIG. 1 will be described. Si _1-x Ge _x A portion of the layer 111b located below the base opening 118 functions as an internal base 119 (intrinsic base). In addition, a portion of the Si cap layer 111 a that is located immediately below the base opening 118 and into which boron is introduced by diffusion from the emitter lead electrode 129 functions as the emitter 130.
[0040]
And Si / Si _1-x Ge _x An external base 116 is constituted by a portion of the layer 111 excluding the region below the base opening 118 and the P + polysilicon layer 115. However, in the part shown in the partial enlarged view, Si / Si _1-x Ge _x A portion of the layer 111 excluding the region below the base opening 118 functions as the external base 116.
[0041]
With the structure as described above, an N + -type emitter 130 made of Si single crystal and mainly Si _1-x Ge _x A Si / SiGe-based NPN heterobipolar transistor having a P + type internal base 119 made of single crystal and a collector layer 102 made of Si single crystal is formed. However, since the emitter-base-collector is partitioned by the impurity conductivity type rather than the Si / SiGe crystal boundary, the emitter-base-collector is precisely determined by the impurity concentration profile. The boundary will also change. In particular, since the concentration profile of boron (B) which is a P-type impurity in the internal base 119 is most important, Si _1-x Ge _x When the layer 111b is deposited, it is as described with reference to FIG.
[0042]
Next, a manufacturing process for realizing the structure shown in FIG. 1 will be described with reference to FIGS. 2 (a) to 5 (b). FIG. 2A to FIG. 5B are cross-sectional views showing manufacturing steps of the Si / SiGe-HBT of the first embodiment. Note that a CMOS device may be formed on a common substrate, or only an HBT may be formed.
[0043]
First, in the step shown in FIG. 2A, an Si single crystal layer is epitaxially grown on the upper part of the Si substrate 100 having the (001) plane as a main surface while doping an N-type impurity, or a high energy after epitaxial growth. By performing ion implantation, an N-type retrograde well 101 having a depth of about 1 μm is formed. However, the retrograde well 101 can be formed by performing ion implantation on a part of the Si substrate 100 without performing epitaxial growth. At this time, since the region near the surface of the Si substrate 100 becomes the collector layer of the HBT, the N-type impurity concentration is set to 1 × 10 6. ¹⁷ atoms ・ cm ^-3 Adjust to the degree.
[0044]
Next, as element isolation, a shallow trench 103 in which silicon oxide is embedded, and a deep trench 104 including an undoped polysilicon film 105 and a silicon oxide film 106 surrounding the undoped polysilicon film 105 are formed. The depths of the trenches 103 and 104 are set to about 0.35 μm and 2 μm, respectively. A region sandwiched between the shallow trenches 103 in the Si substrate 100 is a collector layer 102. Further, an N + collector lead layer 107 for contacting the collector electrode is formed in a region separated from the collector layer 102 in the Si substrate 100 by the shallow trench 103.
[0045]
Next, in the step shown in FIG. 2B, chemical vapor deposition (CVD) using tetraethoxysilane (TEOS) and oxygen is performed at a processing temperature of 680 ° C., and a thickness of about 30 nm is formed on the wafer. After forming the first deposited oxide film 108, a collector opening 110 is formed in the first deposited oxide film 108 by wet etching such as hydrofluoric acid. Then, the portion exposed to the collector opening 110 of the Si substrate 100 is treated with a mixed solution of ammonia water and hydrogen peroxide solution, and a protective oxide film having a thickness of about 1 nm is formed on the portion. It introduce | transduces in the chamber of a UHV-CVD apparatus. After the introduction, the protective oxide film is removed by heat treatment in a hydrogen atmosphere, and then disilane (Si ₂ H ₆ ) And germane (GeH) _Four ), An undoped layer (i−) having a thickness of about 30 nm shown in the partially enlarged view of FIG. 1 is formed on the surface of the Si substrate 100 exposed at the collector opening 110 and the first deposited oxide film 108. Si _1-x Ge _x Layer) is selectively epitaxially grown and then heated to 550 ° C. while disilane (Si ₂ H ₆ ) And germane (GeH) _Four ) Diborane for doping (B ₂ H ₆ ) Gas is introduced into the chamber and i-Si is introduced. _1-x Ge _x P + Si about 60 nm thick on the layer _1-x Ge _x The layer is grown epitaxially. As a result, Si having a total thickness of about 90 nm _1-x Ge _x Layer 111b is formed. And Si _1-x Ge _x After forming the layer 111b, the gas continuously supplied into the chamber is switched to disilane, so that Si _1-x Ge _x P + Si of layer 111b _1-x Ge _x An Si cap layer having a thickness of about 30 nm is epitaxially grown on the layer. This Si _1-x Ge _x By the layer 111b and the Si cap layer 111a, Si / Si _1-x Ge _x Layer 111 is formed. Where P + Si _1-x Ge _x The concentration of boron (B) in the layer is 2 × 10 ¹⁸ atoms ・ cm ^-3 It is. At this time, impurities are not introduced into the Si cap layer 111a. And mainly Si _1-x Ge _x The lower part of the center part of the layer 111b becomes the internal base 119.
[0046]
Next, in the step shown in FIG. 3A, a second deposited oxide film 112 having a thickness of 30 nm serving as an etch stopper is formed on the wafer, and then a resist provided on the second deposited oxide film 112 is formed. Using the mask Pr1, the second deposited oxide film 112 is patterned by dry etching to form the base bonding opening 114. At this time, Si / Si _1-x Ge _x The central portion of the layer 111 is covered with the second deposited oxide film, and the Si / Si opening is formed in the base junction opening 114. _1-x Ge _x A part of the layer 111 and a part of the first deposited oxide film 108 are exposed. Next, in order to suppress the influence of stress in the active region / isolation junction, ion implantation of a P-type impurity such as boron (B) is performed using the resist mask Pr1 used for forming the base junction opening 114. And the concentration near the surface is 3 × 10 ¹⁷ atoms ・ cm ^-3 A junction leak prevention layer 113 having a degree of formation is formed.
[0047]
Next, in the step shown in FIG. 3B, 1 × 10 5 boron is formed on the wafer by CVD. ²⁰ atoms ・ cm ^-3 The P + polysilicon layer 115 having a thickness of about 150 nm doped at the above-described high concentration is deposited, and then a third deposited oxide film 117 having a thickness of about 100 nm is deposited. Next, the third deposited oxide film 117 and the P + polysilicon layer 115 are patterned by dry etching, and the second deposited oxide film 117 and the P + polysilicon layer 115 are centered between the second deposited oxide film 117 and the P + polysilicon layer 115. A base opening 118 reaching the oxide film 112 is formed. The base opening 118 is smaller than the central portion of the second deposited oxide film 112, and the base opening 118 does not straddle the base bonding opening 114. By this process, the P + polysilicon layer 115 and the Si / Si _1-x Ge _x An external base 116 constituted by a portion excluding the central portion of the layer 111 is formed. Here, in the present embodiment, both end portions of the third deposited oxide film 117 and the P + polysilicon layer 115 in the drawing are left without being etched at this time. Thereby, the residue adhering to the etched side wall can be suppressed as much as possible.
[0048]
Next, in the step shown in FIG. 4A, a fourth deposited oxide film 120 having a thickness of about 30 nm and a polysilicon film having a thickness of about 150 nm are deposited on the entire surface of the wafer by CVD. Then, the fourth deposited oxide film 120 and the polysilicon film are etched back by anisotropic dry etching, and the fourth deposited oxide film is formed on the side surfaces of the P + polysilicon layer 115 and the third deposited oxide film 117. Sidewalls 121 made of polysilicon are formed with 120 therebetween. Next, wet etching using hydrofluoric acid or the like is performed, and the exposed portions of the second deposited oxide film 112 and the fourth deposited oxide film 120 are removed. At this time, in the base opening 118, Si / Si _1-x Ge _x The upper Si cap layer of layer 111 is exposed. Further, since the wet etching is isotropic, the second deposited oxide film 112 and the fourth deposited oxide film 120 are also etched in the lateral direction, and the size of the base opening 118 is increased.
[0049]
Next, in the step shown in FIG. 4 (b), an N @-polysilicon layer 129b having a thickness of about 100 nm and an N @ + polysilicon layer 129a having a thickness of about 200 nm are deposited. Thereafter, the emitter lead electrode 129 is formed by patterning the N @-polysilicon layer 129b and the N @ + polysilicon layer 129a by dry etching. At this time, the N @ + polysilicon layer 129a has a thickness of about 7 * 10 due to in-situ doping when the polysilicon film is deposited. ²⁰ atoms ・ cm ^-3 Is doped with phosphorus (P) at a concentration of about 7 × 0 in the N-polysilicon layer 129a. ¹⁹ atoms ・ cm ^-3 The concentration of phosphorus (P) is doped. Thereafter, heat treatment is performed at 925 ° C. for 15 seconds to diffuse phosphorus (P) from the N − polysilicon layer 129b into the Si cap layer 111a, thereby causing the Si cap layer 111a to have a depth of 2 in the substrate depth direction. × 10 ¹⁹ atoms ・ cm ^-3 To 1 × 10 ¹⁷ atoms ・ cm ^-3 Doped with phosphorus (P) with a distribution to the extent. Thereby, the emitter 130 is formed.
[0050]
Next, in the step shown in FIG. 5A, the third deposited oxide film 117, the P + polysilicon layer 115, and the second deposited oxide film 112 are patterned by dry etching to form the shape of the external base 116. decide.
[0051]
Next, in the step shown in FIG. 5B, a deposited oxide film having a thickness of about 120 nm is formed on the wafer, and then dry etching is performed on the side surfaces of the emitter lead-out electrode 129 and the P + polysilicon layer 115. Sidewall 123 is formed. At this time, the exposed portion of the first deposited oxide film 108 is removed by dry etching (overetching), and the surfaces of the emitter lead electrode 129, the P + polysilicon layer 115 and the N + collector lead layer 107 are removed. Expose.
[0052]
Further, in order to obtain the structure shown in FIG. First, a Ti film having a thickness of about 40 nm is deposited on the entire surface of the wafer by sputtering, and then RTA (short-time annealing) at 675 ° C. for 30 seconds is performed, so that the emitter extraction electrode 129 and the P + polysilicon layer 115 are formed. A Ti silicide layer 124 is formed on the exposed surface of the N @ + collector lead layer 107. Thereafter, only the unreacted portion of the Ti film is selectively removed, and then annealing for changing the crystal structure of the Ti silicide layer 124 is performed.
[0053]
Next, an interlayer insulating film 125 is formed on the entire surface of the wafer, and reaches the Ti silicide layer 124 on the emitter leading electrode 129, the P + polysilicon layer 115 and the N + collector leading layer 107 through the interlayer insulating film 125. A connection hole is formed. Then, after a W film is buried in each connection hole to form a W plug 126, an aluminum alloy film is deposited on the entire surface of the wafer, and then patterned to be connected to each W plug 126, and an interlayer insulating film Metal wiring 127 extending on 125 is formed.
[0054]
Through the above process, the HBT having the structure shown in FIG. 1, that is, the collector made of the well layer (retrograde well 101) doped with phosphorus (P) in the Si substrate 100, and boron (B) are doped. P + Si _1-x Ge _x An HBT having a base composed of layers and an emitter composed of a Si cap layer 111a doped with phosphorus (P) is formed.
[0055]
According to the HBT of this embodiment or the manufacturing method thereof, P-polysilicon containing a low concentration of phosphorus (P) between the N + polysilicon layer 129a containing a high concentration of phosphorus (P) and the Si cap layer 111a. Since the layer 129b is interposed, it is possible to suppress the spread of the boron (B) concentration distribution in the internal base layer 119 resulting from the diffusion of high concentration phosphorus (P) into the Si cap layer 111a (emitter 130). it can.
[0056]
FIG. 6 is a diagram schematically showing the concentration distribution of phosphorus (P) and boron (B) in the longitudinal section from the emitter extraction electrode 129 to the Si substrate 100 in the present embodiment. As shown in the figure, in the N + polysilicon layer 129a in the emitter lead-out electrode 129, the concentration of phosphorus (P) is a value sufficient for activation, which is necessary for obtaining the desired characteristics of the HBT. The low resistance of the emitter lead electrode 129 is ensured. On the other hand, the emitter 130 provided above the Si cap layer 111a is doped with phosphorus (P) at a concentration below the solid solubility limit and sufficient to function as an emitter. Then, P + Si serving as the internal base 119 _1-x Ge _x The concentration distribution of boron (B) in the layer depends on the Si cap layer 111a and i-Si. _1-x Ge _x The steepness is maintained without spreading greatly in the layers. The fact that such an impurity concentration distribution is obtained has been confirmed by the following simulation.
[0057]
FIG. 7 shows P + Si _1-x Ge _x FIG. 10 is a diagram showing a result of a simulation performed to examine how the enhanced diffusion of boron (B) in a layer changes depending on the concentration of phosphorus (P) in a polysilicon layer constituting the emitter lead-out electrode 129. In the figure, the horizontal axis represents the relative depth, and the vertical axis represents the concentration of phosphorus (P) or boron (B) (atoms · cm ^-3 ). And i-Si which is a spacer _1-x Ge _x The thickness of the layer is 40 nm and the base P + Si _1-x Ge _x The thickness of the layer is 40 nm, the thickness of the Si cap layer is 40 nm, and the heat treatment for diffusion is performed under the conditions of 925 ° C. and 15 sec. However, since it is difficult to simulate the impurity concentration distribution due to diffusion in the polysilicon layer, it is assumed that the impurity concentration is constant in the polysilicon layer. Further, on the right side of the figure, for each data of boron (B) and phosphorus (P), the concentration of phosphorus (atoms · cm in the polysilicon layer (DPS)). ^-3 )It is shown. For example, data B (DPS 7E20) is 7 × 10 7 in the P− polysilicon layer 129b. ²⁰ atoms ・ cm ^-3 P + Si when doped with phosphorus (P) _1-x Ge _x The data P (DPS 7E20) shows how the doped boron in the layer (internal base) diffuses, and the data P (DPS 7E20) is 7 × 10 7 in the N− polysilicon layer 129b. ²⁰ atoms ・ cm ^-3 It shows how the phosphorus (P) diffused into the Si cap layer 111a when doped with a concentration of phosphorus (P).
[0058]
As shown in FIG. 7, the polysilicon layer in contact with the Si cap layer has a thickness of about 7 × 10 ×. ²⁰ atoms ・ cm ^-3 In the case of doping phosphorus (P) at a concentration of _1-x Ge _x Boron diffusion from the layer is accelerated, and a boron (B) peak appears in the Si cap layer. Further, the polysilicon layer in contact with the Si cap layer has a thickness of about 2 × 10 ²⁰ atoms ・ cm ^-3 In the case of doping with phosphorus (P) at a concentration of 1, no boron (B) peak appears in the Si cap layer, but the Si cap layer and i-Si _1-x Ge _x Boron (B) spreads in the layer. In particular, when the thickness of the Si cap layer in the HBT is 10 nm, the uppermost portion of the Si cap layer is about 3 × 10 ¹⁷ atoms ・ cm ^-3 It can be seen that boron (B) having a concentration of 1 is present, which is not preferable. On the other hand, the polysilicon layer in contact with the Si cap layer is at most about 7 × 0. ¹⁹ atoms ・ cm ^-3 In the case of doping phosphorus (P) at a concentration of _1-x Ge _x Layer to Si cap layer and i-Si _1-x Ge _x The diffusion of boron (B) into the layer is suppressed, and the steepness of the boron (B) concentration distribution is maintained. In the Si cap layer, about 2 × 10 ¹⁹ atoms ・ cm ^-3 Since the concentration of phosphorus (P) is doped, all regions are doped with an impurity at a concentration necessary for the operation of the HBT.
[0059]
That is, as shown in the above manufacturing process, about 7 × 0 ¹⁹ atoms ・ cm ^-3 An N @-polysilicon layer 129b containing a low concentration of phosphorous (P) is deposited immediately above the Si cap layer 111a, and about 7 * 10 on it. ²⁰ atoms ・ cm ^-3 It can be seen that the impurity concentration distribution as shown in FIG. 6 can be realized by depositing the N @ + polysilicon layer 129a containing a high concentration of phosphorus (P).
[0060]
The concentration of phosphorus (P) in the N @-polysilicon layer 129b preferably includes phosphorus at a concentration equal to or lower than the concentration for diffusing phosphorus at a solid solubility limit with respect to the Si cap layer 111a. This is because if the Si cap layer 111a is doped with phosphorus (P) exceeding the solid solubility limit, point defects are generated, which is considered to promote the diffusion of boron. Here, the solid solubility limit of phosphorus in the Si single crystal is about 1 × 10. ²⁰ atoms ・ cm ^-3 The solid solubility limit of phosphorus in various semiconductors is a unique value determined according to the material of the semiconductor. On the other hand, if the concentration of phosphorus (P) in the N-polysilicon layer 129b is too low, a driving force for diffusion of phosphorus (P) cannot be obtained. The concentration must be higher than the concentration at which phosphorus (P) can diffuse. The difference in phosphorus concentration between the upper end of the Si cap layer 111a and the N @-polysilicon layer 129b at this time can be obtained by simulation as shown in FIG. 7, and can also be confirmed by measuring the sample with SIMS. Can do. For example, in the case of the sample from which data of phosphorus (P) (DPS 7E19) shown in FIG. 7 is obtained, the concentration of phosphorus (P) at the upper end of the Si cap layer 111a is about 2 × 10. ¹⁹ atoms ・ cm ^-3 Thus, the concentration of phosphorus (P) in the N @-polysilicon layer 129b is about 6.times.10. ¹⁹ atoms ・ cm ^-3 It is. Considering other samples as well, as far as the simulation is performed, the N-polysilicon layer 129b contains phosphorus having a concentration about three times that of phosphorus (P) to be doped into the Si cap layer 111a. It will be necessary. However, the difference in concentration between the two is that the deposition conditions of polysilicon and amorphous silicon (generally amorphous silicon is often used during deposition) and the boundary between the underlying Si cap layer 111a and the N @-polysilicon layer 129b. It depends on the state of the layer, for example, the presence or absence of a natural oxide film, the thickness, and the like. That is, the appropriate range of phosphorus (P) concentration in the N-polysilicon layer 129b can be experimentally determined using the sample for the manufacturing process.
[0061]
The range of the thickness of the N @-polysilicon layer 129b is determined by the relationship with the concentration of phosphorus (P) in the N @ + polysilicon layer 129a. The diffusion of phosphorus (P) from the N @ + polysilicon layer 129a results in Si. It suffices if the cap layer 111a is not doped with phosphorus (P) exceeding the solid solubility limit and low resistance required for the entire emitter extraction electrode 129 can be obtained.
[0062]
It should be noted that not only two layers, N + polysilicon layer 129a and N− polysilicon layer 129b, but also a third polysilicon layer containing an intermediate concentration of phosphorus is formed between the two layers. A silicon layer may be formed, or phosphorus may be doped so that the concentration of phosphorus in polysilicon continuously changes from a concentration below the solid solubility limit to a concentration exceeding the solid solubility limit.
[0063]
(Second Embodiment)
FIG. 8 is a cross-sectional view of a semiconductor device that is a hetero-bipolar transistor (HBT) according to a second embodiment of the present invention. However, although only the structure of the HBT is shown in the figure, a CMOS device is often provided on a common substrate. In this case, a MIS transistor of the CMOS device is formed in a region not shown. It shall be.
[0064]
As shown in the figure, the structure of the HBT in this embodiment is almost the same as the structure of the HBT in the first embodiment, but the structure of the emitter extraction electrode 129 and the concentration of impurities in the Si cap layer 111a. Distribution is different. Hereinafter, description of the same structure as that of the first embodiment is omitted, and only differences from the first embodiment will be described.
[0065]
In this embodiment, the emitter lead-out electrode 129 is composed only of an N + polysilicon layer, and the emitter layer 130, which is the upper part of the Si cap layer 111a, has a phosphorus concentration of not less than the solid solubility limit in the Si single crystal. (P) is doped. However, the upper portion of the Si cap layer 111a is also doped with a relatively high concentration of boron (B). As will be described later, due to the presence of this boron (B), P + Si serving as an internal base is formed. _1-x Ge _x The steepness of the boron (B) concentration distribution in the layer is maintained.
[0066]
9A and 9B are views showing a part of the manufacturing process of the semiconductor device in the present embodiment. Also in this embodiment, the same steps as those in FIGS. 2A to 3A in the first embodiment are performed. However, in the present embodiment, the thickness of the second deposited oxide film 112 is about 10 nm.
[0067]
Then, in the step shown in FIG. 9A, after depositing an undoped polysilicon film on the wafer by CVD, a dose amount of 3 × 10 is applied to the polysilicon film. ¹⁵ atoms ・ cm ^-2 Boron (B) ions are implanted under the conditions described above to form a heavily doped P + polysilicon layer 115 having a thickness of about 150 nm. Subsequently, after depositing a third deposited oxide film 117 having a thickness of about 100 nm, boron (B) in the P + polysilicon layer 115 is diffused under conditions of 950 ° C. and 15 sec. By this heat treatment, boron (B) in the P + polysilicon layer 115 passes through the second deposited oxide film 112 and is doped into the Si cap layer 111a.
[0068]
Next, in the step shown in FIG. 9B, the third deposited oxide film 117 and the P + polysilicon layer 115 are patterned by dry etching, so that the third deposited oxide film 117 and the P + polysilicon layer are patterned. A base opening 118 reaching the second deposited oxide film 112 is formed in the central portion with 115. The base opening 118 is smaller than the central portion of the second deposited oxide film 112, and the base opening 118 does not straddle the base bonding opening 114. By this process, the P + polysilicon layer 115 and the Si / Si _1-x Ge _x An external base 116 constituted by a portion excluding the central portion of the layer 111 is formed.
[0069]
Subsequent steps are not shown, but substantially the same processes as those shown in FIGS. 4A to 5B are performed. However, when forming the emitter lead-out electrode 129, only the N + polysilicon layer is deposited and then patterned.
[0070]
FIG. 10 shows Si / Si in this embodiment. _1-x Ge _x It is a figure which shows typically concentration distribution of phosphorus (P) and boron (B) in the longitudinal section of layer 111. As shown in the figure, boron (B) diffused from the P + polysilicon layer 115 through the second deposited oxide film 112 is doped at a high concentration on the Si cap layer 111a. That is, at the interface with the emitter lead electrode 129 in the Si cap layer 111a, the concentration of boron (B) is extremely low, but then the boron concentration rapidly increases downward, and the emitter lead electrode 129 in the Si cap layer 111a. A peak of boron (B) concentration appears at a position several nm away from the interface with. Then, P + Si serving as the internal base 119 _1-x Ge _x The concentration distribution of boron (B) in the layer depends on the Si cap layer 111a and i-Si. _1-x Ge _x The steepness is maintained without spreading greatly in the layers. Even if the upper portion of the Si cap layer 111a is doped with a high concentration of boron (B), a higher concentration of phosphorus (P) is further doped, so that the emitter 130 is a high concentration N-type and an NPN bipolar. The function as a transistor is not impaired. The fact that such an impurity concentration distribution is obtained has been confirmed by the following simulation.
[0071]
FIG. 11 is a diagram showing SIMS measurement data when boron (B) is diffused from the P + polysilicon layer into the Si cap layer with an oxide film interposed therebetween, as in the semiconductor device manufacturing process of the present embodiment. is there. In the figure, the horizontal axis represents the relative depth, and the vertical axis represents the concentration of phosphorus (P) or boron (B) (atoms · cm ^-3 ). The boron concentration in the P + polysilicon layer is 1 × 10 ²⁰ atoms ・ cm ^-3 And the thickness of the oxide film interposed between the P + polysilicon layer and the Si cap layer at the time of boron diffusion is 10 nm. However, the data in FIG. 11 is for data obtained by patterning the P + polysilicon layer and then forming an extraction electrode. Further, heat treatment for drive-in diffusion is performed under the conditions of 950 ° C. and 15 sec. It should be noted that the phosphorus (p) data was not shown in the figure because an accurate value was not obtained, but is assumed to have a distribution indicated by a broken line in the figure.
[0072]
As shown in FIG. 11, it can be seen that phosphorus (P) and boron (B) concentration distributions substantially corresponding to FIG. 10 are obtained. That is, P + Si _1-x Ge _x Si cap layer and i-Si on both sides from the layer _1-x Ge _x The diffusion of boron (B) into the layer is suppressed, and the steepness of the boron (B) concentration distribution is maintained. That is, boron diffusion to the Si cap layer 111a and the collector layer 102 side is also suppressed. As shown in FIG. 11, in the manufacturing process as in this embodiment, only the heavy 11B is doped into the P + polysilicon layer 115 by ion implantation, so that boron (B) appearing in FIG. The peak is P + Si _1-x Ge _x It can be seen that this is not due to the diffusion of boron (B) from the layer but from the diffusion of the P + polysilicon layer 115. Note that because of the characteristics measured by SIMS, the sputtered region has a width, so P + Si _1-x Ge _x Although the boron concentration distribution in the layer appears to be widening, it can be assumed that there is actually a steep distribution.
[0073]
That is, as shown in the above-described manufacturing process, boron (B) is diffused from the P + polysilicon layer 115 to the Si cap layer 111a with the second deposited oxide film 112 interposed therebetween, thereby forming P + Si as an internal base. _1-x Ge _x It has been empirically confirmed that the concentration distribution of boron (B) in the layer can be maintained sharply.
[0074]
Thus, P + Si _1-x Ge _x The reason why the concentration distribution of boron (B) in the layer can be maintained sharply has not been confirmed yet. The inventor's guess is that phosphorus (P) having a concentration higher than the intrinsic limit from the emitter lead-out electrode 129 made of an N + polysilicon layer to the Si single crystal diffuses into the Si cap layer 111a, so that the Si cap layer 111a. Even if a point defect is generated inside, the point defect is occupied by boron (B) diffused from the P + polysilicon layer 115 to the Si cap layer 111a. _1-x Ge _x It can be considered that diffusion of the layer, that is, the internal base boron (B) is suppressed.
[0075]
Therefore, at least the upper part of the Si cap layer 111a has P + Si. _1-x Ge _x It is preferable that boron is doped at a higher concentration than the layer (inner base). Further, the entire Si cap layer 111a may be doped with boron.
[0076]
In the Si cap layer 111a, it is preferable that the region doped with boron (B) is included in the region doped with phosphorus at a higher concentration than boron in this region. This is because high pressure resistance can be ensured.
[0077]
(Other embodiments)
In this embodiment, boron (B) is doped into the P + polysilicon layer 115 by ion implantation, but boron (B) may be doped into the P + polysilicon layer 115 by an in-situ doping method. .
[0078]
Further, the method of doping boron (B) at a high concentration on the upper portion of the Si cap layer 111a is not limited to the method described in this embodiment. Although illustration of the manufacturing process is omitted, for example, when the Si cap layer 111a is epitaxially grown (the process shown in FIG. 2B in the first embodiment), boron (B) is highly formed on the Si cap layer 111a. The concentration may be in-situ doped. According to this method, there is an advantage that the impurity concentration distribution in the Si cap layer 111a and the like can be controlled more stably than the manufacturing method in the second embodiment.
[0079]
In each of the above embodiments, Si is used as the base layer. _1-x Ge _x The base layer is made of Si (0 ≦ x <1). _1-x Ge _x Si instead of layer _1-xy Ge _x C _y Layer (0 ≦ x, y <1) or Si _1-y C _y You may comprise by a layer (0 <= y <1). Further, at least one of the emitter and collector is made Si. _1-x Ge _x Layer, Si _1-xy Ge _x C _y Layer or Si _1-y C _y You may comprise by a layer.
[0080]
【The invention's effect】
According to the semiconductor device manufacturing method of the present invention, when the first to third single crystal semiconductor layers serving as the collector, base, and emitter are provided, the solid solubility limit is formed on the upper portion of the third single crystal layer semiconductor layer serving as the emitter. Since the following concentration of phosphorus is included or the upper portion of the third single crystal semiconductor layer includes a P-type impurity and phosphorus having a concentration higher than that of the P-type impurity, the second single crystal serving as a base is included. The diffusion of P-type impurities in the crystalline semiconductor layer can be suppressed, and thus the concentration distribution of P-type impurities in the base can be properly maintained.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of an HBT that is a semiconductor device according to a first embodiment of the present invention.
FIGS. 2A and 2B show Si / Si at the collector opening in the manufacturing process of the semiconductor device of the first embodiment. _1-x Ge _x It is sectional drawing which shows the process of forming a layer.
FIGS. 3A and 3B are cross-sectional views showing a process of forming a base opening in a P + polysilicon layer in the manufacturing process of the semiconductor device of the first embodiment. FIGS.
4A and 4B are cross-sectional views showing a process of forming an N + polysilicon layer in the base opening in the manufacturing process of the semiconductor device of the first embodiment.
FIGS. 5A and 5B are cross-sectional views showing a process of patterning an end portion of P + polysilicon in the manufacturing process of the semiconductor device according to the first embodiment; FIGS.
FIG. 6 is a diagram schematically showing phosphorus (P) and boron (B) concentration distributions in a longitudinal section from the emitter lead electrode to the Si substrate in the first embodiment.
FIG. 7: P + Si _1-x Ge _x It is a figure which shows the simulation result regarding the density | concentration dependence of phosphorus (P) in the polysilicon layer of the boron (B) accelerated diffusion in the layer.
FIG. 8 is a cross-sectional view showing a configuration of an HBT which is a semiconductor device according to a second embodiment of the present invention.
FIGS. 9A and 9B are views showing a process for manufacturing a semiconductor device according to the second embodiment after depositing a P + polysilicon layer and then diffusing boron (B), and then opening a base opening. It is sectional drawing which shows the process of forming.
FIG. 10 is a diagram schematically showing the concentration distribution of phosphorus (P) and boron (B) in the longitudinal section of the Si / Si1-x Gex layer in the second embodiment.
FIG. 11 is a diagram showing SIMS measurement data when boron (B) is diffused from a P + polysilicon layer into an Si cap layer with an oxide film interposed therebetween.
FIG. 12 is a cross-sectional view showing a configuration of a conventional bipolar transistor.
FIG. 13 shows a conventional Si cap layer, P + Si. _1-x Ge _x Layers and i-Si _1-x Ge _x It is a figure which shows the cross-sectional structure of a layer, its B density | concentration, and distribution of Ge content rate.
FIG. 14 is a diagram showing data measured by SIMS for phosphorus (P) and boron (B) concentration distributions and Ge secondary ion intensity distributions in the emitter / base region of a conventional Si / SiGe heterobipolar transistor; It is.
[Explanation of symbols]
100 (001) Si substrate
101 Retro Grade Well
102 Collector layer
103 shallow trench
104 deep trench
105 Undoped polysilicon film
106 Silicon oxide film
107 N + collector extraction layer
108 First deposited oxide film
110 Collector opening
111 Si / Si _1-x Ge _x layer
111a Si cap layer
111b Si _1-x Ge _x layer
112 Second deposited oxide film
113 Junction leak prevention layer
114 Base joint opening
115 P + polysilicon layer
116 External base
117 Third deposited oxide film
118 Base opening
119 Internal base
120 Fourth deposited oxide film
121 sidewall
123 sidewall
124 Ti silicide layer
125 Interlayer insulation layer
126 W plug
127 metal wiring
129 Emitter extraction electrode
129a N + polysilicon layer
129b N-polysilicon layer
130 Emitter

Claims (10)

A step (a) of epitaxially growing a P-type second single crystal semiconductor layer functioning as a base layer on an N-type first single crystal semiconductor layer functioning as a collector layer on the substrate;
A step (b) of epitaxially growing a third single crystal semiconductor layer on the second single crystal semiconductor layer;
On the third single crystal semiconductor layer, the upper Symbol third phosphorus concentration of the solid solubility limit of the single crystal semiconductor layer a third concentration following concentrations of diffusing into the single crystal semiconductor layer phosphorus including N ^- and polysilicon, the N ^- and depositing an emitter electrode by laminating than polysilicon N + polysilicon containing high concentration of phosphorous in the order (c),
The N ^- and was heat-treated for diffusing the phosphorus in the polysilicon, the step of forming the third emitter by doping phosphorus concentrations below solubility limit at the top of the single crystal semiconductor layer (d) and A method of manufacturing a semiconductor device including: In the manufacturing method of the semiconductor device according to claim 1,
In the step (c), the semiconductor device manufacturing method wherein the concentration of phosphorus doped in the semiconductor layer is increased stepwise upward. In the manufacturing method of the semiconductor device according to claim 1,
In the step (c), a method for manufacturing a semiconductor device , wherein the concentration of phosphorus doped in the semiconductor layer is continuously increased upward. In the manufacturing method of the semiconductor device according to claim 1,
The first single crystal semiconductor layer is a Si layer;
The second single crystal semiconductor layer is a SiGe layer,
The method for manufacturing a semiconductor device, wherein the third single crystal semiconductor layer is a Si layer. In the manufacturing method of the semiconductor device according to claim 1,
The first single crystal semiconductor layer is a Si layer;
The second single crystal semiconductor layer is a SiGeC layer;
The method for manufacturing a semiconductor device, wherein the third single crystal semiconductor layer is a Si layer. In the manufacturing method of the semiconductor device according to claim 1,
In the semiconductor device, the N ⁻ polysilicon has a recess, the N ⁺ polysilicon has a projection, and the emitter extraction electrode is deposited so that the recess and the projection fit together. Production method. A step (a) of epitaxially growing a P-type second single crystal semiconductor layer functioning as a base layer on an N-type first single crystal semiconductor layer functioning as a collector layer on the substrate;
A step (b) of epitaxially growing a third single crystal semiconductor layer on the second single crystal semiconductor layer;
A step (c) of doping a P-type impurity into at least an upper portion of the third single crystal semiconductor layer;
Forming a semiconductor layer containing phosphorus on the third single crystal semiconductor layer; and
A heat treatment for diffusing phosphorus in the semiconductor layer is performed, and the emitter is doped by doping higher concentration of phosphorus than the P-type impurity doped in the step (c) above the third single crystal semiconductor layer. And (e) forming a semiconductor device. The method of manufacturing a semiconductor device according to claim 7.
The method of manufacturing a semiconductor device, wherein the step (c) is performed by epitaxially growing the third single crystal semiconductor layer while doping a P-type impurity simultaneously with the step (b). The method of manufacturing a semiconductor device according to claim 7.
The method of manufacturing a semiconductor device, wherein the step (c) is performed by implanting ions of P-type impurities into the third single crystal semiconductor layer after the step (b). The method of manufacturing a semiconductor device according to claim 7.
Forming an insulating layer on the third single crystal semiconductor layer after the step (b) and before the step (c);
Forming a semiconductor layer containing a P-type impurity on the insulating layer,
The method of manufacturing a semiconductor device, wherein the step (c) is performed by introducing a P-type impurity into the third single crystal semiconductor layer through the insulating layer through the semiconductor layer by heat treatment.

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