KR20060062487A - Bipolar transistor and method of fabricating the same - Google Patents

Abstract

A bipolar transistor and a method of manufacturing the same are provided. The bipolar transistor has a collector layer on a semiconductor substrate. An isolation layer defining a base active region is disposed in the collector layer. A trench is disposed in the collector layer of the base active region. A single crystal base layer conformally covers the base active region with the trench. An emitter electrode fills the trench covered by the single crystal base layer. An emitter layer is interposed between the emitter electrode and the single crystal base layer.

Bipolar Transistors, Collector Current, Junction, Trench

Description

Bipolar transistor and method of manufacturing the same {bipolar transistor and method of fabricating the same}

1 to 7 are cross-sectional views illustrating a method of manufacturing a bipolar transistor according to an embodiment of the present invention.

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a bipolar transistor having a high current characteristics and a method for manufacturing the same.

In integrated circuit fabrication, CMOS (Complimentary Metal Oxide Semi conductor) devices are used, but bipolar transistors with faster switching speeds than CMOS devices improve the characteristics of bipolar-CMOS (BiCMOS) designs. It is widely used to make. In general, in order to improve the collector current in a bipolar transistor, it is necessary to increase the junction area of the emitter layer and the base layer or to make the width of the base layer as small as possible. An emitter electrode is formed of a polysilicon film doped with a high concentration of impurities on the base layer to control the width of the base layer, and the emitter layer is diffused from the emitter electrode into the base layer to form an emitter layer. Process has been performed. When the emitter layer is formed using diffusion, there is no channeling of the impurities, and a heat treatment process after ion implantation may be omitted. As a result, the emitter layer formed by the diffusion of the impurities can be formed to have a reduced width than the emitter layer formed by using the ion implantation process, it is also possible to reduce the width of the base layer.

Meanwhile, the emitter resistance may be a function of the junction area between the emitter layer and the base layer. Therefore, in order to reduce the emitter resistance to obtain high current characteristics, it is necessary to increase the junction area between the emitter layer and the base layer as described above. However, in bipolar transistors, increasing the junction area can adversely affect the high integration of semiconductor devices.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a bipolar transistor capable of obtaining a high current and a method of manufacturing the same.

Another object of the present invention is to provide a bipolar transistor capable of increasing the junction area between the emitter layer and the base layer without increasing the dimension of the bipolar transistor, and a method of manufacturing the same.

One aspect of the present invention provides a bipolar transistor having an emitter layer of a trench structure. The bipolar transistor has a collector layer on a semiconductor substrate. An isolation layer defining a base active region is disposed in the collector layer. A trench is disposed in the collector layer of the base active region. A single crystal base layer conformally covers the base active region with the trench. An emitter electrode fills the trench covered by the single crystal base layer. An emitter layer is interposed between the emitter electrode and the single crystal base layer.

In an embodiment, an embedded collector layer may be formed on the semiconductor substrate so as to contact the collector layer. Base electrodes may contact the single crystal base layer on both sides of the trench. An interlayer insulating layer may cover an entire surface of the collector layer on which the emitter electrode and the base electrodes are disposed. Base contact plugs and emitter contact plugs may be connected to the base electrodes and the emitter contact plugs through the interlayer insulating layer.

Another aspect of the invention provides a method of making a bipolar transistor having an emitter layer of a trench structure. The method includes forming a collector layer on a semiconductor substrate. An isolation layer defining a base active region is formed in the collector layer. A trench is formed in the collector layer of the base active region. A single crystal base layer conformally covering the base active region having the trench is formed. An emitter electrode is formed to fill the trench covered by the single crystal base layer.

In one embodiment, the single crystal base layer may be formed of a single crystal silicon germanium layer using an epitaxial growth method.

In another embodiment, forming the emitter electrode may include forming an emitter electrode film filling the trench on the entire surface of the semiconductor substrate having the single crystal base layer, and etching back the emitter electrode film.

Alternatively, forming the emitter electrode may include forming an emitter electrode film filling the trench on the entire surface of the semiconductor substrate having the single crystal base layer, and patterning the emitter electrode film.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed subject matter is thorough and complete, and that the spirit of the present invention to those skilled in the art will fully convey. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

1 to 7 are cross-sectional views illustrating a method of manufacturing a bipolar transistor according to an embodiment of the present invention.

First, a bipolar transistor according to an embodiment of the present invention will be described with reference to FIG. 7.

Referring to FIG. 7, a buried collector layer 102 is disposed on the semiconductor substrate 100. The semiconductor substrate 100 may be a first conductivity type, for example, a P-type single crystal silicon substrate. The buried collector layer 102 may be a second conductivity type, for example, a high concentration N-type doping layer. The buried collector layer 102 may be located in an upper region of the semiconductor substrate 100. The collector layer 104 is disposed on the buried collector layer 102. The collector layer 104 may be a single crystal silicon layer of a second conductivity type. The collector layer 104 has the same conductivity type as the buried collector layer 102 but has a lower impurity concentration than the collector layer 104. An isolation layer defining a base active region B and a sinker region S is disposed in the collector layer 102. In the collector layer 102 of the sinker region S, a collector sinker 108 of a second conductivity type is disposed. The collector sinker 108 may be substantially the same as the buried collector layer 102, may have a higher impurity concentration than the collector layer 104, and may penetrate the collector layer 104 to form the buried collector layer 102. ).

A trench 116 is disposed in the collector layer 104 of the base active region B. A single crystal base layer 118S of the first conductivity type conformally covers the base active region B having the trench 116. The single crystal base layer 118S may be a single crystal silicon germanium layer. In the device isolation layer 116, first polysilicon layer patterns 118P ′ extending from the single crystal base layer 118S onto the device isolation layer 106 may be disposed. In this case, the first polysilicon layer patterns 118P ′ may have a first conductivity type. In addition, a protective insulating layer 110 may be interposed between the first polysilicon layer patterns 118P ′ and the device isolation layer 106. The protective insulating layer 110 may be a silicon oxide layer. When the protective insulating layer 110 is interposed, the first polysilicon layer patterns 118P ′ may be disposed on the protective insulating layer 110.

A second conductivity type emitter electrode 124 fills the trench 116 covered by the single crystal base layer 118S. The emitter electrode 124 may be a polysilicon electrode doped with a high concentration of second conductivity type impurities. An emitter layer 127 of a second conductivity type is interposed between the emitter electrode 124 and the single crystal base layer 118S. The emitter layer 127 may be a second conductivity type impurity diffusion layer made of impurities diffused from the emitter electrode 124. As described above, according to the present invention, the single crystal base layer 118S and the emitter layer 127 are disposed to have a three-dimensional structure along the sidewalls and the bottom surface of the trench 127. Accordingly, the single crystal base layer 118S and the emitter layer 127 may have an effectively increased junction area without increasing the total area of the bipolar transistor, thereby obtaining a high collector current.

The single crystal base layer 118S of the portion disposed on the main surface of the base active region B is disposed above the base active region B on both sides of the trench 116 so as to be spaced apart from the emitter electrode 124. The second polysilicon layer patterns 128 may be connected to the second polysilicon layer patterns 128. The second polysilicon layer patterns 128 may have a second conductivity type. As shown in FIG. 7, the second polysilicon layer patterns 128 may contact the single crystal base layer 118S and may extend over the first polysilicon layer patterns 118P ′. In this case, the second polysilicon film patterns 128 and the first polysilicon film patterns 118P ′ constitute a base electrode. Alternatively, the second polysilicon layer patterns 128 may be omitted. In this case, the first polysilicon layer patterns 118P ′ may be provided as a base electrode.                     

The second polysilicon layer patterns 128 and the emitter electrode 124 are insulated from each other by a dummy insulating layer pattern disposed therebetween. The dummy insulating layer pattern includes a first insulating layer pattern 120 ′ and a second insulating layer pattern 122 ′ sequentially stacked on both sides of the emitter electrode 124. In this case, as shown in FIG. 7, the upper surface of the first insulating layer pattern 120 ′ and the upper surface of the emitter electrode 124 may be substantially positioned at the same level. In addition, the second insulating layer pattern 122 ′ may be disposed on the first insulating layer pattern 120 ′ and extend a predetermined portion onto the emitter electrode 124. The dummy insulating layer pattern may further include a third insulating layer pattern 126 ′ covering the second insulating layer pattern 122 ′ and the emitter electrode 124. The third insulating layer pattern 126 ′ may be penetrated by the emitter electrode 130e to be described later. The first insulating layer pattern 120 ′ and the third insulating layer pattern 126 ′ may be a silicon oxide layer pattern, and the second insulating layer pattern 122 ′ may be a silicon nitride layer pattern.

An interlayer insulating layer 129 is disposed to cover the entire surface of the semiconductor substrate 100 having the second polysilicon layer patterns 128 and the third insulating layer pattern 126 ′. The interlayer insulating layer 129 may be a silicon oxide layer. The emitter contact plug 130e, the base contact plugs 130b, and the collector contact plug 130c are disposed in the interlayer insulating layer 129. The emitter contact plug 130e, the base contact plugs 130b, and the collector contact plug 130c may be tungsten, copper, or aluminum. The emitter contact plug 130e sequentially passes through the interlayer insulating layer 129 and the third insulating layer pattern 126 ′ and is connected to the emitter electrode 124. The base contact plugs 130b and the collector contact plug 130c may pass through the interlayer insulating layer 129 and be connected to the second polysilicon layer patterns 128 and the collector sinker 108, respectively. . As described above, when the second polysilicon layer patterns 128 are omitted, the base contact plugs 130b may be connected to the first polysilicon layer patterns 118P ′. The collector contact plug 130c is electrically connected to the buried collector layer 102 through the collector sinker 108.

Hereinafter, a method of manufacturing a bipolar transistor according to an embodiment of the present invention will be described with reference to FIGS. 1 to 7.

Referring to FIG. 1, a buried collector layer 102 is formed by implanting a second conductive type, for example, a high concentration of N-type impurities into a first conductive type, such as a P-type semiconductor substrate 100. Subsequently, a collector layer 104 is formed on the investment collector layer 102. The collector layer 104 may be formed by epitaxially growing a single crystal silicon layer on the buried collector layer 102. The collector layer 104 is doped with impurities of the second conductivity type. In this case, the impurities of the second conductivity type may be doped in-situ during the epitaxial growth of the collector layer 104. In addition, the collector layer 104 may be doped to have a lower impurity concentration than the investment collector layer 102.

Next, an isolation layer 106 is formed in the collector layer 104 to define the base active region B and the sinker region S. Referring to FIG. The device isolation layer 106 may be formed by a shallow trench isolation process. After forming a mask layer (not shown) covering the base active region B, a second conductivity type is formed in the collector layer 104 by using the mask layer and the element isolation film 106 as ion implantation masks. Inject impurities. As a result, a collector sinker 108 is formed in the sinker region S to be connected to the buried collector layer 102. Next, a protective insulating layer 110 may be formed on the collector layer 104 having the device isolation layer 106 and the collector sinker 108. In this case, the protective insulating layer 110 may be formed to expose the base active region B using a silicon oxide film. The protective insulating layer 110 may serve to protect a region where the CMOS transistor is to be formed when the bipolar CMOS device is formed.

Referring to FIG. 2, a sacrificial oxide film and a mask insulating film covering the entire surface of the resultant device on which the device isolation film 106 and the collector sinker 108 are formed are formed. The sacrificial oxide layer may be formed of a silicon oxide layer, and the mask insulating layer may be formed of a silicon nitride layer. Subsequently, the mask insulating layer is patterned to form a mask insulating layer pattern 114 that exposes the sacrificial oxide layer on a region where the trench is to be formed, that is, a predetermined region of the base active region B. The sacrificial oxide layer and the collector layer 104 are anisotropically etched in sequence using the mask insulating layer pattern 114 as an etching mask. As a result, a trench 116 is formed in the collector layer 104 of the base active region B. In addition, the sacrificial oxide layer is patterned into a sacrificial oxide layer pattern 112. Thereafter, during the anisotropic etching, a process of forming a thermal oxide film on the sidewalls and the bottom of the trench 116 to heal the etch damage applied to the collector layer 104 forming the sidewalls and the bottom of the trench 116 is optional. (Optionally) may be performed.                     

Referring to FIG. 3, the mask insulating layer pattern 114 and the sacrificial oxide layer pattern 112 are removed. When the mask insulating layer pattern 114 is a silicon nitride layer, the mask insulating layer pattern 114 may be removed by wet etching using a solution containing phosphoric acid (H ₃ PO ₄ ) as an etching solution. When the sacrificial oxide layer pattern 112 is a silicon oxide layer, the sacrificial oxide layer pattern 112 may be removed by wet etching using a solution containing hydrofluoric acid (HF) as an etchant. Meanwhile, when the thermal oxide layer is formed, the thermal oxide layer may be removed together during wet etching of the sacrificial oxide layer pattern 112. After the mask insulating layer pattern 114 and the sacrificial oxide layer pattern 112 are removed, a single crystal base layer 118S of a first conductivity type is grown on the collector layer 104 on which the trench 114 is formed. The single crystal base layer 118S is conformally grown along the sidewalls and bottom of the trench 114 and the surface of the base active region B. The single crystal base layer 118S may be formed of a single crystal silicon germanium layer by a low temperature epitaxial process. Impurities of the first conductivity type may be added in-situ during the formation of the single crystal silicon germanium layer by the low temperature epitaxy process. Since the silicon germanium has a smaller energy band gap than silicon, when the heterojunction bipolar transistor (HBT) is used as a base layer, the current gain and operation speed are significantly improved compared to that of the silicon as the base layer. You can.

Meanwhile, while the single crystal base layer 118S is grown, the first polysilicon film 118P may be grown on the device isolation layer 106. As described above, when the protective insulating layer 110 is formed, the first polysilicon layer 118P may be grown on the protective insulating layer 110.

Referring to FIG. 4, a first insulating film 120 and a second insulating film 122 are sequentially formed on the semiconductor substrate 100 having the single crystal base layer 118S. The first insulating layer 120 may be formed of a silicon oxide layer, and the second insulating layer 122 may be formed of a silicon nitride layer. Specifically, a silicon oxide film and a silicon nitride film are sequentially formed on the semiconductor substrate 100 having the single crystal base layer 118S. Thereafter, the silicon nitride layer is patterned to form a second insulating layer 122 exposing an upper region of the trench 116. The second insulating layer 122 may be formed by patterning the silicon nitride layer using a photolithography and an etching process. Thereafter, the silicon oxide film of the portion exposed by the second insulating film 122 is wet-etched and removed using the second insulating film 122 as an etching mask. As a result, the first insulating film 120 remains below the second insulating film 122. The first insulating layer 120 may be removed through wet etching using hydrofluoric acid.

Next, a second conductivity type emitter electrode film filling the trench is formed on the resultant material on which the first insulating film 120 and the second insulating film 122 are formed. The emitter electrode film may be formed of a polysilicon film. The polysilicon film may be formed using chemical vapor deposition, and may be doped in-situ at a high concentration using impurities of a second conductivity type. Thereafter, the emitter electrode film is etched back to form the emitter electrode 124 remaining in the trench. Alternatively, when the emitter electrode film is formed to partially fill the trench 116, the emitter electrode 124 may be formed by patterning the emitter electrode film through a photo and etching process.

Subsequently, the resultant in which the emitter electrode 124 is formed is heat-treated to diffuse impurities in the emitter electrode 124 into the single crystal base layer 118S to form an emitter layer 127 of a second conductivity type. The heat treatment may be, for example, a rapid thermal annealing (RTA) process performed at a temperature of 800 ° C to 1000 ° C. As described above, the trench 116 is formed in the base active region B, and the single crystal base layer 118S and the emitter electrode 124 fill the trench 116. After sequentially forming, the emitter layer 127 is formed through a heat treatment process. As a result, the single crystal base layer 118S and the emitter layer 127 form a junction along the bottom and sidewalls of the trench 116, thereby obtaining a large junction area therebetween.

After the emitter layer 127 is formed, a third insulating layer 126 is formed to cover the resultant of the emitter layer 127. The third insulating layer 126 may be formed of a silicon oxide layer.

Referring to FIG. 5, the third insulating layer 126, the second insulating layer 122, and the first insulating layer 120 are sequentially patterned to form the single crystal base on the base active region B on both sides of the trench 116. A dummy insulating film pattern is formed to expose the layer 118S and cover the sidewalls and the top surface of the emitter electrode 124. The dummy insulating layer pattern includes a first insulating layer pattern 120 ′ and a second insulating layer pattern 122 ′ sequentially stacked on both sides of the emitter electrode 124. In this case, as shown in FIG. 5, an upper surface of the first insulating layer pattern 120 ′ and an upper surface of the emitter electrode 124 may be substantially positioned at the same level. In addition, the second insulating layer pattern 122 ′ may be disposed on the first insulating layer pattern 120 ′ and extend a predetermined portion onto the emitter electrode 124. The dummy insulating layer pattern may further include a third insulating layer pattern 126 ′ covering the second insulating layer pattern 122 ′ and the emitter electrode 124.

Referring to FIG. 6, a second polysilicon film (not shown) of a second conductivity type is formed on the resultant product on which the dummy insulating film pattern is formed. The second polysilicon film may be formed using chemical vapor deposition, and may be doped in-situ using impurities of a second conductivity type. Thereafter, the second polysilicon layer and the first polysilicon layer 118P are patterned, and are insulated from the emitter electrode 124 by the dummy insulating layer pattern, and exposed to both sides of the trench 116. The second polysilicon layer patterns 128 and the first polysilicon layer patterns 118P ′ are formed to contact the single crystal base layer 118S. The second polysilicon layer patterns 128 and the first polysilicon layer patterns 118P ′ may extend a predetermined portion onto the device isolation layer 106, and form a base electrode of the bipolar transistor. Meanwhile, the process of forming the second polysilicon film may be omitted. In this case, only the first polysilicon film 118P is patterned into the first polysilicon film pattern 118P ′ in the patterning process, and the second polysilicon film patterns 128 are omitted.                     

Referring to FIG. 7, an interlayer insulating layer 129 is formed to cover the entire surface of a resultant product in which the first polysilicon layer patterns 118P ′ and the second polysilicon layer patterns 128 are formed. The interlayer insulating film 129 may be formed of a silicon oxide film. Thereafter, emitter contact plugs 130e, base contact plugs 130b, and collector contact plugs 130c are formed in the interlayer insulating layer 129. The emitter contact plug 130e, the base contact plugs 130b, and the collector contact plug 130c may be formed by a known damascene process. The emitter contact plug 130e, the base contact plugs 130b, and the collector contact plug 130c may be formed of tungsten, copper, or aluminum. The emitter contact plug 130e sequentially passes through the interlayer insulating layer 129 and the third insulating layer pattern 126 ′ and is connected to the emitter electrode 124. The base contact plugs 130b and the collector contact plugs 130c pass through the interlayer insulating layer 129 and are respectively connected to the second polysilicon layer patterns 128 and the collector sinker 108. When the protective insulating layer 110 is formed, the collector contact plug 130c may further penetrate the protective insulating layer 110.

Meanwhile, when the second polysilicon layer patterns 128 are omitted as described above, the base contact plugs 130b may be connected to the first polysilicon layer patterns 118P ′. In this case, the first polysilicon film patterns 118P 'are provided as base electrodes.

As described above, the bipolar transistor according to the present invention includes a base layer and an emitter layer formed along sidewalls and bottom surfaces of trenches formed in the base active region. As a result, the junction area between the base layer and the emitter layer can be sufficiently secured without increasing the total area of the bipolar transistor, thereby obtaining a high collector current.

Claims (7)

A collector layer on the semiconductor substrate; An isolation layer disposed in the collector layer to define a base active region; A trench disposed in the collector layer of the base active region; A single crystal base layer conformally covering the base active region having the trench; An emitter electrode filling the trench covered by the single crystal base layer; and And a emitter layer interposed between the emitter electrode and the single crystal base layer. The method of claim 1, And said single crystal base layer is a single crystal silicon germanium layer. The method of claim 1, An investment collector layer formed on the semiconductor substrate to be in contact with the collector layer; Base electrodes in contact with the single crystal base layer on both sides of the trench; An interlayer insulating film covering an entire surface of the collector layer on which the emitter electrode and the base electrodes are disposed; Base contact plugs connected to the base electrodes through the interlayer insulating film; and And a emitter contact plug penetrating the interlayer insulating layer and connected to the emitter electrode. Forming a collector layer on the semiconductor substrate, Forming an isolation layer defining a base active region in the collector layer, Forming a trench in the collector layer of the base active region, Forming a single crystal base layer conformally covering the base active region having the trench, Forming an emitter electrode filling the trench covered by the single crystal base layer. The method of claim 4, wherein And the single crystal base layer is formed of a single crystal silicon germanium layer using an epitaxial growth method. The method of claim 4, wherein Forming the emitter electrode, An emitter electrode film filling the trench is formed on the entire surface of the semiconductor substrate having the single crystal base layer, And etching back said emitter electrode film. The method of claim 4, wherein Forming the emitter electrode, An emitter electrode film filling the trench is formed on the entire surface of the semiconductor substrate having the single crystal base layer, And patterning the emitter electrode film.

Images