KR100212157B1 - Method for fabricating bipolar transistor - Google Patents

Abstract

A bipolar transistor and a method of manufacturing the same are disclosed. It is formed on a silicon substrate, a device isolation film defining a device isolation region and defining a device isolation region, a first insulating film formed on the device isolation film except the base region, and formed on the first insulating film and electrically connected to the base electrode. A base conductive layer, a second insulating film formed on the base conductive layer, an oxide film formed on the surface of the silicon substrate in the base area except the emitter area, the second insulating film, the first conductive layer and the first insulating film sidewalls in an L-shape A third insulating film filling the first and second holes formed between the formed conductive spacer, the insulating spacer formed on the conductive spacer, the insulating spacer and the second insulating film, and between the insulating spacer and the silicon substrate. 3 the emitter conductive layer formed on the insulating film and the insulator spacer, the emitter conductive layer, the base conductive layer And a fourth insulating film formed on the silicon substrate on which the collector is to be formed, and an emitter electrode, a base electrode, and a collector electrode formed through the fourth insulating film. Therefore, the size of the side surface can be reduced, and the size and concentration of the base impurity region can be easily adjusted. In addition, it is possible to easily secure a narrower emitter width and prevent damage to the silicon substrate.

Description

Bipolar Transistor Manufacturing Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor manufacturing method, and more particularly, to a bipolar transistor having a reduced side size of an element and an easy control of the size of a base impurity region.

Recent advances in double polysilicon self-aligned bipolar transistors using polysilicon self-aligned methods have been made due to vertical and lateral integration and reduced base resistance. This technique may increase the cut off frequency (f _T ) or the maximum frequency (fmax).

In general, in the bipolar transistor, in order to simultaneously obtain a high cutoff frequency and a maximum frequency, it is necessary not only to reduce the base resistance but also to optimize the impurity diffusion from the base polysilicon layer to the base region. When the impurity diffusion from the base polysilicon layer is large, the base-collector junction capacitance Cjc is increased, the cutoff frequency f _T is lowered. On the contrary, when the impurity diffusion is small, the base resistance R _B is very high. Will increase.

In view of the above, a method for reducing the junction capacitance and base resistance between the base and the collector and increasing the cutoff frequency has recently been described in the paper-Very-High f _T and fmax Silicon Bipolar Transistors using Ultra-High-Performance super self. -aligned process Technolodgy for Low Energy and Ultra-High-Speed LSI's (1995-735, IEDM, NTT LSI Lab.).

With reference to Figures 1 to 4 will be described a bipolar transistor manufacturing method disclosed in the paper.

Referring to FIG. 1, a high concentration N-type buried layer 12 is formed on a P-type silicon substrate 10, an epitaxial layer 14 is grown thereon, and then a field oxide film 16 for device isolation. ).

Referring to FIG. 2, an oxide film 18 is grown on the resultant on which the field oxide film 16 is formed, polysilicon is deposited thereon, and an impurity to be used as a base electrode is doped by implanting P-type impurities. The first polysilicon layer 20 is formed. The nitride layer 22 is deposited on the first polysilicon layer 20 and then patterned to expose the epitaxial layer 14 on which the emitter region is to be formed.

Referring to FIG. 3, the patterned oxide layer 18 is laterally etched to form an undercut c under the first polysilicon layer, and the second polysilicon layer 24 is free of impurities doped on the resultant. ) To bury the undercut (c). The first polysilicon layer 20 is electrically connected to the epitaxial layer 14 through the second polysilicon layer 24 filling the undercut c.

Referring to FIG. 4, after removing the second polysilicon layer 24 except for embedding the undercut c and performing P-type impurity ion implantation to form an intrinsic base region, a first P-type impurity ion implantation is performed. An insulator spacer 26 is formed on the sidewalls of the polysilicon layer 20. Next, the oxide film on the epitaxial layer 14 to be the emitter region is removed, polysilicon is deposited, and an N-type impurity is implanted to form a third polysilicon layer 30 doped with a high concentration of impurities. . A tungsten silicide layer 32 is formed on the third polysilicon layer 30 and then patterned using a predetermined mask pattern. Subsequently, an insulating film 34 is deposited on the resultant, an emitter, a base, and a collector contact hole are formed through a photolithography process, a metal layer is formed thereon, and then patterned to be connected to the first polysilicon layer 20. A base electrode 38 connected with the emitter electrode 36 and the tungsten silicide layer 32 and a collector electrode (not shown) connected with the silicon substrate are formed.

According to the conventional method described above, an undercut (c) is formed under the first polysilicon layer for the base electrode, and the silicon substrate and the base electrode are brought into contact with each other by embedding it with polysilicon that is not doped with impurities. Therefore, since the base electrode 36 can be formed on the device isolation region without being formed on the base impurity region, the lateral scale can be reduced.

However, according to the above method, it is difficult to control the size and concentration of the base impurity region because it is difficult to control the etching amount during side etching of the oxide film for forming the undercut. In addition, since the silicon substrate is exposed in the process of removing the polysilicon layer deposited on the portion except the undercut, the substrate to be the base region is damaged.

Accordingly, it is an object of the present invention to provide a bipolar transistor in which the size of the base impurity region is easily controlled and the substrate is prevented from being damaged while reducing the side size of the device.

Another object of the present invention is to provide a manufacturing method suitable for manufacturing the bipolar transistor.

Bipolar transistor according to the present invention for achieving the above object is a semiconductor substrate; An isolation layer formed on the semiconductor substrate to define an isolation region; A first insulating film formed on the device isolation film excluding the base region; A base conductive layer formed on the first insulating film and electrically connected to the base electrode; A second insulating film formed on the base conductive layer; An oxide film formed on a surface of the silicon substrate in the base region except for the emitter region; A conductive spacer formed in an L shape on the second insulating layer, the first conductive layer, and the sidewalls of the first insulating layer to connect the base conductive layer and the semiconductor substrate; An insulator spacer formed on the L-shaped conductor spacer; A third insulating film filling the first and second holes formed between the insulator spacer and the second insulating film and between the insulator spacer and the semiconductor substrate by the transient etching and the side etching of the conductive spacer; An emitter conductive layer formed on the third insulating film and the insulator spacer and electrically connected to the emitter region; A fourth insulating film formed on the semiconductor substrate on which the emitter conductive layer, the base conductive layer and the collector are to be formed; And an emitter electrode, a base electrode, and a collector electrode electrically connected to the semiconductor substrate through which the emitter conductive layer, the base conductive layer, and the collector are to be formed.

According to another aspect of the present invention, there is provided a bipolar transistor manufacturing method including: a first step of forming a buried layer and an epitaxial layer of a second conductivity type on a semiconductor substrate of a first conductivity type; Forming a device isolation layer defining an active region on the epitaxial layer; A third step of sequentially forming a first insulating film, a first conductive layer to be used as a base electrode, and a second insulating film on the resultant device isolation layer; A fourth step of patterning the second insulating film, the first conductive layer, and the first insulating film in order to form a base window partially exposing the epitaxial layer; A fifth step of forming a first spacer on an inner wall of the base window; A sixth step of growing an oxide film on a surface of the epitaxial layer except for a first spacer; A seventh step of removing the first spacer; An eighth step of sequentially depositing a conductive material and an insulator on the resultant to form a second conductive layer and an insulating layer, and then anisotropically etching the insulator to form second spacers on sidewalls of the second conductive layer; After forming the L-shaped conductive spacer by isotropically etching the second conductive layer, the first hole and the upper and side surfaces of the conductive spacer are formed by over-etching and side etching. A ninth step of forming a second hole; A tenth step of forming a third insulating film filling the first hole and the second hole; An eleventh step of forming a base impurity region by performing heat treatment on the resultant having the third insulating film formed thereon and diffusing the doped impurities in the heavily doped first conductive layer through the second conductive layer to the epitaxial layer ; An anisotropic etching of the third insulating film and an oxide film below the semiconductor film to expose a negative semiconductor substrate on which an emitter is to be formed; A thirteenth step of forming a third conductive layer to be used as an emitter electrode by removing an oxide film and depositing a conductive material on a resultant product in which an emitter region is exposed, and then patterning the conductive material; A fourteenth step of forming a fourth insulating film for insulating the emitter, the base and the collector by depositing and patterning an insulator on the resultant on which the third conductive layer is formed; And a fifteenth step of forming a base electrode, an emitter electrode, and a collector electrode by depositing and patterning a metal on the resultant product on which the fourth insulating film is formed.

The first conductive layer may be formed of polysilicon doped with impurities of a first conductivity type, and the second conductive layer may be formed of polysilicon that is not doped with impurities. It is preferable to form a polysilicon doped with a biconductive impurity or a polyside layer in which a polysilicon layer and a metal silicide layer are laminated.

In addition, after the sixth step, the base region may be intrinsically implanted by ion implanting impurities of the first conductivity type into the entire surface of the product on which the oxide film is formed.

Therefore, the size of the side surface can be reduced, and the size and concentration of the base impurity region can be easily adjusted. In addition, a narrower emitter width can be easily ensured, and damage to the semiconductor substrate can be prevented.

1 to 4 are cross-sectional views illustrating a bipolar transistor manufacturing method according to the prior art.

5 to 10 are cross-sectional views illustrating a bipolar transistor and a method of manufacturing the same according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

5 to 10 are cross-sectional views illustrating a bipolar transistor and a method of manufacturing the same according to an embodiment of the present invention.

5 shows forming the first insulating film 58 on the silicon substrate.

A buried layer 52 of a second conductivity type, for example, N type, is formed on the first conductive type, for example, P type silicon substrate, and then an N type epitaxial layer 54 is grown thereon. Subsequently, a device isolation film 56 defining an active region is formed using a conventional device isolation process, and the first insulating film 58, for example, an oxide film is grown to a thickness of about 200 kPa to about 1000 kPa on the entire surface of the resultant product.

6 shows the step of forming the base window W _E.

After depositing polysilicon which is not doped with impurities on the resultant on which the first insulating layer 58 is formed, the base first polysilicon layer 60 in which impurities are doped with high concentration is implanted by implanting P-type impurities in high concentration. The second insulating layer 62 is formed by depositing an insulator such as an undoped Silicate Glass on the first polysilicon layer 60. Next, the second insulating film 62, the base first polysilicon layer 60, and the first insulating film 58 are sequentially patterned using a conventional photolithography process to partially expose the epitaxial layer 54. The base window W _E is formed.

7 shows an impurity ion implantation step for making the base region intrinsic.

On the resultant base window W _E formed thereon, an insulator such as nitride is deposited to a thickness of about 500 kPa to 2000 kPa, and then anisotropically etched to define an emitter region on the sidewall of the first polysilicon layer 60. The first spacer 64 is formed, and an oxide film 66 of about 100 kV to about 500 kPa is grown on the epitaxial layer 54 surface. Subsequently, P-type impurities such as BF ₂ are implanted with ion implantation energy of 10 to 30 keV and dose of 1.0E13 to 2.0E14 ions / cm 2 to make the base region intrinsic.

8 shows the steps of forming the first hole h ₁ and the second hole h ₂ .

After removal of the first spacer 64 by wet etching, polysilicon having no impurities doped on the resultant was deposited to a thickness of about 500 kPa to about 2000 kPa to form a second polysilicon layer, and impurities were coated thereon. After the undoped oxide (USG) is deposited to a thickness of about 1000 kV to 3000 kPa, the oxide USG is etched by, for example, a reactive ion etching (RIE) method to form a second spacer 68. Next, an isotropic etching of the second polysilicon layer forms an L-shaped conductive spacer, which is formed between the base first polysilicon layer 60 and the second spacer 68 through over-etching. The first hole h ₁ having a depth of about 500 μs to 1000 μm is formed in the second hole, and the second hole h ₂ is formed under the second spacer 68.

FIG. 9 illustrates a step of forming a third insulating layer 72 filling the first hole h ₁ and the second hole h ₂ .

First holes (h ₁₎ and a second hole (h ₂₎ of the first hole by etching back, and then deposited in a thickness of insulating material, for example, approximately an oxide 500Å ~ 1500Å on the formed output (h ₁₎ and a second hole A third insulating film 72 is formed to fill the (h ₂ ). Here, the third insulating layer 72 serves to electrically insulate the second polysilicon layer 70 and the emitter polysilicon layer formed thereafter.

10 shows forming the base electrode 82, the emitter electrode 84, and the collector electrode (not shown).

P-type impurities in the first polysilicon layer 6 doped at a high concentration by performing heat treatment at 800 to 1000 ° C. on the resultant on which the third insulating layer 72 is formed are formed through the second polysilicon layer 70. The base impurity region 74 is formed by diffusing into the epitaxial layer 54. Subsequently, the oxide film 66 of the portion where the emitter is to be formed is removed by anisotropic etching, polysilylcone is deposited on the resultant, and then doped with N-type impurities to form an emitter third polysilicon layer ( 76), a tungsten silicide layer 78 is formed thereon, and then patterned to form a polysilicon emitter electrode. At this time, the emitter impurity region 75 is formed through heat treatment. Here, the tungsten silicide layer 78 is formed to reduce the resistance of the emitter electrode, and may not be formed. Next, an insulating material is deposited on the resulting product on which the emitter polysilicon layer 76 is formed and then patterned to form a fourth insulating film 80. In this case, when the fourth insulating layer 80 is formed, the second insulating layer 62 is also patterned together to form an epitaxial layer (not shown) of the base first polysilicon layer 60, the tungsten silicide layer 78, and the collector region. Partially). Subsequently, a bipolar transistor is completed by depositing and patterning a metal on the resultant to form a base electrode 82, an emitter electrode 84, and a collector electrode (not shown), respectively.

As described above, according to the present invention, since the base electrode 82 can be formed on the device isolation region without being formed on the base impurity region 74, the side size can be reduced. In addition, when the size and the concentration of the base impurity region are determined according to the etching amount of the first insulating layer 58 under the base polysilicon layer 62, a high concentration doped to the base first polysilicon layer 60 is different. Since the impurity is diffused into the silicon substrate through the second polysilicon layer 70 formed on the sidewall, the base impurity region 74 is formed, so that the size and concentration of the base impurity region 74 can be easily adjusted. In addition, by adjusting the size of the second polysilicon layer 70, it is possible to easily secure a narrower emitter width, and to fill the undercut formed under the first polysilicon layer 60 as in the prior art Since there is no process, damage to the silicon substrate generated in the process can be prevented.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

Claims (6)

Silicon substrate; An isolation layer formed on the silicon substrate to define an isolation region; A first insulating layer formed on the device isolation layer excluding the base region; A base conductive layer formed on the first insulating film and electrically connected to the base electrode; A second insulating film formed on the base conductive layer; An oxide film formed on a surface of the silicon substrate in the base region except for the emitter region; A conductive spacer formed in an L shape on the sidewalls of the second insulating film, the first conductive layer, and the first insulating film to connect the base conductive layer and the silicon substrate; An insulator spacer formed on the L-shaped conductor spacer; A third insulating film filling the first and second holes formed between the insulator spacer and the second insulating film and between the insulator spacer and the silicon substrate by the transient etching of the conductive spacer; An emitter conductive layer formed on the third insulating film, the insulator, and the spacer and electrically connected to the emitter region; A fourth insulating film formed on the silicon substrate on which the emitter conductive layer, the base conductive layer and the collector are to be formed; And an emitter electrode, a base electrode, and a collector electrode electrically connected to the silicon substrate on which the emitter conductive layer, the base conductive layer, and the collector are to be formed, penetrating through the fourth insulating film. The method of claim 1, wherein the base conductive layer is formed of polysilicon doped with impurities, the emitter conductive layer is formed of polysilicon doped with impurities, or a polyside layer in which a polysilicon layer and a metal silicide layer are stacked. Bipolar transistor, characterized in that formed. A first step of forming a buried layer and an epitaxial layer of a second conductive type on the first conductive silicon substrate; Forming a device isolation layer defining an active region on the epitaxial layer; A third step of sequentially forming a first insulating layer, a first conductive layer to be used as a base electrode, and a second insulating layer on the resultant molar formed device isolation layer; A fourth step of forming a base window for partially exposing the epitaxial layer by sequentially patterning the second insulating layer, the first conductive layer, and the first insulating layer; A fifth step of forming a first spacer on an inner wall of the base window; A sixth step of growing an oxide film on a surface of the epitaxial layer except for a first spacer; A seventh step of removing the first spacer; An eighth step of depositing a conductive material and an insulator on the resultant to form a second conductive layer and an insulating layer, and then anisotropically etching the insulator to form a second spacer on sidewalls of the second conductive layer; Isotropically etching the second conductive layer to form an L-shaped conductive spacer, and forming a first hole and a second hole on the top and side surfaces of the conductive spacer by transient etching; A tenth step of forming a third insulating film filling the first hole and the second hole; An eleventh step of forming a base impurity region by performing heat treatment on the resultant having the third insulating film formed thereon and diffusing the doped impurities in the heavily doped first conductive layer into the epitaxial layer through the second conductive layer ; A twelfth step of exposing the emitter region by anisotropic etching using the oxide film of the portion where the emitter is to be formed as the mask; A first step of forming a third conductive layer to be used as an emitter electrode by removing an oxide film and depositing a conductive material on a resultant product in which an emitter region is exposed, and then patterning the conductive material; A fourteenth step of forming a fourth insulating film for depositing and patterning an insulator on the resultant material on which the third conductive layer is formed to insulate the emitter, the base, and the collector; And a fifteenth step of forming a base electrode, an emitter electrode, and a collector electrode by depositing and patterning a metal on the resultant material on which the fourth insulating film is formed. The bipolar transistor of claim 3, wherein the first conductive layer is formed of polysilicon doped with impurities of a first conductivity type, and the second conductive layer is formed of polysilicon that is not doped with impurities. Way. The bipolar transistor according to claim 3, wherein the third conductive layer is formed of polysilicon doped with impurities of the second conductivity type, or a polyside layer in which a polysilicon layer and a metal silicide layer are stacked. Manufacturing method. 4. The method of claim 3, further comprising, after the sixth step, making the base region intrinsic by ion implanting impurities of the first conductivity type over the entire surface of the resultant in which the oxide film is formed.

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