KR20060056971A - Method of manufacturing a semiconductor device with a bipolar transistor and device with a bipolar transistor - Google Patents

Abstract

The invention relates to the manufacturing of a bipolar transistor device (10) in which the emitter is formed using a polycrystalline silicon region (14) which is prevent in a window in an insulating layer (13) and which extends laterally over said insulating layer (13). The silicon region (14) as well as another silicon region (12) bordering the stack of insulating region (13) and silicon region (14) are silicided by means of a metal layer (16) deposited over the structure. The sideface of the stack is provided with means to avoid bridging of the silicides (17) to be formed. According to the invention the means to prevent bridging of the silicides to be formed comprises that the side face of the stack is structured in such a way that the distance between the upper surface of the silicon region (14) and the upper surface the other silicon region (12) along the surface of the side face of the stack is made longer than the total thickness of the insulating layer (13) and the semiconductor layer (14). Through the increased path by either a positive or negative slope of the side face of the stack, the bridging of silicides is avoided. Preferred embodiments relate to how the side face of the stack is structured.

Description

A method of manufacturing a semiconductor device having a bipolar transistor and a device having a bipolar transistor TECHNICAL FIELD

The present invention relates to a method of manufacturing a semiconductor device comprising a silicon semiconductor body having a bipolar transistor having a base, an emitter and a collector, wherein the emitter is formed in a first region of the semiconductor body and is electrically insulated. A layer is formed on the semiconductor body, wherein a window is formed in the first region of the semiconductor body, and a silicon semiconductor layer is formed on the insulating layer, which fills the window in the insulating layer and extends laterally on the insulating layer along the window. After the deposition of the semiconductor layer, the semiconductor layer and the insulating layer are removed from the second region of the semiconductor body, wherein the second region is formed by a stack of stacks including the remaining portion of the insulating layer and the remaining portion of the semiconductor layer. The covering is in contact with the first region, and then the metal layer is on top of the remaining portion of the semiconductor layer and the silicon semiconductor body. Deposited on two regions, silicon oxide is formed between the metal layer and the second region of the silicon semiconductor body and between the metal layer and the remaining portion of the silicon semiconductor layer, and to prevent the formation of bridging silicon oxide on the side of the stack Means for providing are provided. In this way, discrete and integrated bipolar transistors can be made with even more electrical characteristics such as high speed and low consumption.

Such a method is disclosed in US patent application US 2002/0102787, published August 1, 2002. Said document discloses that a SiGe (silicon germanium) heterojunction bipolar transistor is made with an emitter formed on a SiGe substrate, wherein the sidewalls of the emitter are protected by a conformal passivation layer. A description of the method is disclosed. A conformal protective layer is formed on the exposed sidewalls of the emitter prior to silicidating the structure. The presence of a protective layer in the structure prevents the occurrence of shorts of silicon compounds by eliminating bridging between adjacent silicon compound regions; Thus an improved calculation of SiGe bipolar is obtained.

A disadvantage of the known method is that it complicates the manufacturing method of the bipolar transistor, since this method requires several additional processing steps. This method also increases the cost.

Therefore, it is an object of the present invention to provide a method on which, on the one hand, bridging between siliconicide regions is avoided, and on the other hand, the method can make a bipolar transistor simple and inexpensively. will be.

In order to achieve this, according to the invention, the method as described at the outset is characterized in that the means for preventing the bridging of silicon compounds from forming along the upper surface of the remaining portion of the semiconductor layer along the side surface of the stack and the semiconductor And characterized in that the side of the stack is constructed in such a way that the distance between the upper surface of the second region of the body is longer than the overall thickness of the insulating layer and the semiconductor layer. The present invention is based on the recognition that increasing the length of the path along the side of the stack is already sufficient to avoid the occurrence of bridging problems. The present invention also recognizes that this increased path length can be produced by a simple method of constructing the shape of the stacked pile that was orthogonal in the prior art method such that the so-called slope of the shape is changed by an increase in the path length. Based. Both the positive slope of the side of the remaining portion of the insulating layer as well as the negative slope of the side of the remaining portion of the semiconductor layer result in an increase in the path along the side of the stack of both layers. This leads to the avoidance of the bridging problem. In the case of negative inclination, the (partial) shadowing action that will also occur during the deposition of the metal layer needed to form the silicon compound will be advantageous in this respect. Finally, the present invention is based on the recognition that the configuration as expected can be achieved by simply using the etching step necessary to remove some of the insulating layer and the semiconductor layer in a specific manner to be described later. Thus, the method according to the invention does not make the above method more complicated or at least very complex. Thus, the method is also inexpensive.

In a first preferred embodiment of the method according to the invention, the removal of the semiconductor layer and the insulating layer from the second region makes the side of the remaining part of the insulating layer convex, and the remaining part of the semiconductor layer when projected from the front view. It is performed by an etching process to extend outward. The convex portion may be linear in nature but is not required. This positive outward inclination of the remaining side of the insulating layer is easily obtained if a dry etching process is used to remove the portion of the insulating layer, which is based on the chemistry of fluorine and carbon. Carbon may be provided by a photosensitive resin that will be present as a mask during the etching process. The fluorine compound can be added to the plasma. In this process a polymer of fluorine and carbon will deposit at the edge of the bottom of the hole to be etched in the insulating layer. As a result, the same etching process can remove the layers. However, as a result of these events, the remainder of the insulating layer will taper outward, for example with a slope of about 45 degrees. In this way, the length of the path along the side of the stack is increased, so bridging problems are avoided. The slope may be smaller than 45 degrees for the predicted effect, but this small slope also has disadvantages. Preferred tilt values are located between 30 and 60 degrees.

In a second preferred embodiment of the method according to the invention, the removal of the semiconductor layer from the second region makes the side of the remaining part of the semiconductor layer concave and outwards towards the remaining part of the insulating layer when projected from the front. It is carried out by an etching process to extend to. In this way the length of the path along the side is also increased in a simple way. In addition, there are shading effects that can be beneficial in avoiding bridging problems. The shape of the remaining portion of such a semiconductor layer is obtained, for example, by firstly etching the upper part of the semiconductor layer using an anisotropic dry etching process and secondly etching the lower part of the semiconductor layer using an anisotropic etching process.

In a modification having the advantages of the method according to the invention, the lower portion of the semiconductor layer has a high doping level, the upper portion of the semiconductor layer has a low doping level, and the difference in the doping level between the respective portions is desired convex. A doping method is provided for the semiconductor layer to have a remaining side surface of the semiconductor layer. Such differences can lead to different etch rates, for example, in the same wet etch solution, regardless of whether they are combined with the addition of light to the surface to be etched. In addition, when a pn-junction is applied to the semiconductor layer, selective etching of a portion of the remaining portion side of the semiconductor layer can be obtained. The pn junction can then be removed by etching or, for example, overdoping by ion implantation of appropriate doping atoms.

In one variant that draws attention to the method, after the anisotropic etching process for the semiconductor layer, the remaining side surface of the semiconductor layer is thermally oxidized, and the resulting oxide is a wet etching solution based on HF. To be removed. The difference in doping levels described above results in different depths for the oxides on the side of the remaining portion of the semiconductor layer. After the (silicon) oxide of the side is removed, a notch is formed in the lower part of the remaining portion of the semiconductor layer, providing the necessary path extension and shadowing effect. Preferably an insulating layer not yet etched will protect the semiconductor body during the above etching step. Thereafter, the insulating layer is preferably partially etched by a dry anisotropic etching process.

 Preferably, the remaining part of the insulating layer and the remaining part of the semiconductor layer and the layer on top of this layer are used as a mask for doping the second region of the semiconductor body. In this way, an increased doping level for the region, which will later serve as a connection region for the base of the bipolar transistor, is readily provided. The high speed and low consumption of the device are improved in this way.

The base 1 is in direct contact with a single crystal portion of the semiconductor body, thereby forming a first semiconductor region which is a single crystal and constitutes the base of the transistor, and is also in contact with the non-single crystal portion of the semiconductor body at a position outside the base. Thereby providing an additional doped semiconductor layer to the semiconductor body that forms a second semiconductor region constituting a connection region of the base and not a single crystal, wherein an additional collector of the semiconductor body is located below the base. It is preferably formed by the part. This process is particularly suitable for providing, for example, ultrafast heterojunction bipolar transistors with SiGe in the base.

Finally, the present invention provides an insulating region having a bipolar transistor having a base, an emitter and a collector in a silicon semiconductor body and having a window over the emitter, wherein the window extends over the surface of the insulating region. A semiconductor device filled with a silicon compound formed on an upper portion of the silicon region, an upper portion of the semiconductor body, and both sides of the insulating region, and a side surface of the stacked pile formed by the insulating region and the silicon region, The distance between the top surface of the silicon region along the side surface of the stack and the surface of the semiconductor body is constructed in such a way that it is made longer than the total thickness of the insulating region and the silicon region. Such an element characterized by the inclination of the side of the region above the base / emitter away from the direction perpendicular to the layered structure has the above-mentioned advantages, since this inclination leads to the avoidance of the bridging problem described above. High yields can be obtained by the process according to the invention. Both positive and negative slopes are suitable, and the slope may be present in the insulating or silicon region (or both).

The above and other features of the present invention will become apparent from the embodiments described hereinafter, and will be described hereinafter with reference to these embodiments.

1 to 11 are schematic cross sectional views of a semiconductor device having a bipolar transistor viewed at right angles to the thickness direction in successive manufacturing steps using the method of the first embodiment according to the present invention.

12-15 are schematic cross-sectional views of a semiconductor device with bipolar transistors viewed at right angles to the thickness direction in successive relevant manufacturing steps using the method of the second embodiment according to the present invention.

16 to 19 are schematic cross sectional views of a semiconductor device having a bipolar transistor viewed at right angles to the thickness direction in successive manufacturing steps using the method of the third embodiment according to the present invention.

The drawings are schematic and are not drawn to scale, in particular the dimensions in the thickness direction being exaggerated for clarity. Semiconductor regions of the same conductivity are hatched in the same direction. Like reference numerals denote like areas whenever possible.

1 to 11 are schematic cross sectional views of a semiconductor device having a bipolar transistor viewed at right angles to the thickness direction in successive manufacturing steps using the method of the first embodiment according to the present invention. The starting point (see FIG. 1) is formed by a p-type silicon substrate 11 provided with an epitaxial layer 33 of n-type silicon doped in the middle. Prior to the deposition of the layer 33, an buried region 3A1 of n ⁺ type is formed by ion implantation. On the surface of the semiconductor body 100, an isolation region 8 is formed of silicon dioxide as LOCOS (= LOCal Oxidation of Silion) region 8 in this embodiment. By diffusion, the connection region 3A2 is made for the connection of the collector 3 of the transistor to be formed. As a result, a thermal oxide layer 9 is formed on the surface (cleaned) of the semiconductor body 100, and a thin polycrystalline silicon layer 4 is deposited thereon. With the aid of photolithography, for example, a mask 20 of silicon dioxide is patterned on top of the polysilicon layer 4. A window is then opened by etching at the position of the active region of the bipolar transistor to be formed (see FIG. 2). Note that instead of the polysilicon layer 4, a polysilicon layer on silicon nitride may also be used, and only silicon nitride may be used.

The oxide layer 9 is then removed inside the window. After removal of the mask layer 20 (see FIG. 4), the silicon layer 12 is epitaxially deposited on top of the surface of the semiconductor body 100 and CVD (Chemical Vapor Deposition). Is deposited by. The silicon layer 12 is a single crystal in the active region of the transistor and will form the base 1 of the transistor. For this purpose the layer 12 is provided during growth with a p-type doping spike. Although not separately indicated in the figures, a thin sublayer may be provided that includes SiGe (silicon germanium) mixed crystals, which are made very thin so that they do not fit well or out of position. The silicon layer 12 over the isolation region 8 is polycrystalline and will form part of the connection region 1A of the base 1.

On top of the silicon layer 12 (see FIG. 5), a silicon dioxide layer 13, 20 to 200 nm thick, is deposited by CVD. At the position where the emitter of the transistor is to be formed, a small window is opened in the insulating layer 13 by photolithography and etching. As a result, the polycrystalline silicon layer 14 is deposited over the surface of the semiconductor body 100 by CVD, filling the opening in the insulating layer 13 and extending laterally on this layer. Here, the mask 50, which is a photosensitive resin film, has a pattern formed on the upper structure, and the width thereof is, for example, 0.5 μm, and becomes about 100 to 200 nm outside the emitter region, whereas the mask 50 The opening width in the insulating layer 13 below is, for example, about 0.3 [mu] m, but in very advanced devices it can be as small as about 100 nm. It should be noted that the layer 13 may also include different dielectric layer stacks in terms of etch stop function. It should also be noted that the bridging problem defined above and avoided in the present invention can occur especially when the thickness of the dielectric layer 13 is thinner than about 60 nm.

Thereafter (see FIG. 6), the silicon layer 14 is removed outside the mask 50 by etching, for example by dry etching. The insulating layer 13 outside the mask 50 is then also removed by dry etching. This process is based on compounds of fluorine and carbon. Therefore (see FIG. 7), the silicon dioxide layer 13 will be placed under suitable etching conditions and will gradually become thinner out of the mask 50 towards thickness 0. With the aid of a mask 70 having a width of at least 1 μm and extending 0.2 to 0.5 μm out of the active region, layers 9, 4 and 12 are removed outside the active region of the transistor to be formed. Between the steps of FIGS. 5 and 6, the remaining portion of the insulating layer 13 and the silicon layer 14 and the mask layer 50 over the layer inject additional p-type impurities into the silicon layer 12 outside the upper structure. It is used to make. The resistance of the base connection region 1A is reduced in this way.

After the layers 9, 4, 12 are removed out of the active region of the transistor to be formed, a metal layer 16 of titanium is deposited on the structure 100 (see FIG. 8). Metal layer 16 may also be a stack of different metal layers. During a short heat treatment at 720 degrees Celsius (see FIG. 9), the metal layer 15 reacts with the silicon portion, which is the position of the base connection region 1A, the position of the collector connection region 3A2, and Exposed to form silicon compound 17 at a location in the polysilicon region above the emitter. Next (see FIG. 10), the portion of the metal layer 16 that did not react with the silicon is removed by etching. During the subsequent heat treatment at 850 degrees Celsius, the silicon compound 17 is converted from a silicide to a disilicide, the latter having lower sheet resistance. At the same time the emitter 2 is formed by outdiffusion of impurities from the rest of the silicon layer 14 to the base layer 12. For this reason, since the embodiment of the present invention deals with npn bipolar transistors, the polysilicon layer 14 is doped n-type during deposition. The emitter can also be formed in a separate Rapid Thermal Anealing (RTA) at about 1000 degrees Celsius, for example, before silicidation occurs.

Since there is a tapered region in the insulating layer 13 outside the remaining part of the silicon layer 14, the distance between the remaining part of the polysilicon 14 and the surface of the silicon layer 12 is determined by the insulation. The remaining side of the layer 13 is increased compared to the case where it is perpendicular to the layer structure. In this way bridging of the silicon compound 17 formed on top of the remaining portion of the silicon layer 14 and on top of the silicon layer 12 is avoided during the silicon compound formation step described above.

Finally (see FIG. 11), an insulating layer 18 of, for example, silicon dioxide is deposited on the surface of the semiconductor body 100. An opening is provided in which a connecting conductor 19 is formed. After the device 10 formed therein is separated from the wafer, the device is suitable for use.

12-15 are schematic cross-sectional views of a semiconductor device with bipolar transistors viewed at right angles to the thickness direction in successive relevant manufacturing steps using the method of the second embodiment according to the present invention. Since many of the manufacturing steps are the same as in the previous embodiment, these steps will not be described repeatedly, and only important steps will be discussed. After reaching the situation of FIG. 5, the manufacturing step proceeds as shown in FIG. 12. In this embodiment, the etching of the polysilicon layer 14 is performed in the following manner, wherein the remaining portion of the silicon layer 14 has a negative slope, that is, the side surface of the insulating layer 13 under the mask 50. Taper inwards and downwards toward the contact surface. In this embodiment, the above structure is obtained by etching the silicon layer 14 in two etching steps, the first etching step being based on Cl2 chemistry to obtain anisotropy, and to obtain sidewall passivation. Based on HBr, the second isotropic etching step is based on fluorine chemistry using, for example, SF6. The insulating layer 13 is then removed using an anisotropic etching process that brings the side perpendicular to the layer structure (see FIG. 13). 13, 14, and 15 correspond to the steps of FIGS. 7, 8, and 10, and the steps of FIG. 9 are not separately shown in this embodiment.

In this embodiment the length of the path along the side of the stack of stacks formed from the remaining portions of the insulating layer 13 and the silicon layer 14 has an increased length. Therefore, bridging of silicon compounds 17 formed on top of layers 12 and 14 is avoided. The negative shading effect can be observed in FIG. 14, with the advantage of little or even no metal deposition on the sides of the polysilicon.

16 to 19 are schematic cross sectional views of a semiconductor device having a bipolar transistor viewed at right angles to the thickness direction in successive manufacturing steps using the method of the third embodiment according to the present invention. This embodiment refers again to the first embodiment for most of the manufacturing steps. In this embodiment, the relevant steps corresponding to FIG. 6 are shown in FIG. In this embodiment, the portion of the silicon layer 14 has two different doping levels on both sides hatched, while the lower portion 14A is provided with a high doping level, whereas the upper portion 14B is provided with a low doping level. do. After removing the silicon layer 14 outside the mask 50 (see FIG. 17), the side of the remaining portion of the silicon layer 14 is thermally oxidized to form the oxide region 40. Since the oxidation rate of silicon is fast at high doping levels, the oxide region 40 has a stepped shape as shown in FIG. The oxide region 40 is removed after being immersed in an aqueous HF solution (see FIG. 17). As a result, the remaining portion of the silicon layer 14 has a notch immediately below the remaining portion of the insulating layer 13.

Here again the path lengthening and shading effects occur on the side of the lamination pile of the remaining portions of the insulating layer 13 and the silicon layer 14, whereby again bridging occurs during the formation of the silicon compound 17. This is avoided. The steps of FIGS. 18 and 19 correspond to the steps of FIGS. 9 and 10, and the situation of FIG. 9 is not again shown separately.

Finally, the layer (s) deposited in and near the emitter window (in the dielectric layer) is shown in the figure as having a planar top surface, which is actually ditch at the location of the window rather than the plane. Note that you can have a / notch. The present invention is also based on the recognition that such ditches / grooves reduce the possibility of using (outer) spacers.

The present invention is not limited to the above-described embodiment, and many modifications and variations are possible to those skilled in the art within the scope of the present invention. For example, combinations and thicknesses for different (semiconductor) layers or regions may be chosen differently than described in the always examples. It is also possible to use different deposition techniques such as sputtering of Molecular Beam Epitaxy (MBE) or Physical Vapor Deposition (PVD).

The method according to the invention can be applied very well to more complex devices than a single bipolar transistor. The device may include a number of different active or passive electronic or semiconductor devices. The transistor may form part of a Bi (C) MOS IC (Bipolar (Complementary) Metal Oxide Semiconductor Integrated Circuit).

Claims (10)

A method of manufacturing a semiconductor device (10) comprising a silicon semiconductor body (100) having a bipolar transistor having a base (1), an emitter (2) and a collector (3), wherein the emitter (2) is a semiconductor body. Is formed in the first region of the (100), the electrical insulating layer 13 is formed in the semiconductor body 100, the window is formed in the first region of the semiconductor body 100, the insulating layer 13 A silicon semiconductor layer 14 is formed on the insulating layer 13 which fills the window in the sidewall and extends laterally on the insulating layer 13 along the window. After deposition of the semiconductor layer 14, the semiconductor layer 14 and the insulating layer 13 are removed from the second region of the semiconductor body 100, the second region comprising a remaining portion of the insulating layer 13 and the remaining portion of the semiconductor layer 14 In contact with the first region covered by the dummy, the metal layer 16 is the remaining portion of the semiconductor layer 14 Deposited on top of the second region of the silicon semiconductor body 100 and between the metal layer 16 and the second region of the silicon semiconductor body 100 and between the metal layer 16 and the remaining portions of the silicon semiconductor layer 14. In the method of manufacturing the semiconductor device 10, a silicon oxide 17 is formed, and means for preventing bridging of the silicon oxide 17 is provided on the side of the stack. Means for preventing the bridging of the silicon compounds from forming between the upper surface of the remaining portion of the semiconductor layer 14 along the side surface of the stack and the upper surface of the second region of the semiconductor body 100 Characterized in that the side of the stack is constructed in such a way that the distance is longer than the total thickness of the insulating layer 13 and the semiconductor layer 14. Method of manufacturing a semiconductor device. The method of claim 1, The step of removing the semiconductor layer 14 and the insulating layer 13 in the second region is that the side of the remaining portion of the insulating layer is formed in a block and is projected from the front to the outside of the remaining portion of the semiconductor layer 14. A method of manufacturing a semiconductor device, characterized in that performed by an etching process to be extended. The method of claim 2, And a dry etching process is used for the etching process together with a chemical reaction based on a compound of fluorine and carbon. The method of claim 1, The removing of the semiconductor layer 14 in the second region may include forming a concave side surface of the remaining portion of the semiconductor layer 14 and extending inward toward the remaining portion of the insulating layer 13 when viewed from the front. A method of manufacturing a semiconductor device, characterized in that carried out by an etching process. The method of claim 4, wherein A first upper portion of the semiconductor layer (14) is etched using an anisotropic dry etching process, and a second lower portion of the semiconductor layer (14) is etched using an anisotropic etching process. The method of claim 4, wherein In the semiconductor layer 14, the lower portion 14A of the semiconductor layer 14 has a high doping level, and the upper portion 14B of the semiconductor layer 14 has a low doping level, and between the portions 14A and 14B. A method of manufacturing a semiconductor device, characterized in that a doping method is provided such that a difference in doping level is used to form a desired concave side for the remaining portion of the semiconductor layer (14). The method of claim 6, After the anisotropic etching process for the semiconductor layer, the side surface of the remaining portion of the semiconductor layer 14 is thermally oxidized, and the resulting oxide is subsequently removed by a wet etching solution based on HF. Method of manufacturing the device. The method according to any one of claims 1 to 7, The remaining portion of the insulating layer 13, the remaining portion of the semiconductor layer 14 and one layer on the upper layer are used as a mask for doping the second region of the semiconductor body 100. Method of manufacturing a semiconductor device. The method according to any one of claims 1 to 8, The base 1 is an additional doped semiconductor layer 12 that is in contact with the single crystal portion of the semiconductor body 100 to form a first semiconductor region that is single crystal and constitutes the base 1 of the transistor and And also contacting the non-single-crystal portion of the semiconductor body 100 at a position outside of the base 1, thereby forming a second semiconductor region which constitutes the connection region 1A of the base and not a single crystal. Formed by providing an additional semiconductor layer 12 to the semiconductor body 100, The collector (3) is characterized in that it is formed by an additional part of the semiconductor body (100) located below the base (1). An insulating region 13 having a bipolar transistor having a base 1, an emitter 2 and a collector 3 in a silicon semiconductor body 100 and having a window on the emitter 2, wherein the window is The insulating region 13 is filled with a silicon semiconductor region 14 extending over the surface of the insulating region 13, the upper portion of the silicon region 14, the upper portion of the semiconductor body 100 and the insulating region In the semiconductor device 10 having the silicon compound 17 formed on both sides of (13), The side surface of the stacked stack formed by the insulating region 13 and the silicon region 14 is formed between the upper surface of the silicon region 14 and the surface of the semiconductor body 100 along the side surface of the stack. Characterized in that it is constructed in such a way that the distance is made longer than the total thickness of the insulating region 13 and the silicon region 14. Semiconductor device.

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