KR100591121B1 - Semiconductor device and method of fabricating thereof - Google Patents

Abstract

A method of manufacturing a semiconductor device according to the present invention includes the steps of forming a gate oxide film on a substrate, forming a lightly doped region in a predetermined region of the substrate to define a channel region, forming a nitride film and a sacrificial oxide film on the gate oxide, Removing a predetermined region of the oxide layer and the nitride layer to form a trench exposing a gate oxide layer corresponding to the channel region, forming a gate filling the trench, removing the sacrificial oxide layer, etching the nitride layer to form a spacer Removing the gate oxide film which is not protected by the spacer and the gate; forming a source region and a drain region by doping impurities in the substrate at a high concentration; forming a silicide by forming a metal film on the substrate and then performing a heat treatment. do.

Semiconductor, gate, silicide

Description

Semiconductor device and method of manufacturing the same

1 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

2 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in order of process.

The present invention relates to a semiconductor device and a manufacturing method thereof.

The performance of a transistor constituting a semiconductor device is closely related to the speed, drive current, and leakage current of the transistor. Therefore, in order to increase the speed of the transistor and reduce the leakage current, the resistance of the source and drain of the transistor, the resistance of the gate of the transistor, and the resistance of the contact portion must be small.

In order to reduce the resistance of this portion, silicide is formed at the interface between the drain and the source and the interface between the gate and the gate. The silicide is formed by depositing a metal such as titanium (Ti) or cobalt (Cobalt) and performing a rapid temperature process (RTP) to react the lower layer with the metal to form silicide.

However, as the degree of integration of the device is improved, the line width of the circuit is also narrowed, thereby reducing the area where silicide is formed. In addition, if a misalignment occurs in the process of forming the wiring connected to the gate, the wiring is in contact with the side of the gate on which the silicide is not formed due to the misalignment, resulting in an increase in resistance.

To reduce this increase in resistance, the area of silicide must be increased. However, in the conventional structure, as the area of the silicide increases, the area of the gate also increases, resulting in a decrease in the degree of integration of the device.

In addition, notches and feet are generated during etching to form the gate, making it difficult to form a vertical cross section. As a result, as semiconductor devices become smaller and more integrated, they are facing limitations in satisfying the critical dimension of the gate (CD).

Accordingly, the present invention provides a semiconductor device and a method of manufacturing the same, which can maximize the area of silicide while stably securing the gate CD.

The present invention for achieving the above object is to form a gate using a damascene process, and to form a silicide on the side of the gate.

Specifically, the method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate oxide film on a substrate, defining a channel region by forming a low concentration doped region in a predetermined region of the substrate, forming a nitride film and a sacrificial oxide film on the gate oxide film. Removing the predetermined regions of the sacrificial oxide film and the nitride film to form a trench exposing the gate oxide film corresponding to the channel region, forming a gate filling the trench, removing the sacrificial oxide film, etching the nitride film, and etching the spacer Removing the gate oxide film which is not protected by the spacers and the gate; forming a source region and a drain region by doping impurities to the substrate at a high concentration; forming a metal film on the substrate and then performing a heat treatment to form silicide Steps.

The nitride film is preferably formed to a thickness of 2,000-2,500 kPa.

In addition, the sacrificial oxide film is preferably formed to a thickness of 500 to 1,000 GPa.

A semiconductor device according to the present invention for achieving the above-mentioned other objects is formed on a substrate, a substrate, a source region and a drain region defining a channel region, a low concentration doping region, a channel region formed between the source region and the drain region And a gate oxide film overlapping a predetermined region of the lightly doped region, a gate formed on the gate oxide film corresponding to the channel region, and a spacer formed on a side surface of the gate and having a lower thickness than the gate.

It is preferable to further include a silicide formed on the upper surface of the substrate and the gate and a portion of the side surface of the gate corresponding to the source region and the drain region.

The spacer is preferably positioned 500 to 1,000 mm below the upper surface of the gate.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification.

First, a semiconductor device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 1, in a semiconductor device, a source region and a drain region 22, and channel regions located between them, are formed in a substrate 10 in which device isolation regions (not shown) are defined. The source region and the drain region 22 may be heavily doped with conductive impurity ions, and the channel region may be an intrinsic semiconductor region, and may be doped with threshold voltage (Vth) ions.

A gate oxide film 12 is formed on the substrate 10 corresponding to the channel region, and a gate 20 having a spacer 16 is formed on the sidewall of the gate oxide film 12. Since the spacer 16 is lower than the gate 20, the upper side of the gate 20 is completely exposed from some spacer 16. The spacer 16 is made of nitride such as silicon nitride, and the gate 20 is made of polycrystalline silicon.

In the substrate 10 corresponding to the spacer 16, a lightly doped region 14 in which conductive impurities are doped at a lower concentration than the source and drain regions 22 is formed.

In addition, the silicide layer may be formed on the side of the gate 20 and the upper portion of the gate 20, which are not covered by the source and drain regions 22 and the spacers 16 of the substrate 10 that are not exposed because the gate oxide layer 12 is not formed. 24) is formed.

As described above, in the silicide according to the present invention, since the silicide 24 is formed not only on the upper surface of the gate 20 but also on a part of the side surface of the gate 20, the silicide 24 is formed without increasing the size of the gate 20. Increasing the area can minimize contact resistance. In addition, since the silicide 24 is formed on the side surface of the gate 20, the contact resistance does not increase even when misalignment occurs when forming a via for contact with the gate 20 in a subsequent process.

A method of forming a semiconductor device having such a structure will be described in detail with reference to FIGS. 2 to 7 and FIG. 1 described above.

First, as shown in FIG. 2, an isolation region (not shown) is formed in the semiconductor substrate 10 by an STI or LOCOS method to define an active region. The substrate 10 is thermally oxidized to form a gate oxide film 12 directly on the substrate 10. The gate oxide film 12 is a buffer film for protecting the substrate 10 in a subsequent process and is formed to a minimum thickness such that it is not destroyed at a constant voltage.

Next, as shown in FIG. 3, a photoresist film is formed on the gate oxide film 10, and then patterned by a photo process to form a photoresist pattern PR defining a channel region.

Thereafter, the conductive dopant ions are lightly doped in a predetermined region of the substrate 10 using the photoresist pattern PR to form a lightly doped region 14. At this time, the conductive impurity ions are P-type or N-type conductivity, boron (B), gallium (Ga), etc. are used as the P-type conductivity, and phosphorus (P), arsenic (As) as the N-type impurities Etc.

Next, as shown in FIG. 4, after removing the photoresist pattern PR, the nitride film 16A and the sacrificial oxide film 18 are sequentially formed on the substrate 10. The nitride film 16A and the sacrificial oxide film 18 are formed by a method such as chemical vapor deposition.

The thickness of the nitride film 16A and the sacrificial oxide film 18 is formed to be equal to or thicker than the height of the gate to be formed later. The thickness of the sacrificial oxide film 18 is determined according to the required resistance of the semiconductor device. Since the area of the silicide formed on the side surface of the gate varies according to the thickness of the sacrificial oxide film 18, the resistance value changes accordingly. In addition, when the thickness of the nitride film 16A becomes too thin, the width of the spacer formed later is reduced, so that a low concentration doped region of a required size cannot be formed.

Therefore, the thicknesses of the nitride film 16A and the sacrificial oxide film 18 are selected according to the required size of the low concentration doped region and the resistance value.

Thereafter, a photoresist layer is formed on the sacrificial oxide layer 18 and then patterned by a photo process to form a photoresist pattern PR for defining a gate. Then, the sacrificial oxide layer 18 and the nitride layer 16A are etched using the photoresist pattern PR as a mask to form a trench T exposing the gate oxide layer 12.

Next, as shown in FIG. 5, after removing the photoresist pattern PR, polycrystalline silicon is deposited on the entire surface of the substrate 10 including the trench T to form a polycrystalline silicon film. Thereafter, the polycrystalline silicon film is polished by chemical mechanical polishing (CMP) until the sacrificial oxide film 18 is exposed to form the gate 20 filling the trench T.

Next, as shown in FIG. 6, the sacrificial oxide film 18 is removed by wet etching or dry etching. Then, after forming the photoresist pattern, the nitride layer 16A is removed by an etching process to form the spacer 16 on the side of the gate 20. In this case, the spacer 16 is formed below a predetermined distance from the upper surface of the gate 20, and the predetermined distance is the thickness of the sacrificial oxide film 18. The gate oxide film 12 that is not protected by the gate 20 and the spacer 16 together with the spacer 16 is removed to expose the source region and the drain region.

Next, as shown in FIG. 7, the source and drain regions 22 are formed by doping the substrate 10 with a high concentration of conductive impurities using the spacers 16 and the gate 20 as a mask.

Then, as shown in FIG. 1, a metal such as titanium (Ti) or cobalt (Co) is deposited on the entire surface of the substrate 10, and then heat-treated by rapid heat treatment to form the silicide 24. The silicide 24 is then formed on the top surface of the gate 20, which is not protected by the spacer 16, and on the predetermined region and the source region and the drain region 22 on the side of the gate 20.

As described above, when the shape of the gate 20 is limited by using the nitride film 16A, notches or footing do not occur, thereby ensuring a stable and uniform width of the gate 20. The reliability of the is improved.

In addition, silicide is formed on the side surface of the gate 20 to increase the area of the silicide, thereby reducing the resistance of the silicide. In addition, even if misalignment occurs in forming vias to contact the gate 20, the contact resistance of the gate 20 does not increase.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications of those skilled in the art using the basic concept of the present invention defined in the following claims are also the rights of the present invention. It belongs to the range.

As described above, when the gate is formed as in the present invention, the gate width can be easily controlled to form a gate having a narrower width than that of the related art, thereby achieving miniaturization and high integration of the semiconductor device. In addition, the area of the silicide can be easily increased to minimize the resistance of the silicide.

Claims (6)

Forming a gate oxide film on the substrate, Defining a channel region by forming a lightly doped region in a predetermined region of the substrate, Forming a nitride film and a sacrificial oxide film on the gate oxide film, Removing a predetermined region of the sacrificial oxide layer and the nitride layer to form a trench exposing the gate oxide layer corresponding to the channel region; Forming a gate filling the trench; Removing the sacrificial oxide film, Etching the nitride film to form a spacer; Removing the gate oxide film not protected by the spacer and the gate; Doping impurities to the substrate at a high concentration to form a source region and a drain region, Forming a silicide by forming a metal film on the substrate and then performing heat treatment to form a silicide. In claim 1, The nitride film is a semiconductor device manufacturing method to form a thickness of 2,000 ~ 2,500Å. In claim 1, The sacrificial oxide film is a manufacturing method of a semiconductor device to form a thickness of 500 ~ 1,000Å. Board, A source region and a drain region formed in the substrate, A channel region positioned between the source region and the drain region, A lightly doped region extending from the source region and the drain region to the channel region, A gate oxide layer overlapping a predetermined region of the channel region and the lightly doped region, A gate formed on the gate oxide layer corresponding to the channel region, A spacer formed on a side of the gate and having a height lower than that of the gate, And a silicide formed on the substrate corresponding to the source and drain regions, and on an upper surface of the gate and a portion of a side surface of the gate. delete In claim 4, And the spacer is positioned 500 to 1,000 micrometers below the upper surface of the gate.

Images