JP2005079518A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is superior in high-frequency operation by reducing the junction capacity between a collector and a substrate, and provide a method for manufacturing the semiconductor device. <P>SOLUTION: This semiconductor device is a one having a function as a bipolar transistor having an emitter layer, a base layer, and a collector layer, and has an n<SP>-</SP>type Si layer 201 having nearly the same impurity density with the semiconductor substrate below an n<SP>+</SP>buried layer 101. The method for manufacturing the semiconductor device is a one for manufacturing the semiconductor device having the function as a bipolar transistor having an emitter layer, a base layer, and a collector layer, and the n<SP>-</SP>type Si layer 201 which is positioned below the n<SP>+</SP>buried layer 101 and has nearly the same impurity density with the semiconductor substrate is formed by using ion injection. By these means, the junction capacity between the buried layer and substrate is reduced to improve high frequency characteristics. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a manufacturing method of a hetero bipolar transistor.

  In recent years, for the purpose of improving high-frequency characteristics, development of a heterobipolar transistor (HBT) in which a bipolar transistor formed on a silicon substrate includes a heterojunction structure of Si / SiGe has been advanced.

  Since this HBT is made of a material having a good affinity with a general-purpose silicon process such as a Si substrate and a SiGe layer, it has great advantages of high integration and low cost. Further, a high-performance BiCMOS device can be configured by forming and integrating an HBT and a MOS transistor (MOSFET) on a common Si substrate, and this BiCMOS device can be used for communication. As promising.

For this reason, many proposals have been made on Si / Si _1-x Ge _x type HBTs.

As an example of a conventional Si / Si _1-x Ge _x type HBT, there has been known one described in Patent Document 1.

FIG. 10 shows a conventional Si / Si _1-x Ge _x It is sectional drawing which shows the structure of type | mold HBT.

As shown in the figure, an upper portion of a p-type Si substrate 500a having a (001) plane as a main surface includes a buried layer 501 having a depth of 1 μm containing n-type impurities such as arsenic and phosphorus, and an n-type Si epitaxial growth layer 500b. It has become. The n-type impurity concentration of the n-type epitaxial growth layer 500b is adjusted to about 10 ¹⁶ atoms · cm ⁻³ . The impurity concentration of the Si substrate 500 is about 10 ¹⁶ atoms · cm ⁻³ , and the impurity concentration of the buried layer 501 is on the order of 10 ¹⁸ to 10 ¹⁹ atoms · cm ⁻³ . Further, as element isolation, a shallow trench 503 in which silicon oxide is embedded, and a deep trench 504 including an undoped polysilicon film 505 and a silicon oxide film 506 surrounding the undoped polysilicon film 505 are provided.

A collector layer 502 is provided in a region sandwiched between the trenches 503 in the n-type Si epitaxial growth layer 500b, and an electrode of the collector layer 502 is interposed in the region separated from the collector layer 502 by the shallow trench 503 through the buried layer 501. An n ⁺ collector extraction layer 507 is provided for contact with.

A first deposited oxide film 508 having a collector opening 510 and having a thickness of about 30 nm is provided on the n-type Si epitaxial growth layer 500b, and a polysilicon layer is formed on the first deposited oxide film 508. 509 is provided. On the upper surface of the n-type Si epitaxial growth layer 500b, on the portion exposed to the collector opening 510, a Si _1-x Ge _x layer having a thickness of about 60 nm doped with a p-type impurity and a Si film having a thickness of about 10 nm. And a Si / Si _1-x Ge _x layer 511 is provided. The Si / Si _1-x Ge _x layer 511 extends from the entire surface exposed to the collector opening 510 of the n-type Si epitaxial growth layer 500b to the polysilicon layer 509.

The lower part of the central portion of the Si _1-x Ge _x layer 511 functions as an internal base 519, and the upper portion of the central part of the Si / Si _1-x Ge _x layer 511 functions as an emitter layer.

Most of the Si1-x Gex layer in the Si / Si _1-x Ge _x layer 511 is doped to about 2 × 10 ¹⁸ atoms · cm ⁻³ by a p-type impurity such as boron (B). Is about 1 × 10 ²⁰ atoms · cm ⁻³ to 1 × 10 ¹⁷ atoms · cm ^{−3 in} the depth direction of the substrate by diffusion of n-type impurities such as phosphorus (P) from the n ⁺ polysilicon layer 529. Doped with a distribution of up to.

  Here, it arrange | positions so that the end of shallow trench 503 may become inside rather than the end of collector opening part 510. FIG. Thereby, since the shallow trench 503 is arrange | positioned inside, the total area of HBT can be reduced.

A second deposited oxide film 512 for an etch stopper having a thickness of about 30 nm is provided on the Si / Si _1-x Ge _x layer 511. The second deposited oxide film 512 is used for base bonding. An opening 514 and a base opening 518 are formed. The outer width A of the second deposited oxide film 512 around the base opening 518 is as shown in FIG.

A p ⁺ polysilicon layer 515 having a thickness of about 150 nm and a third deposited oxide film 517 are provided to fill the base junction opening 514 and extend on the second deposited oxide film 512. An external base 516 is constituted by a portion of the Si / Si _1-x Ge _x layer 511 excluding the region below the base opening 518 and the p ⁺ polysilicon layer 515.

Of the p ⁺ polysilicon layer 515 and the third deposited oxide film 517, the portion of the second deposited oxide film 512 located above the base opening 518 is opened, and is formed on the side surface of the p ⁺ polysilicon layer 515. A fourth deposited oxide film 520 having a thickness of about 30 nm is formed, and a sidewall 521 made of polysilicon having a thickness of about 100 nm is provided on the fourth deposited oxide film 520. An n ⁺ polysilicon layer 529 is provided to fill the base opening 518 and extend on the third deposited oxide film 517, and this n ⁺ polysilicon layer 529 functions as an emitter lead electrode. By the fourth deposited oxide film 520, p ⁺ with a polysilicon layer 515 and the n ⁺ polysilicon layer 529 is electrically insulated, of impurities from the p ⁺ polysilicon layer 515 to the n ⁺ polysilicon layer 529 Diffusion is blocked. Further, the upper surface of p ⁺ polysilicon layer 515 and n ⁺ polysilicon layer 529 are insulated by third deposited oxide film 517. Further, the outer surfaces of the n ⁺ polysilicon layer 529 and the p ⁺ polysilicon layer 515 are covered with sidewalls 523.

Of the Si / Si _1-x Ge _x layer 511 of the HBT, high-concentration n-type impurities (such as phosphorus) diffuse from the n ⁺ polysilicon layer 529 into the Si layer to form an n ⁺ -type Si layer. ing.

Further, Ti silicide layers 524 are formed on the surfaces of the collector lead layer 507, the p ⁺ polysilicon layer 515 and the n ⁺ polysilicon layer 529, respectively.

The entire substrate is covered with an interlayer insulating film 525, penetrating through the interlayer insulating film 525, an n ⁺ collector extraction layer 507, a p ⁺ polysilicon layer 515 that is a part of the external base, and an n n that is an emitter extraction electrode. ⁺ Connecting holes reaching the Ti silicide layer 524 on the polysilicon layer 529 are formed. A W plug 526 filling each connection hole and a metal wiring 527 connected to each W plug 526 and extending on the interlayer insulating film 525 are provided.
JP 2000-332025 A

  However, in the above-described conventional HBT, the area occupied by the buried layer 501 is large, and there is a junction capacitance between the buried layer 501 and the Si substrate 500a. This junction capacitance limits the frequency characteristics.

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that improve high-frequency characteristics by reducing the junction capacitance between a buried layer and a substrate in HBT or BiCMOS.

In order to solve this problem, the semiconductor device of the present invention has a configuration in which an n ⁻ type Si layer 201 having an impurity concentration comparable to that of a semiconductor substrate is provided below the n ⁺ buried layer 101, and the semiconductor of the present invention. The device manufacturing method is a method of manufacturing a semiconductor device having a function as a bipolar transistor having an emitter layer, a base layer, and a collector layer, and is located under the n ⁺ buried layer 101 and has an impurity concentration equivalent to that of the semiconductor substrate. An n ⁻ -type Si layer 201 having n is formed by ion implantation. By these means, the junction capacitance between the buried layer and the substrate can be reduced and the high frequency characteristics can be improved.

  As described above, according to the present invention, it is possible to obtain an advantageous effect that a semiconductor device with improved high-frequency characteristics can be manufactured.

(Embodiment 1)
Hereinafter, embodiments of the present invention will be described with reference to FIGS.

  1 to 3 are cross-sectional views showing a method of manufacturing SiGe-HBT according to an embodiment of the present invention.

First, as shown in FIG. 1A, a protective oxide film 200 is formed on an upper portion of a p-type Si substrate 100 having a (001) plane as a main surface. Next, as shown in FIG. 1B, the protective oxide film 200 is patterned in the region where the HBT is to be formed, n-type impurity high energy ion implantation is performed using the protective oxide film 200 as a mask, and the impurity concentration is 10 ^15. atoms · cm ^-3 or more 10 ¹⁷ atoms · cm ^-3 or less to form an n ^- first buried layer 201 of the mold. Subsequently, by ion-implanting an n-type impurity with an energy smaller than that for forming the first buried layer 201, an n ⁺ -type second buried layer 101 having an impurity concentration of about 10 ¹⁹ atoms · cm ⁻³ is formed. Form. Thereafter, after heat treatment (annealing), the n-type epitaxial Si layer 202 is grown to obtain a structure as shown in FIG.

Here, although the impurity concentration of the first buried layer 201 is set to 10 ¹⁷ atoms · cm ⁻³ or less, it is preferably about 1 × 10 ¹⁶ atoms · cm ⁻³ .

Next, as element isolation, a shallow trench 103 in which silicon oxide is embedded, and a deep trench 104 including an undoped polysilicon film 105 and a silicon oxide film 106 surrounding the undoped polysilicon film 105 are formed. The depths of the trenches 103 and 104 are set to about 0.2 to 0.4 μm and 3 to 5 μm, respectively. A region sandwiched between the shallow trenches 103 in the n-type epitaxial Si layer 202 becomes the collector layer 102. Further, an n ⁺ collector lead layer 107 for contacting the collector electrode is formed in a region separated from the collector layer 102 in the n-type epitaxial Si layer 202 by the shallow trench 103.

  Then, HBT is formed on the n-type epitaxial Si layer 202 in the same manner as in the prior art, and a wiring process is performed to obtain the structure shown in FIG. 4 is the same as FIG. 4 according to the prior art, except that the numeral “5” in the hundreds is “1” in FIGS.

  By using the semiconductor device and the method for manufacturing the semiconductor device, a wide depletion layer is formed between the semi-first buried layer 201 and the p-type Si substrate 100. As a result, the junction capacitance between the substrate and the collector layer can be reduced, and the high frequency characteristics can be improved.

(Embodiment 2)
In place of the Si _1-x Ge _x layer 111 in the above embodiment, a Si _1-xy Ge _{x Cy} layer (0 ≦ x + y ≦ 1) or an Si _{1-y Cy} layer (0 ≦ y ≦ 1) is used. A film made of a material different from Si containing Si can be used. Alternatively, a film in which two or more of a Si _1-x Ge _x layer, a Si _1-xy Ge _{x Cy} layer, a Si _{1-y Cy} layer, and the like are stacked may be used.

  By using the various materials described above, distortion applied to the semiconductor layer can be suppressed, leading to improvement in reliability of the manufactured semiconductor device and reduction in leakage current.

  In addition, the bipolar transistor in each of the above embodiments is not necessarily limited to the hetero-bipolar transistor, but is also a problem in the bipolar using the Si layer which is a homoepitaxial growth film as a base.

The formation 201 of the first buried layer implantation amount 1 × 10 ¹³ cm ^-2, the implantation energy 250 keV, an implantation angle 0 deg, the second buried layer 101 injection of 1 × 10 ¹⁵ cm ^-2, the implantation energy 25 keV, implantation angle 7deg Ion implantation was performed. The resistivity of the n-type epitaxial Si layer 202 was 1 ohm · cm.

  As described above, according to the present invention, it is possible to obtain an advantageous effect that a semiconductor device with improved high-frequency characteristics can be manufactured.

Sectional drawing which shows the manufacturing process of the semiconductor device of the 1st Embodiment of this invention. Sectional drawing which shows the manufacturing process of the semiconductor device of the 1st Embodiment of this invention. Sectional drawing which shows the semiconductor device of the 1st Embodiment of this invention Sectional view showing a conventional semiconductor device

Explanation of symbols

100 (001) Si substrate 101 Retrograde well 102 Collector layer 103 Shallow trench 104 Deep trench 105 Undoped polysilicon film 106 Silicon oxide film 107 N ⁺ collector extraction layer 108 First deposited oxide film 110 Collector opening 111 Si / Si1- x Gex layer 112 Second deposited oxide film 113 Junction leak prevention layer 114 Base junction opening 115 P ⁺ polysilicon layer 116 External base 117 Third deposited oxide film 118 Base opening 119 Internal base 120 Fourth deposited oxide Film 121 Side wall 123 Side wall 124 Ti silicide layer 125 Interlayer insulating layer 126 W plug 127 Metal wiring 129 N ⁺ polysilicon layer Rai active region / isolation junction 200 P ⁺ polysilicon layer

500 (001) Si substrate 501 Retrograde well 502 Collector layer 503 Shallow trench 504 Deep trench 505 Undoped polysilicon film 506 Silicon oxide film 507 N ⁺ collector extraction layer 508 First deposited oxide film 510 Collector opening 511 Si / Si1- x Gex layer 512 Second deposited oxide film 513 Junction leak prevention layer 514 Base junction opening 515 P ⁺ polysilicon layer 516 External base 517 Third deposited oxide film 518 Base opening 519 Internal base 520 Fourth deposited oxide Film 521 Side wall 523 Side wall 524 Ti silicide layer 525 Interlayer insulating layer 526 W plug 527 Metal wiring 529 N ⁺ polysilicon layer

Claims (4)

A semiconductor device provided in an active region of a semiconductor substrate and having a function as a bipolar transistor having an emitter layer, a base layer, and a collector layer,
A part of the semiconductor substrate is provided with a layer in which n ⁻ type Si having an impurity concentration similar to that of the semiconductor substrate is embedded,
A semiconductor device comprising a layer in which n ⁺ type Si is embedded above the layer in which n ⁻ type Si is embedded. A method of manufacturing a semiconductor device that functions as a bipolar transistor having an emitter layer, a base layer, and a collector layer,
A layer embedded with n ⁻ -type Si having an impurity concentration equivalent to that of the semiconductor substrate is formed by ion implantation, and n ⁺ -type Si is embedded above the n ⁻ -type Si embedded layer. A method for manufacturing a semiconductor device, characterized by being formed by implantation. The semiconductor device according to claim 1.
Base layer is _{Si 1-x Ge x (0} ≦ x ≦ 1), Si 1-xy Ge x C y (0 ≦ x + y ≦ 1) and Si1-y Cy (0 ≦ y ≦ 1) at least one of the 1 A semiconductor device comprising: The method of manufacturing a semiconductor device according to claim 2.
The base layer is at _{least one} of Si _1-x Ge _x (0 ≦ x ≦ 1), Si _1-xy Ge _{x Cy} (0 ≦ x + y ≦ 1), and Si _{1-y Cy} (0 ≦ y ≦ 1). A method for manufacturing a semiconductor device, comprising:

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