JP2001035858A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bipolar transistor, which is low in a base resistance and can be actuated at a high speed, and the manufacturing method of the bipolar transistor. SOLUTION: A collector layer 12 is formed on a region on the vicinity of the surface of an Si substrate 10 and an Si1-xGex/Si layer 21 is formed on the layer 12. A polysilicon emitter layer 30 is provided on the central part of the layer 21 and a third insulating layer 42, a first sidewall 24, a P+ regrowth Si layer 25 and a fourth insulating layer 26 are provided in such a way as to encircle the layer 30. An internal base 29 and an external base 19 are formed in a self alignment and the distance (W2-W1)/2 between an emitter-base junction part and the base 19 is set so as to coincide with the thickness of the sidewall 24. As there is no need to anticipate a margin, a base resistance can be reduced and at the same time, the parasitic capacitance between electrodes can be also reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a hetero-bipolar transistor.

[0002]

2. Description of the Related Art In recent years, a bipolar transistor formed on a silicon substrate has a heterojunction between an emitter-base and a base-collector so that the transistor has excellent electric conduction characteristics and can be used in a higher frequency region. Hetero bipolar transistor (HBT) for realizing operation
Is being developed at a rapid pace. If an element that operates in the frequency region, which has been realized only by a compound semiconductor, can be formed by using a material having an affinity with a silicon process, there is a great merit that the integration degree can be improved and the cost can be reduced. In particular, by forming a heterobipolar transistor on the same silicon substrate as a MOS transistor and integrating it, a high-performance Bi-CMOS L
It can constitute an SI and is promising as a system LSI used for communication-related equipment. Until now, Si / Si
_1-x Ge _x and HB using a heterostructure of Si / SiC, etc.
T has been proposed and prototyped. Among them, along with the emitter layer and the collector layer is constituted by Si, the base layer is constituted by SiGe layer Si / Si _1-x Ge x based HB
T is considered to be promising in that the band gap can be continuously changed by using the properties of the total solid solution of Si and Ge and the effect of strain, and much research has been conducted. Hereinafter, the conventional H will be described with reference to FIGS. 4 and 5A to 5H.
A method for manufacturing a BT will be described.

FIG. 4 shows an NP formed by a conventional technique.
FIG. 2 is a cross-sectional view of an HBT that is an N-type bipolar transistor. In the Si substrate 100 whose main surface is the (001) plane,
A retrograde well 101 having a depth of 1 μm and containing an N-type impurity such as phosphorus formed by an epitaxial growth method or an ion implantation method is formed. Si substrate 1
The collector layer 102 of the bipolar transistor is formed in a region near the surface
2, the concentration of the N-type impurity is adjusted to about 1 × 10 ¹⁷ / cm ³ . The element isolation region is formed by the first insulator 10
5 (non-doped polysilicon) and second insulator 106
(A silicon oxide film) and a shallow trench isolation layer 103 embedded with a second insulator 106. The depth of the shallow trench isolation layer 103 is about 0.35
μm, and the depth of the deep trench isolation layer 104 is about 2 μm. Further, a P ⁺ isolation layer 109 doped with an impurity for a channel stopper is formed in a region of the Si substrate 100 below the deep trench isolation layer 104.
Is provided.

A collector layer 1 is provided in a Si substrate 100.
N ⁺ collector lead-out layer 107 for taking the electrode 02
Is provided. This N ⁺ collector extraction layer 107
The collector layer 102 and the collector layer 102 are separated from each other by a shallow trench isolation layer 103 in a region near the surface in the Si substrate 100, and are connected to each other by a retrograde well 101 in a region behind the Si substrate 100.

On the collector layer 102, a thickness of about 30
A first insulating layer 108 made of a CVD oxide film having a thickness of 10 nm is formed.
2 is provided with a collector opening 110 for opening the upper part. Then, the region above the region in the opening of the first insulating layer 108 in the collector layer 102 and the first insulating layer 108
A thickness of about 60 n doped P-type
m of Si _1-x Ge _x layer and a 10 nm-thick Si layer are continuously laminated, and both of them are Si / Si _1-x
Ge _x layer 111 is formed. Then, on the Si layer, C for etching stopper formed in a double ring shape is formed.
A second insulating layer 112 made of a VD oxide film is formed. In addition, phosphorus (P) is placed on a region of the Si / Si _1-x Ge _x layer 111 which is located in the base opening 118 which is an inner opening of the double ring-shaped second insulating layer 112.
Of about 250 nm thick containing a high concentration of P-type impurities such as
⁺ Polysilicon layer 129 is formed, and the polysilicon emitter layer 12 is formed by the N ⁺ polysilicon layer 129.
2 are configured. Further, the Si _1-x Ge _x / Si layer 1
11, a region containing a high concentration of impurities such as boron (B) is formed on a region located at a base bonding opening which is an outer opening of the double ring-shaped second insulating layer 112. 1
A 50 nm P ⁺ polysilicon layer 115 is provided.

[0006] Then, Si_1-xGe_xInner layer of layers
The portion corresponding to the inner side than the outer edge of the ring is the inner base 11.
9 and Si / Si_1-xGe_xInside of layer 111
The portion corresponding to the outside of the outer edge of the ring is the outer base 1
It is 16. Also, P ⁺Also the polysilicon layer 115
It is a part of the external base 116. In addition, Si_{1- x}
Ge_x/ In the Si layer in the Si layer 111, the inner base 1
The portion located directly above 19 is the Si emitter layer 113.
ing. The collector layer 102 of the inner base 119
And a substantial width W1 of a base portion forming a PN junction therebetween.
(Base opening width) is the base opening of the second insulating layer 112.
Specified by section 118. In addition, Si_1-xGe
_x/ Si of Si layer 111_1-xGe_xIn the layer,
About 2 × 10 P-type impurities such as Ron (B)¹⁸/ Cm^ThreeDark
Doping with degrees. Si _1-xGe_x/ Si layer 1
11 includes a polysilicon emitter layer 1
N-type impurities such as phosphorus (P) diffused from the substrate 22
About 1 × 10 in the depth direction²⁰From about 1 × 10¹⁷/ Cm^ThreeMa
Doping with a distribution of Where Si
_1-xGe_x/ Si layer 111_1-xGe_xlayer
And the continuous formation of the Si layer
Keep the interface with the con-emitter layer 122 away from the P / N junction.
To prevent carrier recombination due to interface states and defects
That's why.

On the inner surface of the base opening 118 of the P ⁺ polysilicon layer 115, there is formed a fourth
The insulating layer 120 and the side wall 121 are formed, and the fourth insulating layer 120 and the side wall 121 are formed.
As a result, the P ⁺ polysilicon layer 115 and the polysilicon emitter layer 122 that are part of the external base 116 are electrically insulated from each other and the diffusion of impurities between them is cut off.

As described above, the base opening width W1 is equal to the second opening width W1.
Of the inner ring of the insulating layer 112 of FIG. Also,
The distance W2 between the outer bases, which is the size of the boundary portion of the outer base 116 that contacts the inner base 19, is defined by the outer edge size of the inner ring of the second insulating layer 112. If the distance W2 between the external bases is too large as compared with the width W1 of the base, a problem that the base resistance and the parasitic capacitance are increased is caused. Therefore, the distance W2 between the external bases is preferably as small as possible. The thicknesses of the fourth insulating layer 120 and the sidewall 121 are 30 nm and 100 nm, respectively.
And the width W1 of the base opening 118 is
20 and the thickness of the side wall 121.

The upper surface of the P ⁺ polysilicon layer 115 which is a part of the external base 116 is covered with a third insulating layer 117 made of a CVD oxide film having a thickness of about 30 nm.
The emitter layer 122 and the external base 116 are insulated from each other by the third insulating layer 117. Further, the outer surfaces of the polysilicon emitter layer 122 and the external base 116 are
Each is covered by a side wall 123. Further, on the polysilicon emitter layer 122, the P ⁺ polysilicon layer 115, and the N ⁺ collector extraction layer 107,
A Ti silicide layer 124 is formed, and the contact resistance is reduced by the Ti silicide layer 124.

The entire transistor is formed by an interlayer insulating film 1
25, and the interlayer insulating film 125 has N
⁺ Ti silicide layer 1 on collector lead layer 107, external base 116 and polysilicon emitter layer 122
24 are formed, and W is embedded in each connection hole to form a W blanket 126. Further, on the interlayer insulating film 125, a metal wiring 127 connected to the W blanket 126 is formed.

With such a structure, the external base 116 is provided.
Is composed not only of the Si _1-x Ge _x / Si layer 111 but also of the P ⁺ polysilicon layer 115, so that the base resistance can be reduced and H suitable for a transistor for high-speed operation can be obtained.
A BT structure is obtained.

Next, a conventional manufacturing method for realizing the structure of the HBT shown in FIG. 4 will be described with reference to FIGS.
FIG. 5D is a cross-sectional view showing a conventional manufacturing process for realizing the structure of the HBT shown in FIG.

First, in the step shown in FIG.
1) An N-type silicon single crystal is formed on the surface of the Si substrate 100 by an epitaxial growth method,
By implanting N-type impurity ions at high energy into the substrate 100, an N-type retrograde well 101 having a depth of about 1 μm is formed in the Si substrate 100. Since the region near the surface of the retrograde well 101 becomes the HBT collector layer 102, the N-type impurity concentration in this region is adjusted to about 1 × 10 ¹⁷ / cm ³ . next,
After a shallow trench and a deep trench are formed in the Si substrate 100, they are buried with a first insulator 105 and a second insulator 106, thereby forming a shallow trench isolation layer 103 and a deep trench isolation layer 104.

Next, N-type impurity ions are implanted at a high dose into a region surrounded by the two shallow trenches 103 of the Si substrate 100, and an N ⁺ collector reaching the retrograde well 101 from the surface of the Si substrate 100. The lead layer 107 is formed.

Next, in the step shown in FIG.
Chemical vapor deposition using silicon (TEOS) and oxygen
(CVD method) at a processing temperature of 680 ° C.
Forming a first insulating layer 108 having a thickness of about 30 nm;
The edge layer 108 is patterned by wet etching with hydrofluoric acid or the like.
To form a collector opening 110. Next
The Si substrate 100 exposed in the collector opening 110
Solution with ammonia water and hydrogen peroxide mixed on the surface of
To form a protective oxide film about 1 nm thick
In this state, the entire substrate is subjected to UHV-CVD (Ultra High
 Vacuum Chemical Vapor Deposition)
You. Then, in a UHV-CVD apparatus, a hydrogen atmosphere
By performing heat treatment in air, the protective oxide film on the substrate
Remove. Next, while heating the substrate to 550 ° C.,
(Si_TwoH₆) And germane (GeH _Four) To dopin
Diborane (B_TwoH₆Gas containing UHV-CV
D device and placed on the substrate to a thickness of about 60 nm.
_1-xGe_xForm a layer. At this time, Si_1-xGe_xlayer
In the collector opening 110, that is, the Si substrate
The portion directly in contact with 100 is made of single crystal,
Si_1-xGe_xA portion of the layer above the first insulating layer 108
Is made of polycrystal. Furthermore, Si_1-xGe
_xAfter forming the layer, continuously switch the gas to disilane
By doing, Si_{1- x}Ge_xAbout 10 nm thick on the layer
Are stacked, and Si_1-xGe_xOf Si layer and Si layer
Si film_1-xGe_x/ Si layer 111 is formed. This
At the time of, on the single crystal Si1-xGex of the Si layer
The formed part is composed of single crystal,
The portion formed on the Si1-xGex layer is made of polycrystal.
It is configured. Note that Si_1-xGe_xEpi in the layer
Boron (B) was introduced during the tax growth
And Si_1-xGe_xThe layer is P-type, with boron
The degree is about 2 × 10¹⁸/ Cm^ThreeIt is. Impurities in the Si layer
Not implemented.

Next, in a step shown in FIG. 5C, a 30-nm thick second insulating layer 1 serving as an etch stopper is formed on the entire surface of the substrate.
After the formation of 12, the second insulating layer 112 is formed by photolithography and dry etching into an outer ring outside the base joining opening 114 and a part inside the base joining opening 114. It is patterned into a shape having island portions. At this time, Si _1-x Ge _x /
The lateral dimension corresponding to the diameter of the island portion of the Si layer 111 is the distance W2 between the external bases. The collector opening 110 is formed only on the active region without including the shallow trench isolation layer 103 in order to eliminate the effect of junction leak caused by stress at the end of the shallow trench isolation layer 103.

Next, in the step shown in FIG. 5D, a P ⁺ polysilicon layer 115 having a thickness of 150 nm into which a high-concentration P-type impurity of 1 × 10 ²⁰ / cm ³ or more is introduced by a CVD method. Subsequently, a third insulating layer 117 having a thickness of about 100 nm is deposited on the P ⁺ polysilicon layer 115. Next, the third insulating layer 117 and the P ⁺ polysilicon layer 11 are subjected to photolithography and dry etching.
5, a base opening 118 reaching the island of the second insulating layer 112 is formed. In a general process, at this time, the third insulating layer 117 and the P ⁺ polysilicon layer 115 are formed.
Is also formed. Here, the P ⁺ polysilicon layer 1
The left portion of FIG. 15 in FIG. 5D is provided wider than the right portion for making contact later.

Next, in a step shown in FIG. 5E, a fourth insulating layer 120 having a thickness of 30 nm and a nitride film for the side wall are deposited on the entire surface of the substrate. Dry etching of the nitride film is performed to form sidewalls 121 on the side surfaces of the third insulating layer 117 and the P ⁺ polysilicon layer 115. Next, wet etching of the oxide film with hydrofluoric acid or the like is performed to remove a portion of the second insulating layer 112 that is exposed at the bottom surface of the base opening 118, and the Si _1-x Ge _x / Si layer 111 The upper Si layer is exposed. At this time, the base opening width W1 is determined by the amount of etching of the oxide film. If the distance W2 between the external bases, which is the external dimension of the second insulating layer 112, is too large than the base opening width W1, the base resistance and the parasitic capacitance increase, which undesirably affects the element characteristics.

Next, in the step shown in FIG.
After depositing nm of N ⁺ polysilicon film, by patterning the N ⁺ polysilicon film by dry etching to form a polysilicon emitter layer 122.

Next, in the step shown in FIG.
dry etching after depositing oxide film for sidewall
To form a polysilicon emitter layer 122 and P⁺Po
A sidewall 123 is formed on the side surface of the silicon layer 115.
Form. At this time, dry etching
Silicon emitter layer 122, external base 116 and N ⁺
The surface of the collector extraction layer 107 is exposed.

Next, in a step shown in FIG. 5H, a Ti film having a thickness of about 40 nm is deposited on the substrate by sputtering.
RTA is performed at 5 ° C. for 30 seconds to react Ti and silicon to form a Ti silicide layer. Thereafter, by removing the unreacted Ti film, the polysilicon emitter layer 122 and the P ⁺ polysilicon layer 11 are removed.
5 (part of the external base layer 116) and the N ⁺ collector extraction layer 107, a Ti silicide layer 124 is formed. Next, an interlayer insulating film 125 is deposited on the substrate, and the polysilicon emitter layer 122, the P ⁺ polysilicon layer 115, and the N ⁺ collector extraction layer 107 are formed on the interlayer insulating film 125.
After forming a contact hole reaching each Ti silicide layer 124 above the contact hole, W is embedded in the contact hole to form a W blanket 12.
6 is assumed. Further, a metal film is formed on the interlayer insulating film 125 and then patterned to form a W blanket 1
The metal wiring 127 connected to 26 is formed.

By using the above configuration and process, an emitter made of N-type Si and a P-type Si _1-x Ge
_x, and a hetero-bipolar transistor (HB
T) is formed.

[0023]

However, the above-mentioned conventional HBT-related technology has the following disadvantages.

In the HBT according to the prior art, the distance W2 between external bases is defined by patterning the second insulating layer 112 by photolithography and dry etching, and then the width of the base opening is separately determined by photolithography and dry etching. Since the opening for defining W1 is formed, the base opening width W with respect to the distance W2 between the external bases is taken into account in consideration of the positional deviation of the mask.
It is necessary to set the dimension 1 in consideration of a margin of about 0.1 μm or more. Therefore, the distance between the emitter-base junction and the boundary between the external base and the internal base (W2-
W1) / 2 increases, and the extra base resistance and parasitic capacitance increase. The increase in the base resistance and the parasitic capacitance is a serious problem in an HBT that needs to operate at a high frequency.

An object of the present invention is to form an emitter / base junction and an external / internal base junction very close to each other without being restricted by optical alignment accuracy, and as a result, to reduce base resistance and parasitic capacitance. An object of the present invention is to provide a small HBT and a manufacturing method thereof.

[0026]

According to the present invention, there is provided a semiconductor device comprising:
The first functioning as a collector of a bipolar transistor
A second semiconductor layer provided on the first semiconductor layer of the substrate and functioning as a base of the bipolar transistor; and a bipolar transistor provided on the second semiconductor layer. A third semiconductor layer functioning as an emitter of the transistor, an emitter conductor layer provided on the third semiconductor layer and functioning as an emitter electrode of a bipolar transistor, and an emitter conductor layer provided on the third semiconductor layer. Is provided in contact with the side of
An inner side wall extending in a vertical direction and an outer side extending in a curved shape; an insulator sidewall for defining a lateral dimension of the emitter-base junction; and an insulator side wall on the third semiconductor layer. A base conductor layer provided outside the wall and functioning as an external base of the bipolar transistor; and an insulator layer provided to be connected to the insulator sidewall and insulating the emitter conductor layer and the base conductor layer. Have.

Thus, the distance between the emitter / base junction and the base conductor layer (external base) is determined by the thickness of the sidewall, so that a margin for masking the two is not required. Therefore, miniaturization of the transistor and reduction of the base resistance can be achieved.

In the above semiconductor device, the base conductor layer is made of silicon formed by epitaxial growth, and (11) is formed on the inner side surface of the base conductor layer.
1) Since the facet is formed and the insulator layer is also interposed in the gap between the insulator sidewall and the base conductor layer, the emitter conductor layer and the base conductor layer are separated by the thick insulator layer. Therefore, the parasitic capacitance is reduced, and the operation speed of the transistor is further improved.

In the semiconductor device, the base resistance is further reduced by further providing an impurity diffusion region formed on both sides of the first semiconductor layer in the substrate and functioning as an external base of the bipolar transistor. become.

In the above semiconductor device, the substrate is made of Si
The first semiconductor layer is a Si layer, and the second semiconductor layer is
Semiconductor layer Si _1-xy of Ge _x C _y layer (1> x, y ≧
0) and the third semiconductor layer is a Si layer, whereby a hetero bipolar transistor having a base bandgap smaller than the band gaps of the emitter and collector can be obtained, and a bipolar transistor having excellent current amplification characteristics and the like can be obtained. Can be

According to the method of manufacturing a semiconductor device of the present invention, there is provided a step (a) of preparing a substrate having a first semiconductor layer serving as a collector of a bipolar transistor, and forming a base of the bipolar transistor on the first semiconductor layer. Forming a second semiconductor layer (b), and forming a third semiconductor layer on the second semiconductor layer as an emitter of a bipolar transistor.
(C) forming a semiconductor layer, and forming a junction width defining insulating layer having a width corresponding to a lateral dimension of an emitter-base junction of the bipolar transistor on the third semiconductor layer. A step (d), a step (e) of forming, on both side surfaces of the junction width defining insulating layer, an insulator sidewall which can be selectively etched with the junction width defining insulating layer; A step (f) of forming a first conductor layer that becomes a part of an external base of the bipolar transistor on the semiconductor layer; and selecting the junction width defining insulating layer on the first conductor layer. Step (g) of forming an inter-electrode insulating layer which can be etched, and forming an opening surrounded by the sidewall by removing a part of the inter-electrode insulating layer and the insulating layer for defining the junction width. (H) performing the opening It embeds a conductive material portion, and a step (i) forming a second conductive layer serving as the emitter electrode of the bipolar transistor.

According to this method, after the sidewall is removed in the step (g), a second conductor layer serving as an emitter electrode is formed in the step (i). The lateral dimensions of the base joint are defined. Therefore, since the lateral dimension of the emitter-base junction and the distance between the external bases are determined by self-alignment, a semiconductor device functioning as a bipolar transistor having the above-described effects can be easily formed.

In the method of manufacturing a semiconductor device, in the step (f), (11) is formed by selective epitaxial growth.
1) By forming a first conductor layer made of silicon doped with impurities and having a facet on a side surface, the first conductor layer is formed.
A gap is formed between the first conductive layer and the sidewall, and the inter-electrode insulating layer is buried in the gap, so that the first conductive layer and the second conductive layer sandwich the thick insulating layer, and the parasitic capacitance is increased. Thus, a transistor having a small operating speed and a high operation speed is formed.

In the method of manufacturing a semiconductor device, in the step (d), a capacitance-reducing insulating layer that can be selectively etched from the insulating layer for defining the junction width is formed on the insulating layer for defining the junction width. In the step (e), the insulator sidewall is formed on each side surface of the junction width defining insulating layer and the capacitance reducing insulating layer. In the step (h), the insulating layer for the capacitance reducing is formed. After removing the part except the end,
By removing the insulating layer for defining the junction width, the first conductive layer and the second conductive layer sandwich the thicker insulating layer, so that a transistor with a higher operation speed is formed.

In the method of manufacturing a semiconductor device, the step of removing the insulating layer for defining the junction width is performed by wet etching, so that the wet etching is an isotropic etching. The insulating layer can be reliably removed.

In the method of manufacturing a semiconductor device, a step of forming an element isolation layer surrounding the semiconductor device formation region on the substrate, and at least the first step after the step (d) and before the step (f). Forming a junction leak prevention layer at the end of isolation between elements by introducing an impurity into the semiconductor layer by an ion implantation method, whereby a bipolar transistor having a smaller base resistance is formed.

In the method of manufacturing a semiconductor device, in the step (a), the first substrate made of a Si layer is used as the substrate.
Preparing a Si substrate having a semiconductor layer of step (b);
Then, the second semiconductor layer made of Si _1-xy Ge _x C _y (1> x, y ≧ 0) is formed. In the step (c),
By forming a third semiconductor layer made of a Si layer,
A semiconductor device functioning as a hetero bipolar transistor is formed.

In the method of manufacturing a semiconductor device, in the step (d), the junction width defining insulating layer is formed from a silicon oxide film, and in the step (e), the insulating sidewall is formed from a silicon nitride film. In the step (g), the inter-electrode insulating layer is formed from a silicon nitride film. In the step (h), a part of the inter-electrode insulating layer is removed by anisotropic dry etching. By removing the insulating layer for defining the junction width by wet etching with an acid, a process suitable for a Si-based heterobipolar transistor is obtained.

[0039]

(First Embodiment) FIG. 1 is a sectional view showing a structure of a hetero bipolar transistor (HBT) according to a first embodiment of the present invention.

As shown in FIG. 1, a 1 μm deep retrograde containing an N-type impurity such as phosphorus formed by an epitaxial growth method or an ion implantation method is provided in a Si substrate 10 having a (001) main surface. A well 11 is formed. A collector layer 12 of a bipolar transistor is formed in a region near the surface of the Si substrate 10.
The concentration of the N-type impurity in this collector layer 12 is 1 × 1
It is adjusted to about 0 ¹⁷ / cm ³ . The element isolation region is
A first insulator 15 (non-doped polysilicon) and a second insulator
And a shallow trench isolation layer 13 in which the second insulator 16 is embedded. The depth of the shallow trench isolation layer 13 is about 0.35
μm, and the depth of the deep trench isolation layer 14 is about 2
μm. In a region of the Si substrate 10 below the deep trench isolation layer 14, a P ⁺ isolation layer 27 doped with an impurity for a channel stopper is provided.

The collector layer 12 is formed in the Si substrate 10.
An N ⁺ collector lead-out layer 17 for taking the above electrode is provided. The N ⁺ collector extraction layer 17 and the collector layer 12 are separated from each other by a shallow trench isolation layer 13 in a region near the surface in the Si substrate 10, and are separated from each other by a retrograde well 11 in a region behind the Si substrate 10. It is connected.

On the collector layer 12, a thickness of about 30 n
m first insulating layer 18 is formed, and the first insulating layer 18 is provided with a collector opening 20 for opening above the collector layer 12. Then, over the collector layer 12 and the first insulating layer 18, a P ₁ -doped Si _1-x Ge _x layer having a thickness of about 60 nm,
A 10-nm-thick Si layer doped in a mold is continuously laminated, and both constitute a Si _1-x Ge _x / Si layer 21. The portion of the Si _1-x Ge _x / Si layer 21 grown from the surface of the Si substrate 10 has a single crystal structure, while the portion grown from the surface of the first insulating layer 18 has a polycrystalline structure. Have.

On the central portion of the Si _1-x Ge _x / Si layer 21, a polysilicon emitter layer 30 made of polysilicon doped with a high concentration of N-type impurity (for example, phosphorus (P)) is provided. Is provided. A first sidewall 24 made of a silicon nitride film is provided so as to surround the side surface of the polysilicon emitter layer 30. Further, high-concentration P-type impurities (for example, boron (B)) are formed so as to surround first sidewall 21.
A doped P ⁺ Si layer 25 is provided. Between the upper end of the first sidewall 24 and the polysilicon emitter layer 30, a third silicon nitride
A fourth insulating layer 26 made of silicon nitride is interposed between the first sidewall 24, the regrown P ⁺ Si layer 25, and the polysilicon emitter layer 30.

Here, the regrowth P⁺The Si layer 25 is made of Si
_1-xGe_x/ Si layer 21 has a single crystal structure
The portion grown from the surface of has a single crystal structure,
Si_{1- x}Ge_x/ Si layer 21 has polycrystalline structure
The part grown from the surface of the part has a polycrystalline structure
You. And regrowth P⁺Single crystal structure of Si layer 25
In the portion having_1-xGe_x/ Si layer 21 and
And extend from a lower end portion in contact with the first sidewall 24.
The sides are (111) facet 33 and (311) facet.
And a socket 34. That is, the Si single crystal
When growing epitaxially, the crystal plane that grows preferentially
First (111) plane and then change to (311) plane
From, regrowth P⁺The elevation angle is 55 ° on the side surface of the Si layer 25.
(111) facet 33 and (311) facet 3
4 are sequentially formed.

The Si emitter layer 23 located below the base opening 28 has a polysilicon emitter layer 30.
The Si emitter layer 23 functions as an emitter of the NPN hetero-bipolar transistor by doping with a high concentration of N-type impurities by diffusion from the N-type impurity. On the other hand, Si
Of the Si _1-x Ge _x layers in the _1-x Ge _x / Si layer 21,
A portion inside the portion located immediately below the first sidewall 24 is an internal base 29 (also called an intrinsic base) of the NPN hetero bipolar transistor. Further, a portion of the Si _1-x Ge _x / Si layer 21 located outside the first sidewall 24 and the regrown P ⁺
The Si layer 25 is the external base 19 of the NPN hetero bipolar transistor. Also, the junction leak prevention layer 22
Also function as an external base.

A first feature of the NPN hetero bipolar transistor (HBT) according to the present embodiment is that the base opening width W1 and the distance W2 between the external bases are both defined by the first sidewall 24. is there. In other words, the internal base 29 and the external base 19 are formed in a self-aligned manner, and the distance (W2−W1) / 2 between the emitter / base junction and the external base / internal base boundary is equal to the first sidewall 24. (Horizontal dimension at the lower end). Since the thickness of the first side wall 24 can be sufficiently set to about 10-20 nm, the distance (W2-W1) / 2 between the emitter-base junction and the boundary between the external base and the internal base. As compared with the structure of the conventional hetero-bipolar transistor, which needs to expect a margin of 0.1 μm, the base resistance and the element size can be greatly reduced. In the present embodiment, since the junction leak preventing layer 22 is provided, even if the collector opening 20 is opened including a part on the shallow trench isolation layer 13, the junction leak due to stress is prevented. It is not affected.

The second feature of the HBT of the present embodiment
Is the regrowth P which accounts for the central part of the external base 19⁺S
The inner side surface of the i-layer 25 is along the first sidewall 24.
Rather than extending from the first sidewall 24
Away (111) facet 33 and (311) facet
This is the point that extends while forming the socket 34. Regrowth P
⁺Since the Si layer 25 has such a structure, the first
Sidewall 24 and regrowth P⁺Between the Si layer 25
The fourth insulating layer 26 may be interposed in the formed gap.
Will be possible. As a result, the polysilicon emitter layer 30
The first side wall 24 and the space between the external base 19
Separated by two insulators, a fourth insulating layer 26
Therefore, although small in size, low parasitic resistance, high speed
An HBT that performs an operation can be realized.

Next, the manufacturing process of the HBT according to the present embodiment will be described with reference to FIGS. 2A to 2K. FIG. 2A
FIG. 2K is a cross-sectional view showing a manufacturing step of the HBT in the present embodiment.

First, in the step shown in FIG.
1) An N-type silicon single crystal is formed on the surface of the Si substrate 10 by an epitaxial growth method, or N-type impurity ions are implanted into the Si substrate 10 at a high energy so that the Si substrate 10 has a depth of about 1 μm. N-type retrograde well 11 is formed. Since the region near the surface of the retrograde well 11 becomes the HBT collector layer 12, the N-type impurity concentration in this region is 1 × 10
It is adjusted to about ¹⁷ / cm ³ . Next, the Si substrate 10
After forming shallow trench and deep trench in
By embedding them with a first insulator 15 and a second insulator 16, a shallow trench isolation layer 13 and a deep trench isolation layer 14 are formed.

Next, N-type impurity ions are implanted at a high dose into a region surrounded by the two shallow trenches 13 of the Si substrate 10, and an N ⁺ collector reaching the retrograde well 11 from the surface of the Si substrate 10. The lead layer 17 is formed.

Next, in the step shown in FIG. 2B, a 30-nm-thick film having a thickness of about 30 nm is formed on the substrate at a processing temperature of 680 ° C. by a chemical vapor deposition method (CVD method) using tetraethoxysilane (TEOS) and oxygen. The first insulating layer 18 is formed, and the first insulating layer 18 is patterned by wet etching such as hydrofluoric acid to form the collector opening 20.

Next, the S exposed in the collector opening 20 is
The surface of the i-substrate 10 is mixed with aqueous ammonia and aqueous hydrogen peroxide.
Approximately 1nm thick protection by treatment with combined chemicals
With the oxide film formed, the whole substrate is UHV-CVD
(Ultra High Vacuum Chemical Vapor Deposition)
To the device. After that, place in UHV-CVD equipment.
By performing heat treatment in a hydrogen atmosphere,
The protective oxide film is removed. Next, heat the substrate to 550 ° C.
While disilane (Si_TwoH₆) And germane (Ge
H_Four) Is replaced by diborane (B_TwoH₆)
Is introduced into the UHV-CVD apparatus, and a thickness of about
60nm Si_1-xGe_xForm a layer. At this time, S
i_1-xGe_xA portion of the layer within the collector opening 20;
The part growing from the surface of the Si substrate 10 has a single crystal structure.
But Si_1-xGe_xFirst insulating layer of layers
The portion growing from the surface of 18 has a polycrystalline structure.
You. Si_1-xGe_xAfter forming the layer, the gas is continuously exhausted.
By switching to silane, Si _1-xGe_xOn the layer
A Si layer having a thickness of about 10 nm_1-xGe_xlayer
And Si which is a laminated film of Si layer_1-xGe_x/ Si layer 21
To form At this time, of the Si layer,_1-xGe_x
The portion formed on the portion having the single crystal structure of the layer is a single
Having a crystal structure, Si_1-xGe_xHas a polycrystalline structure of layers
The part formed on the upper part has a polycrystalline structure.
You. Note that Si_1-xGe_xEpitaxial growth in layers
Since boron (B) is sometimes introduced, Si_1-xGe
_xThe layer is P-type and the concentration of boron is about 2 × 10¹⁸
/ Cm^ThreeIt is. No impurities are introduced into the Si layer
No. In the present embodiment, the base running of the carrier is performed.
In order to increase the line speed,_1-xGe_xEpitaxy layer
When growing silicon, disilane (Si_TwoH₆) And gel
Man (GeH_Four) And the mixing ratio is continuously changed,
Si_{1- x}Ge_xThe Ge content is the highest at the lower end of the layer.
In the upper end, the gradient composition base is such that the Ge content becomes zero.
The base layer is formed.

Next, in the step shown in FIG. 2C, after a silicon oxide film having a film thickness of 100 nm and a silicon nitride film having a film thickness of 10 nm are successively deposited on the entire surface, photolithography and dry etching are performed. Patterning the silicon nitride film and the silicon oxide film,
The second insulating layer 4 has a lateral dimension equal to the base opening width W1.
First and third insulating layers 42 are formed.

Next, in the step shown in FIG. 2D, after a silicon nitride film having a thickness of about 100 nm is deposited on the substrate, the silicon nitride film is etched back, so that the second insulating layer 41 and the third insulating layer 41 are formed. The first sidewall 24 is formed on the side surface of the insulating layer 42.

Here, the width (W2-W1) / 2 (lateral dimension at the lower end) of the first side wall 24 can be made very small between about 10 nm.

Further, in order to suppress the influence of stress on the active region / separation junction, the mask used for forming the second insulating layer 41 and the third insulating layer 42 is used, and boron (B) is self-aligned as it is. P-type impurities are ion-implanted to form a P ⁺ -type junction leak prevention layer 22 having a concentration near the surface of about 3 × 10 ¹⁷ / cm ³ . However, before forming the first sidewall 24, ion implantation for forming the junction leak prevention layer 22 may be performed.

Next, Si_1-xGe_x/ Grows Si layer 21
After forming a protective oxide film, UHV-
Introduced into CVD equipment and maintained by heat treatment in hydrogen atmosphere
After removing the protective oxide film, disilane (Si_TwoH₆) And do
Diborane for ping (B_TwoH ₆) Containing gas,
Si_1-xGe_x/ Si layer in Si layer 21 as growth nucleus
Epitaxial growth and doping to P type with high concentration
500 nm thick regrown P⁺Form Si layer 25
I do. Regrowth P⁺The Si layer 25 is made of Si_1-xGe _x/ Si
Above the portion of layer 21 located directly above collector layer 12
Has a single-crystal structure and is located above the first insulating layer 18.
Has a polycrystalline structure on the part
You. The single crystal regrowth P⁺The impurity concentration of the Si layer 25
1 × 10²⁰/ Cm^ThreeTo achieve a higher concentration, regrowth P
⁺Impurity is further diffused into the Si
For example, ion implantation can be performed.

At this time, a (111) facet 33 and a (311) facet 34 appear on the inner side surface of the regrown P ⁺ Si layer 25. That is, the regrown P ⁺ Si layer 2
5 does not grow along the side surface of the first sidewall 24, but the regrown P ⁺ Si layer 25 grows so as to be inclined away from the first sidewall 24 as going upward. If a growth condition in which a (111) facet 33 having a large angle formed by the regrown P ⁺ Si layer 25 and the substrate surface is used, the change in film thickness can be made sharper, so that the base resistance and the The effect of reducing the parasitic capacitance can be further increased.

Further, in a step shown in FIG. 2F, a fourth insulating layer 26 made of silicon nitride and having a thickness of about 30 nm is formed on the entire surface of the substrate, and a resist mask Prm is formed on the fourth insulating layer 26. I do. In a portion of the resist mask Prm located immediately above the third insulating layer 42, an opening having a size that is within the lateral dimension W1 of the second insulating layer 41 or the third insulating layer 42 is formed. ing.

Next, in the step shown in FIG. 2G, the fourth insulating layer 26 and the third insulating layer 42 are dry-etched using the resist mask Prm and the second insulating layer 41 as an etch stopper. The base opening 28 is formed in the third insulating layer 42. At this time, the fourth insulating layer 26 and the third insulating layer 42 are made of silicon nitride, and the second insulating layer 41 is made of silicon oxide.
During dry etching, a large etching selectivity is obtained between the third insulating layer 42 and the second insulating layer 41.

Next, in the step shown in FIG. 2H, after removing the resist mask Prm, the second insulating layer 42 made of silicon oxide is removed by wet etching with hydrofluoric acid. At this time, since the Si layer forming the upper part of the Si _1-x Ge _x / Si layer 21 and the first sidewall 24 made of silicon nitride have a small etching rate with respect to hydrofluoric acid, an effective etch stopper Becomes In addition,
According to wet etching, the entire second insulating layer 41 can be removed without forming damage such as defects on the surface of the Si _1-x Ge _x / Si layer 21. At this time, the first side wall 24 functions as an etch stopper and at the same time plays a role of insulating the polysilicon emitter and the external base together with the fourth insulating layer 26.

Next, in a step shown in FIG. 2I, a polysilicon doped with a high concentration of N-type is buried in the base opening 28, and then the polysilicon film is patterned to form a polysilicon emitter layer 30. I do. After that, high concentration impurities are diffused from the polysilicon emitter layer 30 into the Si emitter layer 23. Thereby, N type S
A hetero bipolar transistor (HBT) having an emitter composed of an i-layer, a base composed of a P-type SiGe layer, and a collector composed of an N-type Si layer is formed.

Next, in the step shown in FIG. 2J, the fourth insulating layer
26, Regrowth P⁺Si layer 25, Si _1-xGe_x/ Si layer
After patterning 21 and first insulating layer 18, the substrate
A 120 nm thick CVD oxide film for sidewalls
accumulate. Then, etch back this
Con-emitter layer 30 and regrown P⁺Si layer 25 and Si
_1-xGe_x/ Second side wall on the side surface of Si layer 21
Forming a screw 30. Dry etching at this time
And the polysilicon emitter layer 30 and the regrown P⁺Si layer 2
5, Si_1-xGe_x/ Si layer 21 and N⁺Collector pull
The surface of the exposed layer 17 is exposed.

Next, in a step shown in FIG. 2K, a Ti film having a thickness of about 40 nm is deposited on the substrate by sputtering.
RTA is performed at 5 ° C. for 30 seconds to react Ti and silicon to form a Ti silicide layer. Thereafter, by removing the unreacted Ti film, the polysilicon emitter layer 122 and the regrown P ⁺ Si layer 25 are removed.
A Ti silicide layer 32 is formed on (part of the external base layer 19) and the N ⁺ collector extraction layer 17. next,
An interlayer insulating film 35 is deposited on the substrate, and the interlayer insulating film 35 is
After forming connection holes reaching the Ti silicide layers 34 on the polysilicon emitter layer 30, the regrown P ⁺ Si layer 25, and the N ⁺ collector extraction layer 17, W is buried in the connection holes to form a W blanket 36. . Further, a metal film is formed on the interlayer insulating film 35 and then patterned to form a metal wiring 37 connected to the W blanket 36.

According to the method of manufacturing the HBT of this embodiment,
It can be seen that the structure of the HBT shown in FIG. 1 can be easily realized.

(Second Embodiment) In the first embodiment,
In this case, the member serving as the center of the external base 19 is regrown P
⁺The structure of the HBT of the present invention, which was constituted by the Si layer 25
Is not limited to such an embodiment. Second fruit
In the embodiment, the member serving as the center of the external base is made of poly.
An HBT made of silicon will be described.

In this embodiment, the same steps as those shown in FIGS. 2A to 2D in the first embodiment are performed.

Then, instead of the step shown in FIG. 2A, as shown in FIG. 3A, a P ⁺ polysilicon layer 43 doped with a high concentration of P-type impurities is deposited on the entire surface of the substrate.

Next, in the step shown in FIG. 3B, the entire surface of the substrate is polished by CMP (Chemical Mechanical Polishing) until at least the first sidewall 24 is exposed, and the entire substrate is flattened. Thereafter, a fourth insulating layer 26 of silicon nitride having a thickness of about 30 nm is deposited on the entire surface of the substrate, and then a resist mask Prm is formed on the fourth insulating layer 26. This resist mask Prm
Of the second insulating layer 41 and the third insulating layer 42 in the horizontal direction W1 are located directly above the third insulating layer 42.
An opening sized to fit inside is formed.

Next, in the step shown in FIG. 3C, dry etching of the fourth insulating layer 26 and the third insulating layer 42 is performed using the resist mask Prm and the second insulating layer 41 as an etch stopper. The base opening 28 is formed in the third insulating layer 42. At this time, the fourth insulating layer 26 and the third insulating layer 26 are made of silicon nitride, and the second insulating layer 41 is made of silicon oxide.
During dry etching, a large etching selectivity is obtained between the third insulating layer 42 and the second insulating layer 41. Further, after removing the resist mask Prm, the second insulating layer 42 made of silicon oxide is removed by wet etching with hydrofluoric acid. At this time, Si _1-x G
Since the Si layer forming the upper part of the _ex / Si layer 21 and the first sidewall 24 made of silicon nitride have a small etching rate with respect to hydrofluoric acid, they serve as effective etch stoppers. At this time, the first sidewall 2
4 serves as an etch stopper, and at the same time, the fourth insulating layer 26
In addition, it plays a role of insulating between the emitter and the external base.

Thereafter, FIG. 2I in the first embodiment
By performing the same steps as shown in FIG. 2K, the structure shown in FIG. 3D is obtained.

According to the HBT of this embodiment and its manufacturing method, the distance between the external base 19 (P ⁺ polysilicon layer 43) and the polysilicon emitter layer 30 is smaller than that of the structure of the first embodiment. An HBT that can exhibit substantially the same effects as in the first embodiment can be obtained.

In the first and second embodiments, instead of forming the third insulating layer 42, the thickness of the second insulating layer 41 is increased by the thickness of the third insulating layer. In other words, even if only a silicon oxide film is formed, the same effects as those of the above embodiments can be exerted.

The material of the first to fourth insulating layers is not limited in each of the above embodiments. In particular, the material of the second insulating layer 41 may be any material as long as an etching selectivity with the first sidewall 24 and the fourth insulating layer 26 can be secured.

Further, in each of the above embodiments, the internal base is constituted by the SiGe layer. However, the present invention is not limited to this embodiment, and the internal base is made of SiGe.
You may comprise by eC layer or SiC layer. That is, the internal base of the composition, generally Si _1-xy Ge _x C _y layer (1> x, y ≧ 0 ) as long as it is represented by. If the band gap of the internal base is smaller than the band gap between the emitter and the collector, a function as a hetero-bipolar transistor can be obtained, so that the emitter base may contain Ge and C.

[0076]

According to the semiconductor device of the present invention and the method of manufacturing the same, the structure and the manufacturing method are such that the distance between the emitter / base junction and the external base can be defined by self-alignment with the sidewall interposed therebetween. The base resistance and the parasitic capacitance can be reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a structure of an HBT according to a first embodiment.

FIG. 2A is a cross-sectional view showing a step until a shallow trench isolation layer, a deep trench isolation layer, a collector layer, and the like are formed in the manufacturing process of the HBT according to the first embodiment.

FIG. 2B is a view showing a process of manufacturing an HBT according to the first embodiment;
Of which Si_1-xGe _x/ Si layer is formed
It is sectional drawing which shows a process.

FIG. 2C is a cross-sectional view showing a step of forming a second insulating layer and a third insulating layer in the HBT manufacturing steps according to the first embodiment.

FIG. 2D is a cross-sectional view showing the step of forming the first sidewall on the side surfaces of the second insulating layer and the third insulating layer in the manufacturing process of the HBT according to the first embodiment.

FIG. 2E is a cross-sectional view showing a step of forming a regrown P ⁺ Si layer in the HBT manufacturing steps according to the first embodiment.

FIG. 2F is a cross-sectional view showing a step of forming a fourth insulating layer and the like in the HBT manufacturing steps according to the first embodiment.

FIG. 2G is a cross-sectional view showing the step of forming the base opening in the third insulating layer in the manufacturing steps of the HBT according to the first embodiment.

FIG. 2H is a cross-sectional view showing the step of removing the second insulating layer and forming the base opening in the manufacturing steps of the HBT according to the first embodiment.

FIG. 2I is a cross-sectional view showing a step of embedding a polysilicon emitter layer in a base opening in the manufacturing steps of the HBT according to the first embodiment.

FIG. 2J is a cross-sectional view showing a step of patterning a member serving as an external base in the HBT manufacturing steps according to the first embodiment.

FIG. 2K is a cross-sectional view showing the step of forming the interlayer insulating film, the wiring, and the like, among the steps of manufacturing the HBT according to the first embodiment.

FIG. 3A is a cross-sectional view showing a step of depositing a polysilicon film in an HBT manufacturing step according to the second embodiment.

FIG. 3B is a cross-sectional view illustrating a step of forming a fourth insulating layer and the like in the HBT manufacturing steps according to the second embodiment.

FIG. 3C is a cross-sectional view showing a step of forming a base opening in the HBT manufacturing steps according to the first embodiment.

FIG. 3D is a cross-sectional view showing a step of forming an interlayer insulating film, a wiring, and the like in the HBT manufacturing steps according to the second embodiment.

FIG. 4 is a cross-sectional view showing a structure of a conventional HBT.

FIG. 5A is a cross-sectional view showing a process of forming a shallow trench isolation layer, a deep trench isolation layer, a collector layer, and the like in the HBT manufacturing process in the related art.

FIG. 5B is a diagram showing an example of an HBT manufacturing process according to the prior art;
FIG. 4 is a cross-sectional view showing a step of forming a Si _1-x Ge _x / Si layer on an i-substrate.

FIG. 5C is a cross-sectional view showing a step of forming a second insulating layer in the HBT manufacturing steps in the conventional technique.

FIG. 5D is a view showing a conventional HBT manufacturing process.
FIG. 10 is a cross-sectional view showing a step of forming a base opening in a third insulating layer and a P ⁺ polysilicon layer.

FIG. 5E is a cross-sectional view showing a step of forming a sidewall or the like in a base opening in a manufacturing process of the HBT according to the conventional technique.

FIG. 5F is a cross-sectional view showing a step of embedding a polysilicon emitter in a base opening in an HBT manufacturing process in the conventional technique.

FIG. 5G is a cross-sectional view showing a step of forming a sidewall on a side surface of each electrode in a manufacturing process of the HBT according to the related art.

FIG. 5H is a view showing a conventional HBT manufacturing process.
FIG. 9 is a cross-sectional view showing a step of forming an interlayer insulating film, wiring, and the like.

[Explanation of symbols]

Reference Signs List 10 Si substrate 11 Retrograde well 12 Collector layer 13 Shallow trench isolation layer 14 Deep trench isolation layer 15 First insulator 16 Second insulator 17 N ⁺ collector extraction layer 18 First insulation layer 19 External base 20 Collector opening Part 21 Si _1-x Ge _x / Si layer 22 Junction leak prevention layer 23 Si emitter layer 24 First sidewall 25 Regrown P ⁺ Si layer 26 Fourth insulating layer 27 Isolation P ⁺ layer 28 Base opening 29 Internal base 30 Polysilicon emitter 31 Second sidewall 32 Ti silicide 33 (111) facet 34 (311) facet 35 Interlayer insulating film 36 W blanket 37 Metal wiring 41 Second insulating layer 42 Third insulating layer

Claims (11)

[Claims] A substrate having a first semiconductor layer functioning as a collector of a bipolar transistor; a second semiconductor layer provided on the first semiconductor layer of the substrate and functioning as a base of the bipolar transistor; A third semiconductor layer provided on the second semiconductor layer and functioning as an emitter of the bipolar transistor; and an emitter conductor layer provided on the third semiconductor layer and functioning as an emitter electrode of the bipolar transistor. An inner surface extending vertically and an outer surface extending in a curved shape on the third semiconductor layer to define a lateral dimension of the emitter-base junction; An insulator sidewall for performing the operation; and a third insulator layer provided outside the insulator sidewall on the third semiconductor layer. A base conductor layer that functions as an external base of La transistor provided connected to the insulator sidewalls, a semiconductor device and an insulating layer for insulating the said emitter conductive layer and the base conductor layer. 2. The semiconductor device according to claim 1, wherein the base conductor layer is made of silicon formed by epitaxial growth, and (111) facets are formed on inner side surfaces of the base conductor layer. The semiconductor device, wherein the insulator layer is interposed also in a gap between the insulator sidewall and the base conductor layer. 3. The semiconductor device according to claim 1, further comprising an impurity diffusion region formed on both sides of said first semiconductor layer in said substrate and functioning as an external base of said bipolar transistor. A semiconductor device characterized by the above-mentioned. 4. The semiconductor device according to claim 1, wherein the substrate is a Si substrate, the first semiconductor layer is a Si layer, and the second semiconductor layer is a semiconductor device. Is a Si _1-xy Ge _x C _y layer (1>
x, y ≧ 0), and the third semiconductor layer is a Si layer. 5. A step of preparing a substrate having a first semiconductor layer to be a collector of a bipolar transistor (a).
Forming a second semiconductor layer serving as a base of the bipolar transistor on the first semiconductor layer (b); and forming a third semiconductor serving as an emitter of the bipolar transistor on the second semiconductor layer. Step (c) of forming a semiconductor layer
(D) forming a junction width defining insulating layer having a width corresponding to a lateral dimension of an emitter-base junction of the bipolar transistor on the third semiconductor layer; (E) forming insulator sidewalls that can be selectively etched with the junction width defining insulating layer on both side surfaces of the insulating layer for external use, and forming an external side of the bipolar transistor on the third semiconductor layer. A step (f) of forming a first conductor layer to be a part of a base; and forming an inter-electrode insulation layer on the first conductor layer, which is selectively etchable with the junction width defining insulation layer. (G), forming an opening surrounded by the insulator sidewall by removing a part of the inter-electrode insulating layer and the junction width defining insulating layer; Buried conductor material in opening Crowded in, a method of manufacturing a semiconductor device and a step (i) forming a second conductive layer serving as the emitter electrode of the bipolar transistor. 6. The method of manufacturing a semiconductor device according to claim 5, wherein in the step (f), the first conductor layer made of silicon doped with impurities having a (111) facet on a side surface is formed by selective epitaxial growth. A method for manufacturing a semiconductor device, comprising: 7. The method of manufacturing a semiconductor device according to claim 5, wherein in the step (d), the insulating layer for defining the junction width is
The junction width defining insulating layer is formed with a capacity reducing insulating layer capable of being selectively etched. In the step (e), the insulating layer is provided on each side surface of the junction width defining insulating layer and the capacity reducing insulating layer. Forming a body side wall, and in the step (h), after removing a portion excluding an end of the capacitance reducing insulating layer, removing the junction width defining insulating layer. Production method. 8. The method of manufacturing a semiconductor device according to claim 5, wherein the step of removing the insulating layer for defining the junction width is performed by wet etching. Device manufacturing method. 9. The method of manufacturing a semiconductor device according to claim 5, wherein an element isolation layer surrounding the semiconductor device formation region is formed on the substrate, and at least the step (d). After the step (f) and before the step (f), a step of introducing an impurity into the first semiconductor layer by an ion implantation method to form a junction leak prevention layer at an end of element isolation. A method for manufacturing a semiconductor device, comprising: 10. The method of manufacturing a semiconductor device according to claim 5, wherein in the step (a), a Si substrate having a first semiconductor layer made of a Si layer as the substrate. In the step (b), Si _1-xy Ge _x C _y (1> x,
forming a second semiconductor layer made of y ≧ 0), and forming a third semiconductor layer made of a Si layer in the step (c). 11. The method for manufacturing a semiconductor device according to claim 10, wherein in the step (d), the insulating layer for defining the junction width is formed from a silicon oxide film, and in the step (e), the insulating layer is formed from a silicon nitride film. Forming the insulating sidewall; forming the interelectrode insulating layer from a silicon nitride film in the step (g); and forming a part of the interelectrode insulating layer by anisotropic dry etching in the step (h). Removing the insulating layer by wet etching with hydrofluoric acid.