WO1997011496A1 - Dispositif a semi-conducteur, procede de fabrication associe et systeme utilisant ledit dispositif - Google Patents

Dispositif a semi-conducteur, procede de fabrication associe et systeme utilisant ledit dispositif Download PDF

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Publication number
WO1997011496A1
WO1997011496A1 PCT/JP1995/001844 JP9501844W WO9711496A1 WO 1997011496 A1 WO1997011496 A1 WO 1997011496A1 JP 9501844 W JP9501844 W JP 9501844W WO 9711496 A1 WO9711496 A1 WO 9711496A1
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Prior art keywords
semiconductor
region
semiconductor region
conductivity type
base
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PCT/JP1995/001844
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English (en)
Japanese (ja)
Inventor
Eiji Ooue
Takahiro Onai
Katsuyoshi Washio
Yukihiro Kiyota
Masao Kondo
Katsuya Oda
Toru Masuda
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Hitachi, Ltd.
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Priority to PCT/JP1995/001844 priority Critical patent/WO1997011496A1/fr
Publication of WO1997011496A1 publication Critical patent/WO1997011496A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66287—Silicon vertical transistors with a single crystalline emitter, collector or base including extrinsic, link or graft base formed on the silicon substrate, e.g. by epitaxy, recrystallisation, after insulating device isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors

Definitions

  • the present invention relates to a semiconductor device capable of high-speed operation, particularly to a bipolar transistor, and further relates to a method for manufacturing the semiconductor device, an optical transmission system device using the semiconductor device, and a mobile wireless portable device. . Background art
  • FIG. 2 is a cross-sectional view of a conventional bipolar transistor using a conventional silicon selective epitaxial method disclosed in Japanese Patent Application Laid-Open No. Hei 5-3-1542.
  • reference numeral 201 denotes a p-type silicon substrate
  • 202 denotes an n + -type buried layer
  • 203 denotes an n- -type silicon epitaxial layer
  • 204 denotes a LOCOS oxide film
  • 2 denotes a LOCOS oxide film.
  • 05 is an n + type phosphorus diffusion layer
  • 206 is a silicon nitride film
  • 207 is polycrystalline silicon for a p + type base electrode
  • 208 is polycrystalline silicon for an n + type collector electrode
  • 2 09, 214, 220 are silicon nitride films
  • 210 is an n-type buried layer
  • 211 is a single-crystal silicon collector
  • 211 is a single-crystal silicon intrinsic base layer
  • 2 13 is polycrystalline silicon WO 97/11496
  • the single-crystal silicon intrinsic berth layer 212 is deposited by an epitaxy method on the main surface of the silicon substrate 201 on which the collector region is formed. Disclosure of the invention
  • the amount of side etching of the silicon nitride film 206 is increased to make the base polycrystalline silicon electrode 207 and the polycrystalline silicon graph base 21 1
  • the contact area between the base region 2 12 and the collector low-accuracy layer 203 increases, and the base-collector capacitance increases.
  • the contact area between the base polycrystalline silicon electrode 207 and the polycrystalline silicon graphite base 213 cannot be reduced below a certain area in consideration of the maximum base resistance. Therefore, the content of the base region 211 and the collector region 203 is inevitable! : Cannot be less than a certain value.
  • the conventional technology reduces the base resistance for further high-speed operation, and It is difficult to eliminate the parasitic capacitance i component such as base and collector capacitance.
  • the limitation of the high-speed operation of such a bipolar transistor impedes the high-speed operation of various semiconductor integrated circuit devices using the same, and furthermore, the high-speed operation of a system using the same.
  • the need to compensate for the high-speed operation of Gbps optical communication systems also necessitates an increase in the operating speed of transistors.
  • a typical object of the present invention is to overcome the above-mentioned problems
  • Another object of the present invention is to provide a transistor that operates at high speed with low power consumption by reducing the base / collector capacitance ft.
  • Still another object of the present invention is to provide a manufacturing method capable of realizing the above-described transistor by a relatively simple process.
  • Still another object of the present invention is to provide a system such as an optical transmission system that can operate at high speed with low power consumption by using a semiconductor device that can operate at high speed with low power consumption.
  • an insulating film is inserted under a polycrystalline semiconductor graft base which is a connection portion between a base region and a base polycrystalline silicon electrode. And separate it from the collector region to reduce base / collector junction area.
  • a semiconductor device includes:
  • a second conductive semiconductor region (114); a first conductive third semiconductor region (118) formed in the first semiconductor region; and a first wiring layer The second semiconductor region is formed on the main surface of the first semiconductor region, and the first wiring layer is formed on the main region of the first semiconductor region. It is formed on the first semiconductor region via the insulating film (105) formed on the surface.
  • a semiconductor device includes: A first semiconductor region of the first conductivity type (103); a second semiconductor region of the second conductivity type (1 14) deposited on the main surface of the first semiconductor region; A third semiconductor region of the first conductivity type formed in the semiconductor region of the first conductivity type, and a first insulating film formed on the main surface of the first semiconductor region and having a first opening.
  • a method for manufacturing a semiconductor device includes:
  • a first step (105) of forming a first insulating film on a surface of a semiconductor substrate (103) of a first conductivity type formed on a semiconductor substrate (101), and the first insulating film A second step of forming a second insulating film (107) thereon; a third step of forming a first conductor layer (110) on the second insulating film; A fourth 'step (FIG. 5 (b)) of forming a first opening by etching the first conductor layer and the second insulating film; and forming the second opening through the first opening.
  • a method for manufacturing a semiconductor device includes:
  • a front body in which a first conductor layer (1 06) having a first opening is stacked on a main surface of a single crystal semiconductor substrate (1 03) via a first insulating film (105) And selectively depositing a semiconductor material on the main surface of the semiconductor substrate from the first opening to form a first semiconductor region (114, etc.) and contact with the first conductor layer.
  • the first polycrystalline semiconductor graphite base 113 shown in FIG. Decrease in contact resistance of crystalline semiconductor graft base 113
  • the resistance of the polycrystalline semiconductor graft base 1 13 can be reduced. Therefore, if the sheet resistance of the base slaughter 114 is the same, the base resistance can be reduced as compared with the conventional example.
  • the base collector capacitance in this region is equal to the capacitance of the silicon oxide film 105 and that of the low concentration collector layer 103.
  • Series with! which can be reduced to about 12 or less as compared with the conventional case where only the low concentration collector layer 103 is used.
  • the ratio of the planar projection area of this region to the emitter area increases as the emitter size decreases, and if the low-concentration collector layer 103 is made thinner for the purpose of speeding up, It depends on the invention! : The reduction effect is greatly increased, and the base-collector capacitance can be reduced to about 1 2.
  • the base resistance can be reduced and the base collector capacitance can be reduced, and low power consumption and high speed operation can be achieved.
  • FIG. 1 is a sectional view of a bipolar transistor according to a first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view of a conventional bipolar transistor.
  • Fig. 3 shows the parasite of the present invention! : Diagram showing the effect of extinction.
  • FIG. 4 is a first sectional view showing a manufacturing process of the bipolar transistor according to the first embodiment of the present invention.
  • FIG. 5 is a second sectional view showing the manufacturing process of the bipolar transistor according to the first embodiment of the present invention.
  • FIG. 6 shows a manufacturing process of the bipolar transistor according to the first embodiment of the present invention. Third sectional view.
  • FIG. 7 is a fourth sectional view showing the manufacturing process of the bipolar transistor according to the first embodiment of the present invention.
  • FIG. 8 is a cross-sectional view of a bipolar transistor according to a second embodiment of the present invention.
  • FIG. 9 is a first cross-sectional view showing a manufacturing process of the bipolar transistor according to the third embodiment of the present invention.
  • FIG. 10 is a second sectional view showing the manufacturing process of the bipolar transistor according to the third embodiment of the present invention.
  • FIG. 11 is a third sectional view showing the manufacturing process of the bipolar transistor according to the third embodiment of the present invention.
  • FIG. 12 is a fourth sectional view showing the manufacturing process of the bipolar transistor according to the third embodiment of the present invention.
  • FIG. 13 is a cross-sectional view of a bipolar transistor according to a fourth embodiment of the present invention.
  • FIG. 14 is a first cross-sectional view showing a manufacturing process of the bipolar transistor according to the fifth embodiment of the present invention.
  • FIG. 15 is a second sectional view showing the manufacturing process of the bipolar transistor according to the fifth embodiment of the present invention.
  • FIG. 16 is a third sectional view showing the manufacturing process of the bipolar transistor according to the fifth embodiment of the present invention.
  • FIG. 17 is a front S-width circuit diagram of an optical transmission system according to a sixth embodiment of the present invention.
  • FIG. 18 is a front-end module of an optical transmission system according to a seventh embodiment of the present invention.
  • FIG. 19 is a configuration diagram of an optical transmission system according to an eighth embodiment of the present invention.
  • FIG. 20 is a configuration diagram of an optical transmission system according to an eighth embodiment of the present invention.
  • FIG. 21 is a configuration diagram of a mobile radio portable device according to a ninth embodiment of the present invention.
  • FIG. 22 is a circuit diagram of a D flip-flop according to a tenth embodiment of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 shows a sectional view of a first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view of a bipolar transistor according to the present embodiment, and is a cross-sectional view of a substantially completed stage although a final protective film and the like are omitted.
  • 101 is a p-type silicon substrate of a first conductivity type
  • 102 is an n-type high-concentration collector buried layer of a second conductivity type opposite to the first conductivity type
  • 3 is an n-type low concentration collector layer.
  • the main surface of the collector region becomes the main surface of the semiconductor substrate and is formed in a substantially planar shape. A base region is formed.
  • 104, 105, 106, 111, 116, 119 are insulating films such as silicon oxide films, and 107 is a silicon oxide film which is insulating films.
  • 107 is a silicon oxide film which is insulating films.
  • the material of the insulating film 105 and the insulating film 107 is not limited to the oxide film and the nitride film, and that the material of the cabinet is such that the insulating film 105 has a sufficiently high selectivity to the insulating film 107.
  • An insulating film is sufficient.
  • Reference numeral 110 denotes a base polycrystalline silicon electrode which is an extraction electrode of a base region formed of polycrystalline silicon.
  • the base extraction S pole 110 is formed so as to be connected to the base region from the side surface via the later-described graft base regions 113 and 115.
  • the base extraction electrode is formed on the substrate only through the insulating film 105 in the vicinity of the graft base region 113, but has a tapered shape as the distance from the graft base region 113 increases. Since the insulating film 106 having the inclined surface is formed via the insulating film 106, the structure is such that the distance from the semiconductor substrate gradually increases.
  • the connection with the graph base region can be relatively easily performed in the vicinity of the graph base, and the distance from the semiconductor base 103 to the other portions is relatively small. And the parasitic capacitance between the lead electrode 106 and the semiconductor substrate 103! : Can be eliminated.
  • Reference numeral 113 denotes a first polycrystalline semiconductor graft base that electrically connects the intrinsic base region 114 and the base extraction electrode 110.
  • the first graph base region is connected to the base extraction electrode 110 on the upper surface
  • the collector region 103 is connected to the base region through the silicon oxide 105 which is an insulating film on the lower surface.
  • Semiconductor substrate to be formed Is in contact with Further, one of the side surfaces is formed in contact with a second graft base region which is electrically connected to the base region 114, which will be described later, and the other is formed in contact with the silicon nitride layer 107.
  • the base region 114 and the emitter region 118 are formed with a distance also in the depth direction of the drawing, and have a rectangular shape with rounded corners. Is formed.
  • the graph base areas 1 13 and 1 15 are shaped to surround the base castles 114.
  • the base extraction electrode 110 also surrounds the base region, and is configured to be connected to the base region 114 via the graft base region.
  • Reference numeral 114 denotes a single-crystal semiconductor base layer, which is formed in the present embodiment in such a manner that it does not overlap with the base extraction electrode as described above.
  • the base region 114 can be made of a silicon single crystal, and can also be made of a so-called silicon germanium using a mixed material of silicon and germanium. is there. Generally, a single crystal with few crystal defects can be easily formed when formed only with silicon, and the characteristics of a transistor can be improved when silicon germanium is used.
  • Reference numeral 115 denotes a second polycrystalline semiconductor substrate which electrically connects the base layer 114 and the base lead electrode 110 to each other, and has a contact area with the base region 114.
  • the semiconductor substrate is configured to be obliquely in contact with the main surface of the semiconductor substrate.
  • the side surface of the base region is configured to have the (111) plane with respect to the semiconductor substrate 103 having the (100) plane.
  • Reference numeral 117 denotes an emitter polycrystalline silicon electrode
  • reference numeral 118 denotes an emitter region.
  • the connection between the base lead-out electrode 110 and the epitaxial base region 114 does not come into contact with the collector region 103, and the side surface of the base region 114 does not come into contact with the collector region 103. Is being read from. Therefore, it is not necessary to increase the size of the base region, which was required in the past, in a planar manner for connection with the extraction electrode, and the base region can be formed with a minimum size for performing selective epitaxial growth. Base ⁇ Collector capacity can be reduced.
  • the graft base region 113 connecting the base extraction electrode 110 and the epi base region 114 is formed on the main surface of the semiconductor substrate forming the collector region. o is arranged via 5 g. Therefore, draw out the base
  • the volume formed between the source region and the collector region! Can also be reduced.
  • the parasitic capacitance ft between the base and the collector can be reduced, and a sufficient contact area can be secured by connecting the base region and the extraction electrode from the side. Elimination of resistance can also be achieved.
  • the base region is formed by selective epitaxial growth, so that the effects of the above-described embodiment and the effects of selective epitaxial growth are combined, so that higher speed operation and lower power consumption can be achieved. Things.
  • the horizontal axis represents the thickness d e P i of the low concentration collector layer (103 in FIG. 1 and 203 in FIG. 2), and the vertical axis represents the base-collector according to the above embodiment.
  • Peripheral volume between SCTC and conventional base collector! It is the ratio with CTC.
  • the peripheral volume ft between the base and collector in the conventional example is formed by the base region 2 12 immediately below the graph base region 2 13, the low-concentration collector region 203 and the high-concentration collector region 202 It is i. This can be considered as a parasitic capacitance using the base region 211 and the high concentration collector region 202 as electrodes because the low concentration collector region 203 is depleted.
  • the base-collector peripheral volume i CTC has a graft base region because the insulating film 105 is interposed between the graphite base 113 and the collector low-concentration layer 103.
  • the parasitic capacitance Jt using the electrodes 113 and the high-concentration collector layer 102 as both electrodes can be considered.
  • Fig. 3 shows the case where the WE of the emitter in the emitter region is 0.1, 0.2, and 0.4 (where the value of 1 ⁇ (is in the range of 0.05 m to 0.15 ⁇ ). The data up to is shown.
  • the value of the CTC according to the present embodiment divided by the value of the CTC according to the conventional example is less than 1 in all cases. It can be seen that the capacitance between the base and the collector has decreased. In particular, as the emitter width, for example, the emitter WE, becomes smaller, the graph becomes lower in the figure, indicating that the effect of this embodiment becomes more remarkable as the size becomes smaller. I have.
  • FIGS. 4 to 7 show a manufacturing method of the first embodiment of the present invention.
  • a high-concentration n-type collector buried layer 102 is formed on a silicon substrate 101 by thermal diffusion, and then a low-concentration n-type collector is formed by silicon epitaxial growth.
  • the layer 103 is formed.
  • the low-concentration collector layer 103 is formed in the shape of a semiconductor substrate, becomes a base portion of an element, and has a substantially planar surface.
  • a trench having a depth of 3 / m is formed by dry etching so as to surround the periphery of the high-concentration n-type collector buried layer 102 on the plane, and the silicon oxide film 104 is buried.
  • a low concentration n-type collector layer 103 is thermally oxidized to form a silicon oxide film 105 of about 30 nm.
  • the thermal oxidation is preferably performed at a temperature as low as possible from the viewpoint of preventing the high-concentration collector layer 102 from rising, and in this embodiment, the thermal oxidation is performed at about 90 Ot.
  • a silicon oxide film 106 of 200 ⁇ m is formed by the CVD method, and only a silicon oxide layer 106 is removed by wet etching at a place where an emitter is to be formed.
  • silicon oxide film 106 This is because a step is formed in the silicon oxide film 106 in order to secure a space between a base lead electrode formed later and the semiconductor substrate and to facilitate connection with the base region.
  • approximately 50 nm of silicon nitride 107 is formed by the CVD method.
  • other materials can be used instead of the silicon nitride film 107. Since the silicon nitride film 107 is partly removed later by etching, it is necessary to use a material having a sufficient selectivity with respect to the silicon oxide film.
  • the silicon oxide film 107, the silicon oxide film 106, and the silicon oxide film 105 are opened by dry etching, and n-type impurities are ion-implanted. , An n-type layer 108 is formed. Thereafter, a collector polycrystalline silicon electrode 109 is formed.
  • a 200 nm p-type polycrystalline silicon film 110 is deposited and processed into a base polycrystalline silicon polarized pattern.
  • the base extraction electrode 110 is processed into a size necessary to be connected to the base electrode later, and the silicon oxide film 106 formed by selective etching as shown in FIG. 4 (b). It is formed so as to straddle the step.
  • a 200 nm silicon The con oxide film 111 is laminated.
  • the silicon oxide film 111 and the base polycrystalline silicon electrode 110 are etched using the resist film defining the intrinsic region of the transistor as a mask. .
  • a silicon oxide film 112 is deposited to a thickness of about 100 nm, and a side wall insulating film 112 is formed by dry etching.
  • the silicon nitride film 107 is side-etched by wet etching using hot phosphoric acid or the like. This side-etched portion is filled with polycrystalline silicon later to form a contact with the base lead electrode.
  • a side etch of about 100 nm is performed as a value satisfying both requirements.
  • the first p-type polycrystalline semiconductor graft base 1 having the same thickness as the silicon nitride film 107 was formed by selective growth only on the portion of the base polycrystalline silicon electrode 110 exposed by the side-etching.
  • the selective growth is performed at a temperature of about 500 to 600 using monosilane, disilane, or a mixed gas of these and germane depending on the material to be deposited.
  • the polycrystal is grown using the polycrystal base extraction electrode as a seed, and the graft base region 113 is formed.
  • the silicon oxide film 105 is etched using an HF-based etchant, and the p-type single crystal semiconductor base layer 114 is formed by selective growth.
  • a second p-type polycrystalline semiconductor graft base 1 15 is simultaneously formed. This selective growth can be performed under the same conditions as the selective growth of the graft base region 113 described above.
  • the base region 1 14 is deposited on the low-concentration collector layer 103, which is a single crystal, while maintaining the single crystal.
  • the gradient region 1 15 is a polycrystalline graphite base region 1 1 3 Is deposited in a polycrystalline state.
  • the side surface of the base region 114 growing as a single crystal becomes the (111) plane.
  • the region to be a single crystal and the region to be a polycrystal are oblique along the (111) plane.
  • the silicon region 114 can be made of either a silicon single crystal or a silicon-germanium single crystal, but generally, silicon-germanium has characteristics such as a larger current width ratio.
  • the step of filling the graft base region 113 and the step of depositing the graft base region 115 and the base region 114 are performed separately.
  • the graphite base region 113 can be sufficiently filled, the connection with the base extraction electrode 110 can be sufficiently achieved, and the impurity concentration can be set separately.
  • the impurity concentration of the graft base region 113 can be increased, and the base resistance can be reduced.
  • an opening is formed up to the silicon oxide film 105, the silicon nitride film 107 is removed by wet etching, and then selective growth is performed. It can be realized.
  • a silicon oxide film is again deposited on the entire surface by the CVD method, and the side wall insulating silicon oxide film 116 is removed by anisotropic dry etching. Form.
  • a high-concentration n-type polycrystalline silicon is deposited on the entire surface, and the periphery of the emitter region is etched using a resist mask having an S-shaped pattern to form a polycrystalline silicon emitter electrode 117.
  • heat treatment is performed at 900 for about 30 seconds, and n-type impurities are diffused from the polycrystalline silicon emitter electrode 117 to the surface of the base layer 114 to form an emitter region 118.
  • the bipolar transistor according to the present embodiment has a collector region 103 formed by depositing on the semiconductor substrate and a base region 114 formed by projecting on the collector region.
  • the base electrode is formed from an emitter region formed by diffusion in the base castle, and the base extraction electrode can be configured to be connected from the side surface of the base castle.
  • a portion deposited as the base region 114 and in contact with the collector slope remains in an open area for selective growth, so that the base-collector capacitance can be reduced.
  • a silicon oxide film 119 is deposited, and an emitter and a base are deposited. Open the silicon oxide film 119 on the electrode of each source and collector by dry etching, and form the emitter electrode 120, the base electrode 121, and the collector 3 ⁇ 4 ⁇ 122 with tungsten. .
  • the structure shown in FIG. 1 is obtained by the above manufacturing method.
  • the emitter electrode 120 and the like can be formed by a gold-extended material such as aluminum in addition to tungsten.However, when aluminum is used, it is necessary to consider the mutual diffusion of silicon with the polycrystalline silicon 117 and the like. It is necessary to use a barrier metal such as titanium nitride between them.
  • FIG. 8 is a sectional view of a second embodiment of the present invention.
  • the same parts as those in the above-described embodiment are denoted by the same reference numerals, and description thereof will be omitted.
  • a silicon oxide film 130 which is an insulative material, is formed on a silicon substrate 101, and a single crystal silicon layer 131 serving as a semiconductor base portion on which elements are formed is formed thereon.
  • an SOI (silicon 'on' insulator) substrate is used, which is formed by using a manufacturing method similar to that of the first embodiment on an SOI substrate formed by known bonding or implantation of oxygen ions.
  • the collector-to-substrate capacitance i is 1 Z2 compared to the first embodiment.
  • the reduction of the base-collector capacitance and the SOI substrate realized by the present invention can be achieved. It is possible to further reduce the parasitic capacitance S of the bipolar transistor by reducing the collector to substrate capacitance !.
  • FIG. 12 is a sectional view of a bipolar transistor according to a third embodiment of the present invention.
  • the description of the parts of the present embodiment which are the same as those of the first and second embodiments will be omitted.
  • a so-called LOCOS oxide film is used together with the groove 104 for element isolation.
  • reference numeral 134 denotes a local isolation oxide (OSC) oxide film for element isolation in which the area other than the element formation region is locally oxidized.
  • OSC local isolation oxide
  • a high concentration n-type collector buried layer 102 is formed on a silicon substrate 101 by thermal expansion, and then a low concentration n-type A collector layer 103 is deposited.
  • planarly high level n-type collector A 3 m deep is formed by dry etching so as to surround the periphery of the buried layer 102, the silicon oxide film 104 is buried, and a device for element separation for electrically separating the devices is formed. Form 3 ⁇ 4.
  • the surface of the low-concentration n-type collector layer 103 which is the semiconductor substrate formed by the epitaxial growth, is oxidized by thermal oxidation to form a silicon oxide film of about 20 nm. Form.
  • a silicon nitride film 133 which is an oxidation-resistant film, is deposited on the entire surface by the CVD method to a thickness of about 200 nm, and dry etching is performed on portions other than those where the intrinsic region is to be formed, as shown in FIG.
  • the silicon nitride film 133 is left.
  • the silicon oxide film 107 and the LOCOS oxide film 134 are opened by dry etching, n-type impurities are ion-implanted, and contact with the collector electrode is made. An n-type layer 108 for reducing resistance is formed. Thereafter, a collector polycrystalline silicon electrode 109 is formed.
  • a p-type polycrystalline silicon film 110 of about 200 nm is deposited and processed into a base polycrystalline silicon electrode pattern.
  • the base extraction electrode 110 is formed so that its end is formed on the LOCOS oxide film and has a step.
  • the silicon oxide layer 111 and the base polycrystalline silicon electrode 110 are formed. Perform etching. Thereafter, in order to form a silicon oxide film 112 having a sidewall isolation, a silicon oxide is deposited to a thickness of about 100 nm and then dry-etched to form a side wall 112.
  • the silicon nitride film 107 is side-etched with hot phosphoric acid by 100 nm.
  • the side etch forms the graph base area described later.
  • the process is performed to the left and right in the figure to the bottom of the base extraction electrode 110, respectively.
  • the base portion serving as the collector region is protected by the oxide film 134, and the side surface of the base lead electrode 110 is supported by the side wall oxide film 112.
  • the first p-type polycrystalline semiconductor graph having the same thickness as the silicon nitride film 107 was formed only by the selective growth method on the portion exposed by the side etch under the base polycrystalline silicon electrode 110.
  • the LOCOS oxide layer 134 is etched using an HF-based etchant, and the base layer 1 of the p-type single crystal semiconductor is formed by a selective growth method. 14 are deposited on the collector region 103. At this time, the second p-type polycrystalline semiconductor graft base 115 is simultaneously formed.
  • a silicon oxide film is deposited on the entire surface by the CVD method, and a silicon oxide film sidewall 16 is formed by anisotropic dry etching.
  • high-concentration n-type polycrystalline silicon is deposited on the entire surface, and is etched using a resist mask having a pattern covering the periphery of the emitter region to form a polycrystalline silicon emitter electrode 117.
  • a heat treatment is performed at about 900 for about 30 seconds, and n-type impurities are diffused from the polycrystalline silicon emitter electrode 117 to the surface of the base layer 114 to selectively grow the base region 1.
  • An emitter region 1 18 is formed in 14.
  • a silicon oxide film 119 is deposited, and polycrystalline silicon of the emitter, base, and collector is opened.
  • the silicon oxide film 119 on the electrode is opened by dry etching, and the emitter electrode 122 is made of tungsten. 0, base electrode 122, and collector electrode 122 are formed.
  • the structure shown in FIG. 12 is obtained by the above manufacturing method.
  • the thickness of the silicon oxide film 134 below the first graph base 114 is formed by the LOCOS method, so that the thickness increases as the distance from the emitter increases, and the base-collector capacitance becomes lower. Can be destroyed.
  • the process for forming the base extraction electrode 110 with a step can be formed by the process of forming the L ⁇ COS oxide film, the silicon oxide film 106 as in the first embodiment can be formed. ⁇ The etching step can be omitted.
  • FIG. Also in this embodiment, the description of the same parts as those in the above-described embodiment will be omitted.
  • a manufacturing method similar to that of the third embodiment is used by using an SOI substrate having a silicon oxide layer 130 as an insulating film and a single-crystal silicon layer 131 on a silicon substrate 101. .
  • the capacitance between the collector substrates is about 1/2 that of the third embodiment.
  • the base extraction electrode 140 is formed of tungsten. Also in this embodiment, the description of the parts common to the above-described embodiments is omitted.
  • a 50 nm p-type polycrystalline silicon film 1 is formed. 35 is deposited and processed into a base polycrystalline silicon electrode pattern. On top of this, a 20 nm silicon oxide film 1336 and a 150 nm polycrystalline silicon film 1337 are stacked, and a 400 nm silicon oxide film 111 is further laminated.
  • a silicon oxide film 111, a polycrystalline silicon film 1337, and a silicon oxide film 11 are used as a mask with a resist (not shown) defining an intrinsic region of the transistor. 1 36 and the p-type polycrystalline silicon film 1 35 are etched. After that, a silicon oxide layer 112 is deposited to a thickness of 100 nm, and a side wall is formed by dry etching.
  • the polycrystalline silicon layer 117 is deposited on the entire surface through the steps shown in FIGS. 5 (c) to 6 (b) shown in the first embodiment and the like, and is shown in FIG. 15 (c). Such a structure is formed.
  • a silicon oxide film 1380 is deposited to a thickness of 300 nm, and a silicon oxide film 1380, an emitter polycrystalline silicon electrode 117 and a silicon oxide film 111 are formed. Is processed by dry etching into a pattern covering the emitter. Thereafter, a silicon oxide film 139 is deposited on the entire surface, and a silicon oxide film 139 is formed by anisotropic dry etching.
  • the polycrystalline silicon 137 is removed by isotropic dry etching, and the silicon oxide film 136 is removed by wet etching.
  • a base tungsten lead electrode 140 and a collector tungsten 141 are formed on the exposed p-type polycrystalline silicon 135 by a selective CVD method. After that, a silicon oxide film 119 is deposited, and the silicon oxide film 119 of the tungsten electrode of the base and collector is opened by dry etching on the polycrystalline silicon electrode of the emitter, and the emitter electrode 120 of tungsten is formed by tungsten.
  • a base electrode 1 2 1 and a collector electrode 1 2 2 are formed. With the above manufacturing method, the structure shown in FIG. 16 (b) is obtained.
  • the resistance of the base extraction electrode is reduced to about 1/10 as compared with the first embodiment.
  • a bipolar transistor with low power consumption can be formed.
  • an LOCOS oxide film can be used for element isolation as in the third embodiment, and an SO1 substrate can be used as in the second and fourth embodiments.
  • the base-collector capacitance is reduced, and the capacity between the collector and the substrate! : It is possible to reduce the resistance and further reduce the resistance of the base lead-out electrode, and it is possible to configure a bipolar transistor that can operate at high speed and high frequency. Therefore, by using the bipolar transistor according to the present invention particularly in a circuit or a system that requires a high-speed operation, it is possible to improve the performance of the entire circuit and the system.
  • FIG. 17 shows a sixth embodiment of the present invention.
  • the circuit shown in FIG. 17 is a circuit diagram showing a frontal hunting circuit used in the optical transmission system.
  • an optical transmission system requires high-speed transmission of several tens of Gbps, and its pre-width circuit requires particularly high-speed operation. Therefore, by employing the transistor according to the present invention as a transistor constituting this amplifying circuit, the performance of the entire width circuit can be remarkably improved.
  • reference numeral 300 denotes a semiconductor integrated circuit that constitutes a pre-arm circuit formed on a single semiconductor substrate.
  • PD is a photodiode that is a light receiving element that receives an optical signal transmitted through an optical transmission cable
  • 303 is a power line and a grounding line. This is a depletion capacitor connected to the internal circuit and short-circuiting the AC component, and is externally provided outside the semiconductor circuit 300.
  • the bipolar transistors Q1 and Q2 are bipolar transistors forming a wide-width circuit, and the above-described device having the structure of the present embodiment is applied.
  • Diode D1 is a diode for level shift, which can be formed by using the bipolar transistor of the present invention and short-circuiting between the base and the collector. Diodes can also be applied in series.
  • Rl, R2, and R3 are resistors.
  • OUT is an output terminal, and an output buffer circuit is inserted between the output terminal and the emitter of the transistor Q2 as necessary.
  • the optical signal transmitted through the optical transmission cable is converted into an electric signal by the photodiode PD, and the signal is transmitted through the input terminal IN of the semiconductor circuit 300 to the width transistors Q1 and Q2. It operates so that it is output from the output terminal OUT after being amplified by 2.
  • the present circuit has a margin of 40 GHz or more.
  • FIG. 18 shows a front end module of an optical transmission system in which the photodiode PD and the pre-width circuit 300 shown in FIG. 17 are integrated.
  • 401 is an optical fiber
  • 402 is a lens
  • 403 is a photodiode
  • 404 is a semiconductor integrated circuit on which a preamplifier is formed.
  • Reference numeral 407 denotes a substrate on which a photodiode and a preamplifier 404 are mounted, which is connected to an output amplifier 406 via a wiring 406 for connecting a diode and a louver. Have been.
  • Reference numeral 408 denotes a hermetically sealed package such as a metal case.
  • the substrate 407 also has the capacitor 303 shown in FIG.
  • the signal path can be shortened, making it difficult for noise to occur and reducing the parasitic L and C components. Can be suppressed.
  • This embodiment is an example in which the semiconductor device manufactured according to the above embodiment is used for the preamplifier circuit of the sixth embodiment, which is used as an integrated circuit chip, and is applied to a front end module.
  • the optical signal input from the optical fiber 401 is passed through the lens 402.
  • the light is condensed and converted to an S-gas signal by the photo diode IC 403. Electrical signal is on the board
  • the signal is amplified by the preamplifier IC 404 through the wiring 405 on 407 and output from the output terminal 406.
  • FIGS. 19 and 20 show system configuration diagrams of the optical transmission system using the front-end amplifier and the front end module shown in FIGS. 17 and 18.
  • FIG. 19 shows a transmitting system 500 of the optical transmission system.
  • the gas signal 501 to be transmitted is input to the multiplexer MUX and multiplexed into, for example, 4: 1 and the output signal is transmitted to the driver 502.
  • the semiconductor laser LD always emits light of a constant intensity, and an external modulator driven by a driver 502
  • the transmission module shown in Fig. 19 is what is called an external modulation type. In this embodiment, instead of this, it is possible to employ a direct modulation type which directly controls the light emission of the semiconductor laser, but in general, the transmission by the external modulation type is performed by a trap. Suitable for high-speed, long-distance transmission with no spread of vector oscillation.
  • FIG. 20 shows an optical receiving module 510 of the optical transmission system according to the present embodiment.
  • reference numeral 52 denotes a front-end module to which the embodiment of the present invention shown in FIGS. 17 and 18 can be applied.
  • the electric signal amplified by the preamplifier 522 in the front end module is input to the main amplifier 530 and amplified.
  • the main amplifier 530 is input to an automatic gain adjuster 531 that sweeps the output of the main amplifier 532 to keep the output constant, avoiding variations due to optical transmission distances and manufacturing deviations. It is configured to: It should be noted that, in addition to the configuration for adjusting the gain, a limit amplifier for limiting the output amplitude may be employed for the main amplifier.
  • the Iffi classifier 540 is configured to perform 1-bit analog-to-digital conversion in synchronization with a predetermined clock, digitizes the output of the main amplifier section, and uses a separator DMUX to output, for example, 1: 4.
  • the signal is input to a digital signal processing circuit 560 of the subsequent stage, and a predetermined process is performed.
  • the mouth extraction unit 550 is the operation timing of the separator 540 and the separator DMU X
  • the output of the main amplifier section 530 is rectified by the full-wave rectifier 551, and is filtered by the narrow-band filter 552 to become a clock signal. Extract the signal.
  • the output of the filter 552 is a phase shifter for matching the phase of the filter output and the analog signal, and delays the filter output based on a predetermined delay 1 :.
  • a circuit can be configured using the transistor element having the above-described configuration at various points.
  • the circuit constituting the main amplifier 532 can be constituted by the circuit shown in FIG.
  • FIG. 21 is a configuration diagram of a mobile radio portable device according to a ninth embodiment of the present invention.
  • a semiconductor device manufactured according to the above embodiment is manufactured by using a mobile radio such as a low-noise gun 603, a synthesizer 606, a PLL (Phase Locked Loop) 611, or the like.
  • a mobile radio such as a low-noise gun 603, a synthesizer 606, a PLL (Phase Locked Loop) 611, or the like.
  • PLL Phase Locked Loop
  • the input from the antenna is amplified by the low-noise amplifier 603, the frequency emitted from the synthesizer 606 is oscillated from the oscillator 605, and the signal from the low-noise amplifier 603 is used by using the signal oscillated from the oscillator 605.
  • the down-mixer 604 down-compensates to a lower frequency. Further, the frequency generated from the PLL 611 is oscillated from the oscillator 610, and the signal from the down mixer 604 is oscillated from the oscillator 610, and the lowering device 609 is used to handle the lower frequency. Signal processing is performed by the baseband unit 6 13.
  • the signal emitted from the baseband unit 613 is modulated by the transformer 612 using the signal from the PLL 611, and furthermore, the upmixer 608 converts the signal by the synthesizer 606.
  • the signal is up-converted to a high frequency based on this signal, amplified by the power amplifier 607, and transmitted from the antenna 601.
  • Reference numeral 602 denotes a switch for switching between transmission and reception of a signal. The switch receives a control signal (not shown) from the base unit 613 and controls its transmission and reception.
  • the baseband unit 6 13 is connected to a microphone (not shown), which is not shown in the drawing, and is capable of inputting and outputting audio signals.
  • the semiconductor device manufactured according to the above-described embodiment may be applied to each block of the present embodiment, in particular, to the low-noise amplifier 603, the synthesizer 606, and the PLL 611 to configure respective circuits. it can. Since the transistor according to the present invention can reduce the base resistance and the base collector capacitance, the low-noise gun 603, the synthesizer 606, and the PLL 611 reduce noise and reduce power consumption. Can be achieved. This makes it possible to realize a mobile wireless portable device that can be used for a long time with low noise as a whole system.
  • FIG. 22 is a circuit diagram of a D flip-flop used in a PLL prescaler of a mobile radio portable device according to a tenth embodiment of the present invention.
  • This embodiment is an example in which the semiconductor device g manufactured according to the above-described embodiment is used for the transistors 71 to 72 on the circuit of FIG.
  • the input signal, the close signal, and the output signal have only two states, high potential and low potential.
  • the input signal and inverted input signal are input to terminals 7 19 and 7 20, respectively, and the clock signal and inverted clock signal are input to terminals 7 2 1 and 7 22, respectively.
  • Terminals 7 2 3 and 7 An output signal and an inverted output signal are obtained from 24.
  • the current paths flowing through the current sources 718 and 719 are switched to one of the transistors 709 and 710 and 711 and 712 by a clock signal, respectively.
  • the on / off of the transistors 701 to 706 is determined by an input signal, a short-circuit signal, and a potential at a lower end of the resistor generated by a current flowing through the resistors 713 and 714. In this circuit, the output signal outputs an input value when the peak signal changes from a low level to a high potential, and otherwise holds the previous input value.
  • the semiconductor device manufactured according to the above-described embodiment can reduce the base resistance and the base no-collector volume 1: so that the power consumption of PLL of the mobile wireless portable device can be reduced.
  • the present invention uses a base plug without increasing the base resistance.
  • the transistor capacity can be reduced, and a transistor that operates at high speed with low power consumption can be obtained.
  • Applying this to a wide-bandwidth circuit and peripheral circuits of an optical transmission system makes it possible to transmit and receive large-capacity signals at ultra-high speed.
  • a mobile wireless portable device that has low noise and can be used for a long time can be obtained.
  • the present invention can be applied to a bipolar transistor and various semiconductor integrated circuit devices using the same.
  • the present invention is applicable to a semiconductor integrated circuit device forming an optical transmission system or a mobile wireless terminal. Can be.

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un transistor bipolaire de faible puissance et à vitesse ultra-haute, ainsi qu'un circuit utilisant ledit transistor, permettant l'émission à vitesse ultra-haute et la réception d'une grande quantité de signaux, ainsi que le fonctionnement à bruit réduit d'un dispositif radio portable sur de longues périodes. On insère un film d'oxyde de silicium (115) sous une base greffée en silicium polycristallin (113) reliant une zone de la base (114) à une électrode de base en silicium polycristallin (110). Ceci permet d'abaisser la résistance de la base et la capacitance base-collecteur, et d'obtenir un transistor de faible puissance fonctionnant à vitesse ultra-haute.
PCT/JP1995/001844 1995-09-18 1995-09-18 Dispositif a semi-conducteur, procede de fabrication associe et systeme utilisant ledit dispositif WO1997011496A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1995/001844 WO1997011496A1 (fr) 1995-09-18 1995-09-18 Dispositif a semi-conducteur, procede de fabrication associe et systeme utilisant ledit dispositif

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Application Number Priority Date Filing Date Title
PCT/JP1995/001844 WO1997011496A1 (fr) 1995-09-18 1995-09-18 Dispositif a semi-conducteur, procede de fabrication associe et systeme utilisant ledit dispositif

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WO1997011496A1 true WO1997011496A1 (fr) 1997-03-27

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123949A (ja) * 2007-02-16 2007-05-17 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
CN117594442A (zh) * 2024-01-18 2024-02-23 常州承芯半导体有限公司 半导体器件及其形成方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63289863A (ja) * 1987-05-21 1988-11-28 Sony Corp バイポ−ラトランジスタおよびその製造方法
JPH01300559A (ja) * 1988-05-30 1989-12-05 Oki Electric Ind Co Ltd バイポーラ型半導体集積回路装置の製造方法
JPH03147332A (ja) * 1989-11-02 1991-06-24 Nec Corp 半導体装置の製造方法
JPH04188716A (ja) * 1990-11-22 1992-07-07 Hitachi Ltd 半導体装置及びその製造方法
JPH04262539A (ja) * 1991-02-18 1992-09-17 Nec Corp 半導体装置およびその製造方法
JPH05299429A (ja) * 1992-04-08 1993-11-12 Nec Corp 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63289863A (ja) * 1987-05-21 1988-11-28 Sony Corp バイポ−ラトランジスタおよびその製造方法
JPH01300559A (ja) * 1988-05-30 1989-12-05 Oki Electric Ind Co Ltd バイポーラ型半導体集積回路装置の製造方法
JPH03147332A (ja) * 1989-11-02 1991-06-24 Nec Corp 半導体装置の製造方法
JPH04188716A (ja) * 1990-11-22 1992-07-07 Hitachi Ltd 半導体装置及びその製造方法
JPH04262539A (ja) * 1991-02-18 1992-09-17 Nec Corp 半導体装置およびその製造方法
JPH05299429A (ja) * 1992-04-08 1993-11-12 Nec Corp 半導体装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007123949A (ja) * 2007-02-16 2007-05-17 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
CN117594442A (zh) * 2024-01-18 2024-02-23 常州承芯半导体有限公司 半导体器件及其形成方法
CN117594442B (zh) * 2024-01-18 2024-05-28 常州承芯半导体有限公司 半导体器件及其形成方法

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