JP2000150532A - Semiconductor device and system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transistor which operates fast with low power consumption by tilting the side wall of an opening of a base polycrystal silicon electrode, allowing the upper part of the opening to be wider while the lower part narrower, and reducing a base-collector capacitance with no increase in base resistance and emitter resistance. SOLUTION: A silicon oxide film 109 is etched using a mask with only a true region opened and a polycrystal silicon film 108 is worked into tapered form. The polycrystal silicon film 108 is, for example, worked by an anisotropic dry etching with much side-wall deposit. Thus, related to the polycrystal silicon film 108, an open area decreases at a constant rate due to the side-wall deposit as advances downward, resulting in its tapered side-wall. The contact area between the base polycrystal silicon electrode 108 and a polycrystal silicon graft base 112 is maintained without reducing open area at the upper part of an emitter opening while a base/collector capacitance is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ultra-high-speed bipolar semiconductor device, a semiconductor integrated circuit device, and an optical transmission system device.

[0002]

2. Description of the Related Art FIG. 2 is a sectional view of a bipolar transistor using a conventional silicon selective epitaxial method.
In FIG. 2, 201 is a p-type silicon substrate, 202 is n
⁺ Type buried layer, 203 is an n ⁻ type silicon epitaxial growth layer, 204, 208, 209, 210, 213, 21
6 is a silicon oxide film, 205 is an n ⁺ type phosphorus diffusion layer, 20
7 is a polycrystalline silicon for ap ⁺ type base electrode, 206 is a silicon nitride film, 212a is a single crystal silicon intrinsic base layer, 212b is a polycrystalline silicon graft base, 214
Is a single-crystal silicon emitter, 215 is polycrystalline silicon for an n ⁺ -type emitter electrode, and 217, 218, and 219 are aluminum electrodes. The conventional example of FIG.
It is described in Issue 2.

[0003]

In the prior art shown in FIG.
Silicon nitride film 206 to reduce base / collector capacitance
As the side-etch amount of the base region 212a and the low-concentration layer 203 is reduced,
The contact area between base polycrystalline silicon electrode 207 and polycrystalline silicon graft base 212b decreases, and the base resistance increases. Thus, in the conventional structure of FIG. 2, there is a trade-off relationship between the base / collector capacitance and the base resistance. When the silicon oxide film 209 is thinned without changing the contact area between the base polycrystalline silicon electrode 207 and the polycrystalline silicon graft base 212b, the emitter capacitance increases, and the aspect ratio of the emitter opening increases.
Emitter resistance also increases.

[0004]

According to the present invention, the side wall of the opening of the base polycrystalline silicon electrode is inclined, and the upper part of the opening is widened and the lower part is narrowed. Thereby, the contact area between the base polycrystalline silicon electrode and the polycrystalline silicon graft base can be maintained without reducing the opening area above the emitter opening, and without increasing the emitter resistance and the base resistance. The collector capacity can be reduced.

[0005]

FIG. 1 is a sectional view of a transistor according to a first embodiment of the present invention. In FIG. 1, 101 is a silicon substrate, 102 is a high concentration collector burying layer, 103
Is a low concentration collector layer, 104, 106, 107, 10
9, 110, 113 and 116 are silicon oxide films, 105
Is an n-type collector contact layer, 108 is a base polycrystalline silicon electrode, 111 is a monocrystalline semiconductor base layer, 112 is a polycrystalline semiconductor graft base, 114 is an emitter polycrystalline silicon electrode, 115 is an emitter region, 117 is an emitter electrode, 118 Denotes a base electrode, and 119 denotes a collector electrode.

FIGS. 3 to 5 show a manufacturing method according to a first embodiment of the present invention. After the high concentration n-type collector buried layer 102 is formed on the silicon substrate 101 by thermal diffusion, the low concentration n-type collector layer 103 is formed by silicon epitaxial growth.
To form A silicon oxide film 104 is formed by LOCOS on the entire surface except for the intrinsic region and a portion expected to be a collector region. Alternatively, the entire surface excluding the intrinsic region and the portion expected to be the collector region is cut by about 400 nm by dry etching, and the portion is buried with the silicon oxide film 104. An n-type collector contact layer 105 is formed in the collector region by ion implantation (FIG. 3A).

On a plane, a high concentration n-type collector burying layer 102
Is formed to have a depth of 3 μm, and the silicon oxide film 106 is buried. A silicon oxide film 107 is deposited on the entire surface by the CVD method (FIG. 3B).

A polycrystalline silicon film 108 of about 200 nm
Is formed on the entire surface, and a p-type impurity is added to the polycrystalline silicon film 108 by ion implantation. The polycrystalline silicon film is removed except for the base polycrystalline silicon region. A silicon oxide film 109 of about 500 nm is deposited thereon (FIG. 3C).

The silicon oxide film 109 is etched using a mask for opening only the intrinsic region. Further, the polycrystalline silicon film 108 is processed into a tapered shape. For example, the polycrystalline silicon film 108 is processed by using anisotropic dry etching with a large amount of sidewall deposits. As a result, the opening area of the polycrystalline silicon film 108 decreases at a constant rate due to the side wall deposit as it goes downward, and the side wall becomes tapered. Thereafter, a silicon oxide film 110 is deposited,
A sidewall 110 of a silicon oxide film is formed by anisotropic dry etching. At this time, the dry etching amount is the same as that of the silicon oxide film 110 and the polycrystalline silicon film 10.
8 so that the lower part of the side wall 110 is made a vertical surface (FIG. 4A).

The silicon nitride film 107 is side-etched by wet etching. Then, a single crystal silicon and a silicon-germanium mixed crystal 1 are formed on the opened intrinsic region.
Then, polycrystalline silicon and a silicon-germanium mixed crystal 112 are selectively formed on the bottom surface of the polycrystalline silicon film 108 (FIG. 4B).

A silicon oxide film 113 is deposited, and a silicon oxide film sidewall 113 is formed by anisotropic dry etching. Thereafter, high-concentration n-type polycrystalline silicon 114 is deposited on the entire surface and etched using a resist mask having a pattern covering the periphery of the emitter region to form a polycrystalline silicon emitter electrode 114. Then 900
C. for about 30 seconds to diffuse n-type impurities from the polycrystalline silicon emitter electrode to the surface of the base layer 111,
An emitter region 115 is formed (FIG. 5A).

A silicon oxide film 116 is deposited, the silicon oxide film 116 on each of the polycrystalline silicon electrodes of the emitter, base and collector is opened by dry etching, and the emitter electrode 117 and the base electrode 11 are made of tungsten.
8. A collector electrode 119 is formed. The structure shown in FIG. 1 is obtained by the above manufacturing method (FIG. 5B).

FIGS. 6 to 9 show a manufacturing method according to a second embodiment of the present invention. After the high concentration n-type collector buried layer 102 is formed on the silicon substrate 101 by thermal diffusion, the low concentration n-type collector layer 103 is formed by silicon epitaxial growth.
To form A silicon oxide film 104 is formed by LOCOS on the entire surface except for the intrinsic region and a portion expected to be a collector region. Alternatively, the entire surface excluding the intrinsic region and the portion expected to be the collector region is cut by about 400 nm by dry etching, and the portion is buried with the silicon oxide film 104. An n-type collector contact layer 105 is formed in the collector region by ion implantation (FIG. 6A).

On a plane, a high concentration n-type collector buried layer 102
Is formed with a depth of 3 μm so as to surround the silicon oxide film 106. Silicon oxide film on entire surface by CVD method
107 is deposited (FIG. 6B).

After forming a polysilicon film 108 of about 50 nm, a p-type impurity is added to the polysilicon film 108 by ion implantation. Thereafter, a silicon oxide film 120 of about 20 nm and a polycrystalline silicon 121 of about 150 nm are laminated, and the polycrystalline silicon 121, the silicon oxide film 120, and the polycrystalline silicon film 108 are removed except for the base electrode region. A silicon oxide film 109 is deposited thereon (FIG. 6C).

After etching the silicon oxide film 109 using a mask for opening only the intrinsic region, the polycrystalline silicon film 121 is processed into a tapered shape. For example, the polycrystalline silicon film 121 is processed by using anisotropic dry etching with a large amount of sidewall deposits. As a result, the opening area of the polycrystalline silicon film 121 is reduced at a constant rate by the side wall deposits as it goes downward, and the side wall becomes tapered. After that, the silicon oxide film 120 is etched,
The polycrystalline silicon film 108 is processed in the same manner as the polycrystalline silicon film 120. Thereafter, a silicon oxide film 110 is deposited, and a sidewall 110 of the silicon oxide film is formed by anisotropic dry etching. At this time, the dry etching amount is performed by the total thickness of the silicon oxide film 110 and the polycrystalline silicon film 108, and the lower part of the side wall 110 is made a vertical surface (FIG. 7A).

The silicon nitride film 107 is side-etched by wet etching. Then, a single crystal silicon and a silicon-germanium mixed crystal 1 are formed on the opened intrinsic region.
11 is formed on the bottom surface of the polycrystalline silicon film 108 by selectively forming polycrystalline silicon and a silicon-germanium mixed crystal 112 (FIG. 7B).

A silicon oxide film 113 is deposited, and a silicon oxide film sidewall 113 is formed by anisotropic dry etching. Thereafter, high-concentration n-type polycrystalline silicon 114 is deposited on the entire surface and etched using a resist mask having a pattern covering the periphery of the emitter region to form a polycrystalline silicon emitter electrode 114. Then 900
C. for about 30 seconds to diffuse n-type impurities from the polycrystalline silicon emitter electrode to the surface of the base layer 111,
An emitter region 115 is formed (FIG. 8A).

The polycrystalline silicon emitter electrode 114 is covered with a resist, and a silicon oxide film 109, polycrystalline silicon 1
08 is removed (FIG. 8B).

A silicon oxide film 116 is deposited, the silicon oxide film 116 on each of the polycrystalline silicon electrodes of the emitter, base and collector is opened by dry etching, and the emitter electrode 117 and the base electrode 11 are made of tungsten.
8. A collector electrode 119 is formed (FIG. 9).

According to the present embodiment, the base resistance is １ ／ compared to the first embodiment.

FIG. 10 is a sectional view of a third embodiment of the present invention. In the present embodiment, a metal silicide 124 is formed on polycrystalline silicon 108, and the same manufacturing method as in the first embodiment is used. By using this structure, the base resistance is reduced by half compared to the first embodiment.

FIG. 11 is a sectional view of a fourth embodiment of the present invention. In the present embodiment, a manufacturing method similar to that of the first embodiment is used using an SOI substrate having a silicon oxide film 120 and a single crystal silicon layer 121 on a silicon substrate 101. By using this structure, the capacity of the collector / substrate is reduced to half of that of the first embodiment.

FIG. 12 is a preamplifier circuit diagram of an optical transmission system according to a fifth embodiment of the present invention. This embodiment is an example in which the semiconductor device manufactured according to the above embodiment is used for the amplification transistor 301 on the circuit and the transistors 302 and 303 of the buffer circuit. This circuit amplifies the input from the photodiode 306 and outputs the signal from the output buffer 307 through an amplifier circuit including transistors 301, 302, 303 and resistors 304, 305. By using the semiconductor device manufactured according to the above-described embodiment, this circuit can achieve 40 G
hz or more.

FIG. 13 shows a front end module including a photodiode and a preamplifier in an optical receiving module according to a sixth embodiment of the present invention. This embodiment is an example in which a semiconductor device manufactured according to the above embodiment is applied to a front-end module using the preamplifier circuit of the fifth embodiment as an integrated circuit chip. An optical signal input from the optical fiber 401 is condensed by a lens 402 and converted into an electric signal by a photodiode IC 403. The electric signal is amplified by the preamplifier IC 404 through the wiring 405 on the substrate 407 and output from the output terminal 406.

FIG. 14 is a configuration diagram of an optical transmission system according to a seventh embodiment of the present invention. This embodiment is an example in which the semiconductor device manufactured according to the above embodiment is applied to both transmission systems of an optical transmission module 513 for transmitting data at an ultra-high speed and an optical reception module 514 for receiving data.

In this embodiment, an optical transmission module comprising a multiplex conversion digital circuit 501 for processing a transmission-side electric signal 510 by a semiconductor device manufactured according to the above embodiment, and a semiconductor laser driving analog circuit 502 for driving a semiconductor laser 503. 513, a preamplifier 505 for amplifying a receiving-side electric signal 512 obtained by converting a transmitted optical signal 511 by a photodiode 504, an automatic gain control amplifier 506, a clock extracting circuit 507,
The optical receiver module 514 includes the analog circuits of the identification circuit 508 and the separation / conversion circuit 509 which is a digital circuit. Here, the photodiode 50
4. The preamplifier 505 has a cutoff frequency and a maximum cutoff frequency of 100 for the semiconductor device manufactured according to the above embodiment.
Ghz and can operate at ultra high speed, 40G per second
Bits and large capacity signals can be transmitted and received at ultra-high speeds.

[0028]

According to the present invention, the base / collector capacitance can be reduced without increasing the base resistance and the emitter resistance. Thus, a transistor which operates at high speed with low power consumption can be obtained.

[Brief description of the drawings]

FIG. 1 is a sectional view of a bipolar transistor according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional bipolar transistor.

FIG. 3 is a sectional view showing a manufacturing process of the bipolar transistor according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a manufacturing process of the bipolar transistor according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a manufacturing process of the bipolar transistor according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing a manufacturing process of the bipolar transistor according to the second embodiment of the present invention.

FIG. 7 is a sectional view showing a manufacturing process of the bipolar transistor according to the second embodiment of the present invention.

FIG. 8 is a sectional view showing a manufacturing process of the bipolar transistor according to the second embodiment of the present invention.

FIG. 9 is a sectional view showing a manufacturing process of the bipolar transistor according to the second embodiment of the present invention.

FIG. 10 is a sectional view of a bipolar transistor according to a third embodiment of the present invention.

FIG. 11 is a sectional view of a bipolar transistor according to a fourth embodiment of the present invention.

FIG. 12 is a circuit diagram of a preamplifier of an optical transmission system according to a fifth embodiment of the present invention.

FIG. 13 is a sectional view of a front-end module of an optical transmission system according to a sixth embodiment of the present invention.

FIG. 14 is a block diagram illustrating a configuration of an optical transmission system according to a seventh embodiment of the present invention.

[Explanation of symbols]

101, 126: silicon substrate, 102: high concentration n-type collector region, 103: low concentration n-type collector region, 10
4,106,109,110,113,116,12
0, 125: silicon oxide film, 107: silicon nitride film, 108: base polycrystalline silicon electrode, 111: single crystal semiconductor base layer, 112: graft base of polycrystalline semiconductor, 114: emitter polycrystalline silicon electrode, 115 ...
Emitter region, 117: emitter electrode, 118: base electrode, 119: collector electrode, 121: polycrystalline silicon layer, 122: metal base layer, 123: metal emitter layer,
124 ... metal silicide layer, 201 ... p-type silicon substrate, 202 ... ^{n +} -type buried layer, 203 ... n ^- -type silicon epitaxial layer, 204 ... silicon oxide film, 205 ...
n ⁺ type phosphorus diffusion layer, 206 ... silicon nitride film, 207 ...
polycrystalline silicon for p ⁺ type base electrode, 208, 209,
210, 213, 216 ... silicon oxide film, 212a ...
Monocrystalline silicon intrinsic base layer, 212b polycrystalline silicon graft base, 214 emitter, 215 n ⁺
-Type polysilicon for emitter electrodes, 217, 218, 2
19: Al-based electrode, 301, 302, 303: transistor, 304, 305: resistor, 306: photodiode, 307: output buffer, 401: optical fiber, 4
02: lens, 403: photodiode, 404: preamplifier IC, 405: wiring, 406: output terminal, 40
Reference numeral 7: substrate, 408: package, 501: multiplex conversion digital circuit, 502: semiconductor laser drive analog circuit, 5
03: semiconductor laser, 504: photodiode, 50
5: Preamplifier, 506: Automatic gain control amplifier, 507
... Clock extraction circuit, 508 identification circuit, 509 separation conversion circuit, 510 transmission electric signal, 511 transmitted optical signal, 512 reception electric signal, 513 optical transmission module, 514 optical reception module.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H04B 10/28 10/26 10/14 10/04 10/06 (72) Inventor Katsuya Oda Kokubunji, Tokyo 1-280, Higashi-Koigakubo, Hitachi, Ltd. Central Research Laboratory, Hitachi, Ltd. (72) Inventor Katsuyoshi Washio 1,280, Higashi-Koikekubo, Kokubunji-shi, Tokyo F-term, Central Research Laboratory, Hitachi, Ltd. BB04 BB06 BB08 BB90 BC08 BE08 BF06 BM01 BP11 BP21 BP31 BP41 BP93 BS04 5F049 MA01 NA20 NB01 TA14 5K002 AA01 AA03 BA02 BA07 BA13 BA31 DA05 FA01

Claims (9)

[Claims] A semiconductor substrate of a first conductivity type, a first insulating film in contact with a main surface of the semiconductor substrate, and a first semiconductor region of a second conductivity type opposite to the first conductivity type; A first conductive type second semiconductor region in contact with the first semiconductor region and a second conductive type first polycrystalline semiconductor region in contact with the first insulating film and the first semiconductor region; Become the first
Wherein the polycrystalline semiconductor region has an opening above the second semiconductor region, and the area of the opening increases as the distance from the first semiconductor region increases. 2. The semiconductor device according to claim 1, wherein at least one region having a constant opening area exists. 3. The semiconductor device according to claim 1, wherein said semiconductor substrate is a collector region of a bipolar transistor, said first semiconductor region is a base region, and said second semiconductor region is an emitter region. Semiconductor device. 4. The semiconductor device according to claim 2, wherein said first semiconductor region is made of silicon germanium. 5. The semiconductor device according to claim 1, wherein a bottom shape of said first semiconductor region is defined by an opening of said first insulating film. 6. The semiconductor device according to claim 6, wherein the first conductivity type is n-type, the second conductivity type is p-type, and the semiconductor device is the first semiconductor region, the second semiconductor region, and the third semiconductor region. 2. The semiconductor device according to claim 1, wherein the region forms a bipolar transistor. 7. A light receiving element for receiving an optical signal and outputting an electric signal, a first amplifier circuit for receiving an electric signal from the light receiving element, a second amplifier circuit for receiving an output of the first amplifier circuit, An optical discriminator for converting an output of the second amplifying circuit into a digital signal in synchronization with a predetermined clock signal, wherein the first amplifying circuit has a base connected to the light receiving element. A first bipolar transistor connected thereto, a base connected to a collector of the first bipolar transistor, and a collector connected to the second bipolar transistor;
And a second bipolar transistor connected to an input of the amplifier circuit, wherein at least one of the first and second bipolar transistors is constituted by the semiconductor device according to claim 1 or 2. Characteristic optical receiving system. 8. An optical receiving system, wherein each of the first and second bipolar transistors is constituted by the semiconductor device according to claim 1. 9. The semiconductor device according to claim 1, wherein said first and second bipolar transistors are formed on a single semiconductor chip, and said light receiving element and said semiconductor chip are mounted on a single substrate. 9. The optical receiving system according to 7 or 8.