JP2000294564A - Bipolar transistor, manufacture thereof, and electronic circuit device or optical communication system using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high-speed operation for a bipolar transistor by lowering the external base resistance and lessen the dispersion of base resistance, and making the capacity between a collector and a base small. SOLUTION: A single crystalline Si-Ge intrinsic base 18 and a base layer 7 are connected with each other in a self alignment manner, by thickening a low-concentration collector layer 16 in the vicinity of an external base layer. Hereby, the distance between the intrinsic base 18 and the base lead layer 7 is reduced, and junction region is increased, whereby the base resistance of the splicing section can be reduced, and the dispersion of the base resistance can be reduced. Since the low-concentration collector becomes thick in the vicinity, the capacity between the collector and the base decreases. Accordingly, a high-speed bipolar transistor can be materialized, and by using this, an electronic circuit device or a system capable of high-speed operation can be materialized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bipolar transistor technology, and more particularly to a bipolar transistor using single crystal silicon / germanium as an intrinsic base layer, a method of manufacturing the same, an electronic circuit device using the bipolar transistor, and an optical device. The present invention relates to a communication system.

[0002]

2. Description of the Related Art A conventional bipolar transistor using single crystal silicon / germanium as an intrinsic base layer,
For example, US Patent No. 5,508,537 (US Patent No. 5,508,53
7). FIG. 49 is a diagram showing a cross-sectional structure of the conventional bipolar transistor, and FIGS. 50 and 51 are diagrams for explaining a manufacturing process of an active region which is a main part of the conventional bipolar transistor. .

Conventionally, as shown in FIG. 49, a high concentration n-type buried layer 32 is provided on a silicon substrate 31, and a bipolar transistor is formed on the high concentration n-type buried layer 32. A detailed process of forming a bipolar transistor on the high-concentration n-type buried layer 32 will be described with reference to FIGS.

First, as shown in FIG. 50, a low-concentration n-type silicon layer 33 serving as a collector layer is epitaxially grown on a high-concentration n-type buried layer 32 formed on a silicon substrate. A base insulating film 34 is formed.
The intrinsic region of the bipolar transistor is divided into three insulating films 4
After covering with the islands of 8, 49 and 50, a base extraction layer (polycrystalline silicon) 35 made of polycrystalline silicon and an emitter / base isolation insulating film 36 are formed, and an opening of an intrinsic region is formed. Next, the base extraction layer (polycrystalline silicon)
An insulating film 37 is formed on the side wall of the emitter / base isolation insulating film 36 (see FIG. 50A).

Next, the insulating film 48 covering the intrinsic region is selectively removed by etching to expose the low-concentration n-type silicon layer 33 (see FIG. 50B). Due to the selective etching of the insulating film 48, the lower part of the eaves of the base lead electrode 35 is covered with the double insulating films 49 and 50. Even after the insulating film 49 is removed by etching, the base lead layer (multiple) is formed by the insulating film 50. Since the (crystalline silicon) 35 is not exposed, the low-concentration n-type silicon / germanium layer 39 is selectively formed.
Can be formed. After selectively forming the low-concentration n-type silicon-germanium layer 39, the insulating film 50 is removed by etching, so that the base extraction layer 35 is formed.
Is exposed (see FIG. 50 (c)).

Next, as shown in FIG. 51, an intrinsic base layer 40 made of p-type single crystal silicon / germanium and an external base layer 4 made of p-type polycrystalline silicon / germanium
1 are selectively formed on the low-concentration n-type silicon layer 33 and the base extraction layer 35, respectively (see FIG. 51A). Next, after covering the insulating film 37 on the side wall with the insulating film 42, an n-type polycrystalline silicon layer 43 doped with phosphorus at a high concentration is deposited in the opening, and annealing is performed to diffuse phosphorus into the intrinsic base layer 40. This forms an emitter layer 45 (see FIG. 51B). Finally, as shown in FIG. 49, necessary electrodes 47 are provided on the base extraction layer 35, the n-type polycrystalline silicon layer (emitter extraction layer) 43, and the like to complete the bipolar transistor. A conventional bipolar transistor using single crystal silicon / germanium as an intrinsic base layer is manufactured as described above.

[0007]

As described above, the conventional bipolar transistor using single crystal silicon / germanium for the intrinsic base layer has the following problems. First, when the surface of the polycrystalline silicon-germanium layer (external base layer) 41 formed under the protrusion of the base extraction layer 35 contacts the intrinsic base layer 40 of single-crystal silicon-germanium. There is a gap at the interface. When such a gap is formed, no reactive gas is supplied to the gap, so that the gap is not filled even if epitaxial growth is continued thereafter. As a result, the intrinsic base layer 40 and the base extraction layer 35
Connection becomes incomplete and the base resistance increases.

Second, since the irregularities of the polycrystalline silicon-germanium layer (external base layer) 41 are not uniform, there is a problem that variation in base resistance among transistors becomes large. Third, the intrinsic base layer 40 is formed by the side etching of the collector / base isolation insulating film 34 accompanying the etching of the island-shaped insulating film before the formation of the intrinsic base layer 40.
Therefore, there is a problem that the high-speed operation of the circuit is suppressed because the facing area between the external base layer 41 and the external base layer 41 increases and the capacitance between the collector and the base increases.

Fourth, since the low concentration n-type silicon / germanium layer 39 is in direct contact with the external base layer 41 in which the p-type impurity is heavily doped, the p-type impurity in the external base layer 41 has a low concentration. n-type silicon / germanium layer 3
9, an external base layer is formed, and the collector-base junction area and the impurity concentration at the junction increase, so that there is a problem that the collector-base capacitance increases. Fifth, the external base layer 41 and the low-concentration n-type silicon
Since the germanium layer 39 is in direct contact, the insulating film 3
There is a problem that the collector-base breakdown voltage is reduced due to crystal defects generated at the boundary with No. 4 and circuit characteristics are deteriorated.

Accordingly, an object of the present invention is to provide a bipolar transistor using a single crystal silicon-germanium layer as an intrinsic base layer, which has a low external base resistance, a small variation in base resistance, and a small capacitance between the collector and the base. An object of the present invention is to provide a bipolar transistor capable of high-speed operation, a method for manufacturing the same, an electronic circuit device using the bipolar transistor, and an optical communication system.

[0011]

A bipolar transistor according to the present invention comprises a single-crystal silicon layer of a first conductivity type (for example, a low-concentration n-type collector layer serving as a first collector region in FIG. 1); A first insulating film having an opening provided on the surface of the first conductivity type single crystal silicon layer, that is, a collector / base separation insulating film 4 and a second insulating film, that is, a second collector / base separation insulating film 5; A second conductive type polycrystalline layer having a conductivity type opposite to the first conductive type, that is, a base film 7 made of p-type polycrystalline silicon and a third insulating layer, that is, a multilayer film made of an emitter-base isolation insulating film 9; A first-conductivity-type single-crystal silicon-germanium layer provided in the opening, that is, a low-concentration n-type collector layer 16 made of single-crystal silicon-germanium; A p-type intrinsic base layer 18 of a second conductivity type single crystal silicon-germanium layer or a single crystal silicon-germanium provided on iodonium layer, wherein the second conductivity type single crystal silicon-germanium layer second
A second conductivity type polycrystalline silicon-germanium layer provided in contact with both the insulating film 5 and the second conductivity type polycrystalline layer 7, that is, a p-type external base layer 17 made of polycrystalline silicon-germanium. Have at least the first
The thickness of the conductive type single crystal silicon / germanium layer 16 is larger at the periphery than at the center of the opening.

In the bipolar transistor, the second conductive type base extraction layer may be a polycrystalline silicon layer or a polycrystalline silicon / germanium layer. Also,
The thickness of the thickest portion of the low concentration collector layer made of the first conductivity type single crystal silicon / germanium, ie, FIG.
In other words, the thickness of the thickest portion around the low-concentration n-type collector layer 16 is at least 5 nm or more.

The second conductivity type single crystal silicon is provided on the second conductivity type single crystal silicon / germanium layer.
If a second second conductivity type single crystal layer having an impurity concentration lower than that of the germanium layer is further provided, that is, a structure in which the intrinsic base layer 18 and the base extraction layer 7 are joined by the external base layer 17 as shown in FIG. Is further provided with a low-concentration cap layer 25 made of a single crystal.
In this case, the second second conductivity type single crystal layer may be a single crystal silicon layer or a single crystal silicon / germanium layer.

Further, a second first conductivity type single crystal layer provided on the second conductivity type single crystal silicon-germanium layer, that is, as shown in FIG. 15, is formed on the intrinsic base layer 18 by epitaxial growth. It is characterized in that a single-crystal layer 27 serving as the formed emitter layer is further provided.
In this case, the second first conductivity type single crystal layer may be a single crystal silicon layer or a single crystal silicon / germanium layer.

In any one of the bipolar transistors, the second insulating film, that is, the second collector / base isolation insulating film 5 in FIG. 1 is a silicon nitride film, or the third insulating film The film, that is, the emitter-base isolation insulating film 9 in FIG. 1 is a silicon oxide film.

In any of the above bipolar transistors, the profile in which the composition ratio of germanium in the second conductivity type single crystal silicon-germanium layer decreases from the first conductivity type single crystal silicon layer side toward the surface, ie, As shown in FIG. 16 and FIG. 18, a characteristic is that the germanium composition ratio in the base has a profile that decreases from the collector side to the emitter side.

Alternatively, the first conductivity type single crystal silicon
The composition ratio of germanium in the germanium layer is the first ratio.
A profile in which the composition ratio increases from the conductivity type single crystal silicon layer side to the surface and the germanium composition ratio becomes constant on the surface side, that is, as shown in FIG. 20, the germanium composition ratio in the low concentration collector layer changes from the collector side to the emitter side. , And the profile may be such that the germanium composition ratio is constant on the base side in the low concentration collector layer.

Alternatively, the first conductivity type single crystal silicon
The composition ratio of germanium in the germanium layer is the first ratio.
It has a profile that increases from the conductivity type single crystal silicon layer side to the surface, that is, a profile in which the germanium composition ratio in the low concentration collector layer increases from the collector side to the emitter side as shown in FIG. And

Further, as the composition ratio of germanium in the second conductivity type single crystal silicon-germanium layer and the first conductivity type single crystal silicon-germanium layer increases from the first conductivity type single crystal silicon layer side toward the surface. Decreased,
The inclination in the first conductivity type single crystal silicon-germanium layer is smaller than the inclination in the second conductivity type single crystal silicon-germanium, that is, the inclination of the germanium composition ratio profile in the intrinsic base as shown in FIG. The inclination of the germanium composition ratio profile in the low-concentration n-type collector layer may be made smaller.

Alternatively, the second conductivity type single crystal silicon
A germanium layer and the first conductivity type single crystal silicon;
The composition ratio of germanium in the germanium layer decreases from the first conductivity type single crystal silicon layer side toward the surface, and the first conductivity type monocrystalline silicon / germanium has a first conductivity type lower than the inclination of the germanium composition ratio. Profile in which the inclination in the single-crystal silicon-germanium layer is small, and further, a region in which the germanium composition ratio increases from the first-conductivity-type single-crystal silicon side toward the surface in the first-conductivity-type single-crystal silicon, that is, FIG.
As shown in the figure, the germanium composition ratio in the intrinsic base decreases from the collector side to the emitter side, and the low concentration n
A profile in which the germanium composition ratio in the mold collector layer initially increases from the collector side to the emitter side and decreases in the middle.

According to the method of manufacturing a bipolar transistor of the present invention, a first insulating film, a second insulating film, and a second conductive film having a conductivity type opposite to the first conductivity type are formed on a surface of a single conductivity type single crystal silicon layer. Forming a multilayer film comprising a polycrystalline layer and a third insulating layer, providing an opening in the multilayer film, and providing a first conductivity type single crystal silicon / germanium layer in the opening; Providing a second-conductivity-type single-crystal silicon-germanium layer on the first-conductivity-type single-crystal silicon-germanium layer;
Providing a germanium layer in contact with any of the second conductivity type single crystal silicon-germanium layer and the second conductivity type polycrystalline layer, wherein the first conductivity type single crystal The step of increasing the thickness of the silicon-germanium layer in the peripheral portion than the center of the opening and providing the second conductivity type single-crystal silicon-germanium layer is a step of forming by epitaxial growth, The method is characterized in that the epitaxial growth is performed under the condition that the temperature during the growth is 500 ° C. to 800 ° C. and the pressure during the growth does not exceed 100 Pa (Pascal).

Further, an electronic circuit device or an optical communication device according to the present invention is characterized by using a bipolar transistor having any one of the above structures. Further, an optical communication system according to the present invention includes a light receiving element that receives an optical signal and outputs an electric signal, a first amplifier circuit that receives the electric signal from the light receiving element, and receives an output of the first amplifier circuit. An optical receiving system including a second amplifier circuit and a discriminator that converts an output of the second amplifier circuit into a digital signal in synchronization with a predetermined clock signal, wherein the first amplifier circuit includes: A first bipolar transistor having a base connected to a light receiving element, and a second bipolar transistor having a base connected to the collector of the first bipolar transistor and having a collector connected to an input of the second amplifier circuit And at least one of the first and second bipolar transistors is constituted by the bipolar transistor according to any of the above. It is a symptom. In that case, the first
And the second bipolar transistor is formed on a single semiconductor chip, and the semiconductor chip and the light receiving element are mounted on a single substrate.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the bipolar transistor according to the present invention, a peripheral portion is formed only in an opening of a first insulating film formed in a first collector region on a silicon substrate. A second collector layer made of low-concentration single-crystal silicon / germanium having a thickness larger than that of the central portion, and a base extraction layer made of polycrystalline silicon; and a second collector layer. It has a structure provided above and in contact with an intrinsic base region made of single crystal silicon / germanium via an external base layer made of polycrystalline silicon / germanium.

By providing the low-concentration collector layer having a large thickness only in the peripheral portion between the intrinsic base made of a single-crystal silicon-germanium layer and the first collector layer, the distance between the intrinsic base and the base extraction layer is increased. As the intrinsic base approaches, the intrinsic base and the base extraction layer are connected from the initial stage of the formation of the intrinsic base, and the contact area between the intrinsic base and the external base is increased, so that the variation of the base resistance at the joint portion is reduced and the base resistance is reduced. Can be reduced.

In addition, since the thickness at the periphery of the low concentration collector layer increases, the capacitance between the collector and the base can be reduced. In addition, since the contact area between the intrinsic base and the external base increases, the intrinsic base and the external base can be connected without increasing the contact resistance even if the length of the extension of the base extraction layer is shortened. The capacity between bases can be reduced. In addition, since the emitter and the base are formed in a self-aligned manner, the capacitance between the emitter and the base can be reduced. Therefore, the bipolar transistor according to the present invention can operate at high speed.

In a preferred embodiment of the method for manufacturing a bipolar transistor according to the present invention, the temperature at which single crystal silicon / germanium of the intrinsic base layer and the low-concentration cap layer constituting the bipolar transistor are formed by epitaxial growth. Is 500 ° C or more and 800
C. or lower and the pressure at the time of formation does not exceed 100 Pa.

When single crystal silicon / germanium is grown on single crystal silicon by performing epitaxial growth under such conditions, depending on the composition ratio of germanium and the grown film thickness, single crystal silicon or single crystal silicon / germanium may be formed. Deposits a single-crystal silicon-germanium layer, but prevents polycrystalline silicon-germanium from depositing on the silicon oxide film and the silicon nitride film. Therefore, when forming the low-concentration collector layer, polycrystalline silicon-germanium is not deposited on the collector-base isolation oxide film and the emitter-base isolation insulating film, but only on the first collector layer. Single crystal silicon / germanium can be formed, and the distance between the intrinsic base and the base extraction layer can be reduced from the initial stage of growth of the intrinsic base.

By replacing the bipolar transistors used in various electronic circuit devices and optical communication systems with the bipolar transistors as described above, electronic circuit devices and optical communication systems capable of high-speed operation can be realized.

In a preferred embodiment of the optical communication system according to the present invention, a light receiving element for receiving an optical signal and outputting an electric signal, a first amplifier circuit for receiving an electric signal from the light receiving element, An optical receiving system comprising: a second amplifier circuit receiving an output of the amplifier circuit of (1); and a discriminator for converting an output of the second amplifier circuit into a digital signal in synchronization with a predetermined clock signal. Is a first bipolar transistor whose base is connected to the light receiving element, and a second bipolar transistor whose base is connected to the collector of the first bipolar transistor and whose collector is connected to the input of the second amplifier circuit. And a bipolar transistor of
At least one of the first and second bipolar transistors is constituted by any of the bipolar transistors described above. Thereby, a high-speed optical receiving system can be realized.

<Embodiment 1> Next, a specific example of an optical communication system which is an example of a bipolar transistor according to the present invention, a method of manufacturing the same, and a circuit device / system using the bipolar transistor will be described with reference to the accompanying drawings. This will be described in detail with reference to FIG. FIG. 1 is a sectional structural view of a first embodiment of a bipolar transistor according to the present invention.
Hereinafter, an outline of a manufacturing process of the bipolar transistor having the structure shown in FIG. 1 will be described.

First, a low-concentration n-type collector layer 3 is epitaxially grown on the entire surface of a p-type silicon substrate 1 having a high-concentration n-type buried layer 2 formed in the emitter and collector regions. Next, a first collector comprising a silicon oxide film is formed.
A base isolation insulating film 4 and a second collector / base isolation insulating film 5 made of a silicon nitride film are deposited, and an opening is formed in the collector portion.

Next, a collector lead layer 8 made of polycrystalline silicon, a base lead layer 7 made of polycrystalline silicon around the opening of the emitter, and an emitter / base separation insulating film 9 made of a silicon oxide film are formed. A portion is opened, and phosphorus as an n-type dopant is implanted into the opening by ion implantation to form a high-concentration n-type collector lead layer 6.

Next, openings of the first collector / base isolation insulating film 4, the second collector / base isolation insulating film 5, the base lead layer 7, and the emitter / base isolation insulating film 9 are formed. The low-concentration n-type collector layer 1 made of single-crystal silicon / germanium is formed in the opening thus formed.
6. p-type intrinsic base layer 18 made of single-crystal silicon / germanium; p-type intrinsic base layer 18 made of polycrystalline silicon / germanium
The mold external base layer 17 is formed.

Next, the emitter / base isolation insulating film 19,
After covering the external base 17 with 20, an emitter extraction layer 21 made of high-concentration n-type polycrystalline silicon is deposited, and an impurity is diffused into the single-crystal silicon-germanium layer by annealing, thereby forming an emitter region 22. (Detailed manufacturing process of the active region of the bipolar transistor
This will be described later with reference to FIGS. Next, an insulating film 23 is formed thereon.
Then, openings are formed in the emitter, base, and collector portions of the insulating film, and finally, electrodes 24 are formed in the emitter, base, and collector openings. In the bipolar transistor, polycrystalline silicon / germanium may be used for the base extraction layer 7. The same applies to these layers in the following examples.

FIG. 2 shows the germanium composition ratio and the impurity profile of the bipolar transistor of this embodiment formed as described above, and FIG. 3 shows the energy band structure. As can be seen from FIG. 2A, germanium is contained not only in the base layer but also in the collector region. As a result, as shown in FIG. 3, the energy barrier due to the difference in the band gap between silicon and silicon germanium is included in the depletion layer between the collector and the base, and the carriers injected from the emitter are affected by the barrier. You can reach the collector without receiving it.

In FIG. 2B, the emitter region has an impurity concentration of phosphorus (P), the base region has an impurity concentration of boron (B), and the low-concentration n-type collector region has an impurity concentration of phosphorus (P). The high-concentration n-type buried layer shows the impurity concentration of arsenic (As). The same applies to the diagram of the impurity profile below.

FIG. 4, FIG. 5, and FIG. 6 are detailed views for explaining a manufacturing process of an active region which is a main part of the bipolar transistor of this embodiment. First, as shown in FIG. 4A, a low-concentration n-type collector layer 3 made of single-crystal silicon is formed on the high-concentration n-type buried layer 2 by epitaxial growth. Next, a first collector / base isolation insulating film 4 made of a silicon oxide film, a second collector / base isolation insulating film 5 made of a silicon nitride film, and polycrystalline silicon (or polycrystalline silicon / germanium) are formed. Base extraction layer 7 and first silicon oxide film
Is formed, and a second emitter-base isolation insulating film 10 made of a silicon nitride film is formed.

Next, as shown in FIG. 4B, the emitter / base isolation insulating films 9, 10 and 10 are anisotropically etched.
Openings are formed in the base extraction layer 7 and the collector / base isolation insulating film 5, and an insulating film 11 made of a silicon nitride film and an insulating film 12 made of a silicon oxide film are formed on side walls of the opening. By implanting, the second low concentration collector region 13 is formed only in the region of the opening.

Next, as shown in FIG. 4C, a silicon nitride film is deposited only in the opening by depositing a silicon nitride film in the opening and performing anisotropic etching. Here, the silicon nitride film 14 may be formed by using a silicon nitride film deposition and a chemical mechanical polishing method.
The same applies to these portions in the following embodiments.

Next, the silicon oxide film 12 is removed from the surface by isotropic etching to form an opening 15, and subsequently, the collector / base isolation insulating film 4 made of a silicon oxide film is partially etched. By removing, as shown in FIG. 5A, the surface of the low-concentration n-type collector layer 3 is exposed only around the opening.

Next, as shown in FIG. 5B, after the silicon nitride film 14 is removed by etching, the island 4a of the low-concentration n-type collector layer is epitaxially grown by using the island 4a of the silicon oxide film as a mask. Form. At this time, the difference between the growth start time of single crystal silicon / germanium on single crystal silicon and the growth start time of polycrystalline silicon / germanium on insulating film, and the desorption reaction of silicon on silicon oxide film and silicon nitride film Utilizing the presence or absence, on the island 4a of the silicon oxide film, on the first collector / base isolation insulating film 4, and on the first
The second collector-base isolation made of the silicon nitride film and the side wall of the base extraction layer 7 made of polycrystalline silicon (or polycrystalline silicon germanium) without depositing the polycrystalline silicon germanium on the base isolation insulating film 9 The growth is performed under the condition that the polycrystalline silicon / germanium layer is deposited only on the side wall of the insulating film 5.

For example, when the epitaxial growth temperature is 650
° C. and the growth pressure is 1 Pa, the thickness of the single crystal silicon / germanium which grows on the single crystal silicon before the polycrystalline silicon / germanium starts to be deposited on the silicon oxide film and the silicon nitride film, that is, the selective growth FIG. 7 shows the relationship between the critical film thickness and the composition ratio of germanium contained in single-crystal silicon-germanium.

In the figure, (a) is a film thickness of a single crystal silicon / germanium which grows on a single crystal silicon before polycrystalline silicon / germanium starts to be deposited on a silicon nitride film (critical film thickness for selective growth). (B) shows the film thickness (critical film thickness for selective growth) of single-crystal silicon-germanium which grows on single-crystal silicon before polycrystalline silicon-germanium starts to be deposited on the silicon oxide film. As can be seen from FIG. 7, the case of only silicon (Ge
Even if the composition ratio is 0%), if the thickness of the single crystal silicon grown on the single crystal silicon is 100 nm or less, no polycrystalline silicon is deposited on the silicon oxide film and the silicon nitride film, and the thickness of the single crystal silicon Is from 100 nm to 150 nm
During this period, no polycrystalline silicon is deposited on the silicon oxide film, and polycrystalline silicon starts to be deposited only on the silicon nitride film.

In the case of silicon germanium (G
The critical film thickness increases as the germanium composition ratio increases, and when the Ge composition ratio is 30%, even if single-crystal silicon / germanium of about 200 nm grows on single-crystal silicon, silicon oxide is not oxidized. No polycrystalline silicon / germanium is deposited on the film and the silicon nitride film, and the thickness of the single crystal silicon / germanium is 200 nm.
In the range from to 300 nm, no polycrystalline silicon / germanium is deposited on the silicon oxide film, but only on the silicon nitride film.

Therefore, as shown in FIG. 5B, even if a low-concentration collector layer having a thickness equal to or less than the critical thickness (b) for the silicon oxide film is selectively grown, the low-concentration polycrystalline silicon.
Germanium is deposited on the low-concentration n-type collector layer 3 made of single-crystal silicon, but is not deposited on the side wall of the collector-base isolation insulating film 4 made of a silicon oxide film and on the emitter-base isolation insulating film 9.

In order to perform such a growth, a gas source MBE (Molecular Beam Epitaxy) method or a CVD method is used.
A (Chemical Vapor Deposition) method can be used, but the CVD method is more preferable because the selectivity is well controlled. The temperature range is 500 ° C. or higher, at which the selectivity between the silicon oxide film and the silicon nitride film and the single crystal silicon can be favorably obtained.
It is in the range of 00 ° C or less. In this temperature range, the growth pressure may be 100 Pa or less at which the polycrystalline silicon / germanium layer starts growing on the silicon oxide film or the silicon nitride film.

In the selective growth, chlorine gas (Cl) is used.
Alternatively, it can be realized by supplying hydrochloric acid gas (HCl) during growth. For example, when the epitaxial growth temperature is 650 ° C. and the growth pressure is 10000 Pa, the ratio of the HCl flow required to prevent polycrystalline silicon / germanium from depositing on the silicon oxide film and the silicon nitride film as indicated by the total raw material gas flow is FIG. 8 shows the relationship between the composition ratios of germanium contained in crystalline silicon / germanium.

In FIG. 5, (a) shows a region where the HCl flow rate required for depositing polycrystalline silicon germanium on the silicon oxide film and the silicon nitride film is shown by the total source gas flow rate. ) Indicates a region where the ratio of HCl flow required to prevent polycrystalline silicon-germanium from being deposited only on the silicon nitride film and from depositing polycrystalline silicon-germanium on the silicon oxide film is represented by the total source gas flow, (C) shows a region of the ratio of the HCl flow necessary for preventing the deposition of polycrystalline silicon / germanium on the silicon oxide film and the silicon nitride film to the total source gas flow.

As can be seen from FIG. 8, even in the case of silicon alone (Ge composition ratio = 0%), the HCl flow rate is set to 50% or more of the total source gas flow rate, so that the silicon oxide film and the silicon nitride film are not formed. No polycrystalline silicon is deposited,
In the range of 30 to 50%, polycrystalline silicon is deposited only on the silicon nitride film, and no polycrystalline silicon is deposited on the silicon oxide film, and when it is less than 30%, it is deposited on both the silicon nitride film and the silicon oxide film. Polycrystalline silicon is deposited.

In the case of silicon germanium (G
e composition ratio ≠ 0%), the HCl flow rate may be smaller as the composition ratio of germanium is increased.
By setting the flow rate to 20% or more of the total source gas flow rate, no polycrystalline silicon / germanium is deposited on the silicon oxide film and the silicon nitride film. Crystalline silicon is deposited, no polycrystalline silicon is deposited on the silicon oxide film, 10%
If it is less than 1, polycrystalline silicon is deposited on both the silicon nitride film and the silicon oxide film.

In order to perform such growth, a gas source MBE method or a CVD method can be used, but the CVD method is more preferable because the selectivity is well controlled. Further, the temperature range is 500 ° C. at which the selectivity between the silicon oxide film and the silicon nitride film and the single crystal silicon can be favorably obtained.
As described above, the upper limit is in a range of 800 ° C. or less at which crystal defects begin to occur.

Next, the island 4a of the silicon oxide film is removed by etching to expose the surface of the low-concentration n-type collector layer 3 at the center of the opening, and then single-crystal silicon / germanium is selectively grown again to form a bipolar transistor. A low-concentration n-type collector layer 16b is formed at the center of the opening serving as the intrinsic portion of the substrate. When the intrinsic base layer 18 made of single-crystal silicon / germanium doped with impurities at a high concentration is formed, an external base layer made of polycrystalline silicon / germanium is further formed on the external base layer 17a with the growth of the single-crystal silicon / germanium. 17b are formed, and the intrinsic base layer 18 is formed from the initial growth.
And the base extraction layer 7 are connected to the external base layer 17 (17a, 1
7b). For example, when the epitaxial growth temperature is 600 ° C. and the growth pressure is 1 Pa, the critical thickness of the selective growth on the silicon oxide film and the silicon nitride film and the composition ratio of germanium contained in single crystal silicon / germanium are determined. FIG. 9 shows the relationship.

In FIG. 9, (a) shows a critical film thickness for selective growth on a silicon nitride film, and (b) shows a critical film thickness for selective growth on a silicon oxide film. As can be seen from FIG. 9, even in the case of only silicon (Ge composition ratio = 0%),
The thickness of the single crystal silicon grown on the single crystal silicon is 5
At 0 nm or less, polycrystalline silicon is deposited on the silicon nitride film, but no polycrystalline silicon is deposited on the silicon oxide film. That is, selective growth is possible.

In the case of silicon germanium (G
e, the critical film thickness increases as the composition ratio of germanium increases, and when the composition ratio is 30%, even if single-crystal silicon / germanium of about 20 nm grows on single-crystal silicon, the silicon oxide film is formed. No polycrystalline silicon / germanium is deposited on the film and the silicon nitride film. Continue to grow further on single crystal silicon
When single-crystal silicon-germanium of 150 nm is grown, polycrystalline silicon is deposited on the silicon nitride film, but no polycrystalline silicon-germanium is deposited on the silicon oxide film. Therefore, by selectively growing the intrinsic base layer in this range, polycrystalline silicon / germanium can be prevented from being deposited on the emitter / base isolation insulating film 9 made of a silicon oxide film (FIG. 5C).
reference).

In order to perform such growth, a gas source MBE method or a CVD method can be used, but the CVD method is more preferable because the selectivity is well controlled. Further, the temperature range is 500 ° C. at which the selectivity between the silicon oxide film and the silicon nitride film and the single crystal silicon can be favorably obtained.
As described above, the upper limit is in a range of 800 ° C. or less at which crystal defects begin to occur. In this temperature range, the growth pressure may be 100 Pa or less at which the polycrystalline silicon / germanium layer starts growing on the silicon oxide film or the silicon nitride film.

Next, as shown in FIG. 6A, the second emitter-base isolation insulating film 19 and the third emitter-base isolation insulating film 20 are formed so as to cover the external base layer 17b.
To form Next, as shown in FIG. 6B, after an opening of the second emitter / base isolation insulating film 19 is formed,
A high-concentration n-type polycrystalline silicon 21 serving as a diffusion source of an emitter and an emitter extraction layer 21 is deposited and annealed to diffuse an n-type impurity into a single-crystal silicon-germanium layer (intrinsic base layer) 18 to form an emitter region. 2
2 is formed, and at the same time, p-type impurities are diffused from the base extraction layer 7 to the low concentration portion 17a of the external base layer, and the intrinsic base layer 18 is electrically connected. Thereafter, an insulating film 23 is deposited, openings are formed in the respective regions of the emitter, the base and the collector, and the electrode 24 is formed. As described above, FIG.
Can be obtained.

As in this embodiment, n-type single crystal silicon
By increasing the thickness of the germanium layer 16 at the periphery of the opening than at the center of the opening, the base resistance and the collector / collector resistance are increased.
Since the capacitance at the base interface can be reduced, a high-speed bipolar transistor having a cutoff frequency fT and a maximum oscillation frequency fmax of 50 GHz or more can be realized.
Further, since the variation in the base resistance can be reduced, it is possible to increase the speed and performance of a circuit device and a system using the bipolar transistor.

<Embodiment 2> FIG. 10 is a sectional structural view of a bipolar transistor according to a second embodiment of the present invention. The manufacturing process of the bipolar transistor having the structure of this embodiment is as follows. As in the first embodiment described above,
Forming a high-concentration n-type buried layer 2, a first low-concentration n-type collector layer 3, a first collector / base isolation insulating film 4, and a second collector / base isolation insulating film 5 on a silicon substrate 1; A polycrystalline silicon layer 8 serving as a collector electrode is deposited only in the collector region, and a high-concentration n-type collector lead layer 6 is formed by ion implantation.

Next, a base extraction layer 7 and a first emitter / base isolation insulating film 9 are deposited, and an opening is formed only in the emitter region. Next, an insulating film is formed on the side wall of the base extraction layer 7, and an n-type impurity is ion-implanted to form the second low-concentration collector layer 13. Next, a silicon nitride film is formed only in the opening, the side wall is removed by isotropic etching, and the silicon nitride film in the opening is removed, thereby forming a silicon oxide film island on the low-concentration n-type collector 3. Form.

The difference from the first embodiment shown in FIG. 1 is that when the low concentration n-type collector layer is formed, polycrystalline silicon germanium is formed on the side walls of the base extraction layer 7 and the collector / base isolation insulating film 5. That is, do not deposit. For example, when the epitaxial growth temperature is 575 ° C. and the growth pressure is 1 Pa, the thickness of single-crystal silicon-germanium that grows on single-crystal silicon before the start of deposition of polycrystalline silicon-germanium on polycrystal silicon, that is, selective growth FIG. 11 shows the relationship between the critical film thickness and the composition ratio of germanium contained in single crystal silicon / germanium.
Shown in

As can be seen from FIG. 11, even when only silicon is used (Ge composition ratio = 0%), if the thickness of the single crystal silicon grown on the single crystal silicon is 5 nm or less, the polycrystal silicon is not Does not accumulate. In the case of silicon-germanium (Ge composition ratio ≠ 0%), the film thickness increases as the composition ratio of germanium increases,
At a composition ratio of 30%, even if single-crystal silicon-germanium of about 40 nm grows on single-crystal silicon, no polycrystalline silicon-germanium is deposited on polycrystalline silicon. Therefore, even if a low-concentration collector layer having a thickness equal to or less than the critical thickness is selectively grown, low-concentration polycrystalline silicon / germanium is not deposited on the side wall of the base extraction layer 7.

In order to perform such a growth, a gas source MBE method or a CVD method can be used, but the CVD method is more preferable because the selectivity is well controlled. Further, the temperature range is 500 ° C. at which the selectivity between the silicon oxide film and the silicon nitride film and the single crystal silicon can be favorably obtained.
As described above, the upper limit is in a range of 800 ° C. or less at which crystal defects begin to occur. In this temperature range, the growth pressure may be 100 Pa or less at which the polycrystalline silicon / germanium layer starts growing on the side wall of the base extraction layer 7.

Then, an intrinsic base layer 1 made of single crystal silicon / germanium doped with impurities at a high concentration.
8 is formed, the total thickness of the low-concentration collector layer 16 and the intrinsic base layer 18 is made equal to or more than the critical thickness for selective growth,
As the single-crystal silicon-germanium grows, the doped polycrystalline silicon-germanium is deposited from the side wall of the base extraction layer 7 to form the outer base layer 1.
7 is formed, and the intrinsic base layer 18 and the base extraction layer 7 are formed.
Are connected via only the external base layer 17 doped with impurities.

Then, after the outer base layer 17 is covered with the third emitter / base isolation insulating films 19 and 20, the emitter extraction layer 21 made of high-concentration n-type polycrystalline silicon is formed.
Is deposited, and annealing is performed to form an emitter region 2.
Form 2 Finally, an insulating film 23 is deposited in the same manner as in the first embodiment, openings are formed in the emitter, base and collector portions, and an electrode 24 is formed. Thereby, a bipolar transistor having the cross-sectional structure shown in FIG. 10 can be obtained.

According to this embodiment, in addition to the effect of the above-described first embodiment, the base resistance is reduced because the intrinsic base layer 18 and the base extraction layer 7 are connected only by the doped polycrystalline silicon / germanium. As a result, the bipolar transistor can operate at a higher speed, and the characteristics of a circuit using the bipolar transistor can be improved.

<Embodiment 3> FIG. 12 is a sectional structural view of a third embodiment of the bipolar transistor according to the present invention. The manufacturing method of the bipolar transistor having the structure of the present embodiment is as follows.

As in the first embodiment, the silicon substrate 1
A high-concentration n-type buried layer 2, a first low-concentration n-type collector layer 3, a first collector / base separation insulating film 4, and a second collector / base separation insulating film 5 are formed thereon, and only the collector region is formed. A polycrystalline silicon layer (collector extraction layer 8) serving as a collector electrode is deposited on
A mold collector extraction layer 6 is formed. Next, a base extraction layer 7 and a first emitter / base isolation insulating film 9 are deposited, and an opening is formed only in the emitter region.

Next, an insulating film is formed on the side wall of the base extraction layer 7, and an n-type impurity is ion-implanted to form a second low concentration collector layer 11. Next, a silicon nitride film is formed only in the opening, the side wall is removed by isotropic etching, and the silicon nitride film in the opening is removed, thereby forming a silicon oxide film island on the low-concentration n-type collector 3. Then, a low concentration collector layer 16, an intrinsic base layer 18, and an external base layer 17 are formed.

The difference from the first embodiment shown in FIG. 1 is that the intrinsic base layer 18 made of high-concentration p-type silicon germanium is used.
A cap layer 25 made of low-concentration p-type silicon
And a low-concentration p-type polysilicon layer 2 on the external base layer 17 made of p-type polysilicon / germanium.
6 is selectively growing. Then, after the outer base layers 17 and 26 are covered with the emitter / base isolation insulating films 19 and 20, an emitter extraction layer 21 made of high-concentration n-type polycrystalline silicon is deposited and annealed to form a low-concentration cap layer 25. An emitter region 22 is formed therein. Finally, the insulating film 2 is formed in the same manner as in the first embodiment.
3 are formed, openings are formed in the emitter, base and collector portions, and the electrode 24 is formed. As a result, FIG.
A bipolar transistor having the cross-sectional structure shown in FIG. In the bipolar transistor, single crystal silicon / germanium may be used for the low concentration cap layer. The same applies to this layer in the following examples.

In this embodiment, since the low-concentration cap layer 25 is provided on the intrinsic base layer 18, the impurity concentration at the emitter-base junction is lower than that in the first embodiment (FIG. 13A). b)). As a result, tunnel current at the emitter-base junction can be reduced. Further, since the band gap on the base side of the emitter-base interface is smaller than that on the emitter side, the energy barrier for holes injected from the base to the emitter is larger than the energy barrier for electrons injected from the emitter to the base. (See FIG. 14). Therefore, the current amplification factor of the bipolar transistor increases.

According to this embodiment, in addition to the effects of the first embodiment, the current amplification factor of the bipolar transistor can be improved, so that the bipolar transistor can operate at a higher speed. Further, since the impurity concentration at the emitter-base junction can be reduced, the breakdown voltage between the emitter and the base can be increased, and the characteristics of a circuit using this bipolar transistor can be improved.

<Embodiment 4> FIG. 15 is a sectional structural view of a fourth embodiment of the bipolar transistor according to the present invention. The manufacturing method of the bipolar transistor having the structure of the present embodiment is as follows.

An emitter opening, a low-concentration n-type collector layer 16, a p-type intrinsic base layer 18, and a p-type external base layer 17 are formed in the same manner as in the first embodiment. p
After forming the emitter / base isolation insulating films 19 and 20 so as to cover the mold external base layer 17, an emitter layer 27 is formed by epitaxial growth, and then the high-concentration n-type polycrystalline silicon which becomes the emitter extraction layer 21 and the insulating film 23 are formed. Is deposited, and openings are formed in the emitter, base and collector portions of the insulating film to form the electrode 24. Thus, a bipolar transistor having the cross-sectional structure shown in FIG. 15 can be obtained.

In this embodiment, the leakage current in the base region can be reduced by reducing the impurity concentration in the emitter layer at the emitter-base interface, and the same effect as in the third embodiment can be obtained. . Further, since the emitter layer is formed by epitaxial growth, the controllability of the impurity concentration and the film thickness in the emitter layer is improved, and the variation in transistor performance can be reduced. further,
In this embodiment, since the area of the interface between the emitter and the base can be reduced, the capacitance between the emitter and the base can be reduced, and the characteristics of a circuit using this transistor can be improved.

<Embodiment 5> FIGS. 16A and 16B show a fifth embodiment of a bipolar transistor according to the present invention. FIG. 16A shows a germanium composition ratio of the bipolar transistor, and FIG. It is a characteristic diagram which shows a density profile, respectively. As the structure of the bipolar transistor used in the present embodiment, those shown in FIG. 1, FIG. 10, FIG. 12, and FIG. 15 are all applicable. For reference numerals in the following description, for example, see the cross-sectional structure diagram of FIG. This is the same as in Examples 6 to 1 described later.
The same applies to 0.

The germanium composition ratio in the intrinsic base layer of the bipolar transistor of this embodiment is shown in FIG.
As shown in FIG. 16B, the impurity concentration becomes smaller from the collector side to the emitter side, and has an impurity concentration profile as shown in FIG. FIG. 17 shows the energy band structure at this time. As can be seen from FIG. 17, in the base layer, the energy band can be inclined in accordance with the germanium composition ratio.

Thus, the carriers injected from the emitter are accelerated in the base layer by the electric field caused by the inclined energy band, so that the bipolar transistor can operate at a higher speed. As a result, by using this transistor, the first and second embodiments described above can be used.
In addition to the effects described in the second, third, and fourth embodiments, the characteristics of the circuit can be further improved.

<Embodiment 6> FIGS. 18A and 18B show a sixth embodiment of a bipolar transistor according to the present invention. FIG. 18A shows a germanium composition ratio of the bipolar transistor, and FIG. It is a characteristic diagram which shows a density profile, respectively. The structure of a bipolar transistor is
1, 10, 12, and 15 are all applicable, and the cross-sectional structure diagram is omitted as in the fifth embodiment.

As shown in FIG. 18A, the germanium composition ratio in the intrinsic base layer of the bipolar transistor according to the present embodiment is set to decrease from the collector side to the emitter side. Unlike this, the germanium composition ratio is not reduced to 0% on the emitter side. FIG. 19 shows the energy band structure at this time.

As can be seen from FIG. 19, in this embodiment,
In addition to the slope of the energy band of the base layer,
The energy barrier at the base junction is smaller. As a result, the carriers injected from the emitter are accelerated in the base layer by the electric field caused by the inclined energy band, and the injection of carriers from the emitter to the base increases, so that the bipolar transistor can operate at a higher speed. It becomes possible. As a result, by using this bipolar transistor, the characteristics of the circuit can be further improved in addition to the effect of the fifth embodiment.

<Embodiment 7> FIGS. 20A and 20B are views showing a seventh embodiment of a bipolar transistor according to the present invention, wherein FIG. 20A shows the germanium composition ratio of the bipolar transistor, and FIG. It is a characteristic diagram which shows a density profile, respectively. The structure of a bipolar transistor is
1, 10, 12, and 15 are all applicable, and the cross-sectional structure diagram is omitted as in the fifth embodiment.

As shown in FIG. 20A, a region where the germanium composition ratio in the low-concentration n-type collector layer of the transistor of this embodiment increases from the collector side toward the emitter side is provided. FIG. 21 shows the energy band structure at this time. As can be seen from FIG.
There is no energy barrier in the depletion layer between the collector and the base. Thereby, the carriers injected from the emitter are accelerated by the depletion layer without being affected by the energy barrier at all, and reach the collector layer, so that the bipolar transistor can operate at higher speed. as a result,
By using this bipolar transistor, the characteristics of the circuit can be further improved in addition to the effect of the sixth embodiment.

<Embodiment 8> FIGS. 22A and 22B are views showing an eighth embodiment of a bipolar transistor according to the present invention. FIG. 22A shows the germanium composition ratio of the bipolar transistor, and FIG. It is a characteristic diagram which shows a density profile, respectively. The structure of a bipolar transistor is
1, 10, 12, and 15 are all applicable, and the cross-sectional structure diagram is omitted as in the fifth embodiment.

As shown in FIG. 22A, the composition ratio of germanium in the low-concentration n-type collector layer of the transistor of this embodiment increases from the collector side to the emitter side. FIG. 23 shows the energy band structure at this time. As can be seen from FIG. 23, similarly to the seventh embodiment, since no energy barrier is generated in the depletion layer between the collector and the base, the carriers injected from the emitter are not affected by the energy barrier at all. It is accelerated by the depletion layer and can reach the collector layer, so that the bipolar transistor can operate at higher speed.

The point of difference from the above-mentioned Example 7 is that the germanium composition ratio on the collector side is set to be equal to or less than the maximum amount in which defects caused by distortion do not enter the low-concentration n-type collector layer and the intrinsic base layer. Can be reduced. As a result, by using this bipolar transistor, the characteristics of the circuit can be further improved in addition to the effect of the seventh embodiment.

<Embodiment 9> FIGS. 24A and 24B show a ninth embodiment of a bipolar transistor according to the present invention. FIG. 24A shows a germanium composition ratio of the bipolar transistor, and FIG. It is a characteristic diagram which shows a density profile, respectively. The structure of a bipolar transistor is
1, 10, 12, and 15 are all applicable, and the cross-sectional structure diagram is omitted as in the fifth embodiment.

As shown in FIG. 24A, the germanium composition ratio in the intrinsic base layer and the low-concentration n-type collector layer of the bipolar transistor of this embodiment is set to decrease from the collector side toward the emitter side. . FIG. 25 shows the energy band structure at this time. As can be seen from FIG. 25, the energy band can be inclined in the depletion layer between the collector and the base in addition to the inclination of the energy band in the base layer, and the leak current due to crystal defects can be reduced. As a result, by using this bipolar transistor, the characteristics of the circuit can be further improved in addition to the effects of the sixth embodiment.

<Embodiment 10> FIGS. 26A and 26B show a tenth embodiment of a bipolar transistor according to the present invention. FIG. 26A shows a germanium composition ratio of the bipolar transistor, and FIG. It is a characteristic diagram which shows a density profile, respectively. As the structure of the bipolar transistor, all of those shown in FIGS. 1, 10, 12, and 15 can be applied, and a cross-sectional structure diagram is omitted as in the fifth embodiment.

As shown in FIG. 26A, the germanium composition ratio in the intrinsic base layer and the low-concentration n-type collector layer of the bipolar transistor of this embodiment increases from the collector side to the emitter side and decreases in the middle. After that, the profile decreases even in the intrinsic base. FIG. 27 shows the energy band structure at this time.

As can be seen from FIG. 27, the carriers injected from the emitter are accelerated in the intrinsic base, and are further accelerated in the depletion layer between the collector and the base by the change in the band gap, and the energy barrier is also increased. not exist. As a result, by using this bipolar transistor, the characteristics of the circuit can be further improved in addition to the effects of the ninth embodiment.

<Embodiment 11> Next, an embodiment of an optical communication system using the bipolar transistor according to the present invention as described above will be described. FIG. 28 is a diagram showing an embodiment using the bipolar transistor according to the present invention, and is an example applied to a preamplifier circuit used in an optical communication system. As is well known, an optical communication system requires high-speed communication of several tens of Gbps, and its preamplifier circuit particularly requires high-speed operation. Therefore, by employing the bipolar transistor according to the present invention as a transistor constituting the preamplifier circuit, the performance of the entire preamplifier circuit can be significantly improved.

In FIG. 28, reference numeral 300 denotes a semiconductor integrated circuit that constitutes a preamplifier circuit formed on a single semiconductor substrate, and a photodiode PD is connected to an input terminal IN of the semiconductor integrated circuit 300. A decoupling capacitor 3 is provided between the power supply terminal 301 and the ground terminal 302.
03 is externally attached. The photodiode PD is a light receiving element that receives an optical signal transmitted through an optical transmission cable, and the decoupling capacitor 303 is a capacitor for short-circuiting an AC component between a power supply line and a ground line.

Bipolar transistors Q1 and Q2
Is a bipolar transistor constituting an amplifier circuit, and any of the bipolar transistors according to the present invention having the structure described in the first to tenth embodiments can be suitably used. The diode D1 is a diode for level shift, and may be formed by short-circuiting between the collector and base of the bipolar transistor according to the present invention.
If necessary, a plurality of diodes can be directly connected and applied. Also, if necessary, the output terminal OU
An output buffer circuit is inserted between T and the emitter of the transistor Q2.

The semiconductor integrated circuit 300 constituting the preamplifier circuit for the optical communication system of the present embodiment uses an optical signal transmitted through an optical transmission cable to transmit a photodiode PD.
Is input to the input terminal IN, and the input electric signal is input to the amplifying transistor Q1.
And Q2 to amplify and output from the output terminal OUT. By using any of the bipolar transistors according to the present invention described in the first to tenth embodiments, the preamplifier circuit of the present embodiment can realize a band characteristic of 40 GHz or more.

FIG. 29 is a sectional view of a front end module of an optical communication system in which the photodiode PD and the preamplifier circuit 300 are integrated on a mounting substrate.
In FIG. 29, reference numeral 401 denotes an optical fiber, 40
2 is a lens, 403 is a photodiode, 404 is FIG.
8 shows a semiconductor integrated circuit (hereinafter, referred to as a preamplifier circuit IC) in which the preamplifier circuit 300 described in FIG. 8 is formed.
7, the photodiode 403 and the preamplifier circuit IC 404 are connected to an output terminal 406 via a wiring 405 connecting these. The substrate 407 is housed in a hermetically sealed package 408 such as a metal case. Although not shown, FIG.
Are also mounted.

As described above, by configuring the photodiode 403 and the preamplifier circuit IC 404 constituting the front end in the same module, the signal path can be shortened, noise is less likely to occur, and the parasitic L component ( Inductor components) and C components (capacitance components) can also be kept small.

In the front end module shown in FIG. 29, an optical signal input from an optical fiber 401 is collected by a lens 402 and converted into an electric signal by a photodiode 403. This electric signal is amplified by the preamplifier circuit IC 404 through the wiring 405 on the substrate 407 and output from the output terminal 406.

FIG. 30 shows a transmission module 500 of the optical communication system. An electric signal 501 to be transmitted is input to a multiplexing circuit (MUX) 5001 and multiplexed, for example, at a ratio of 4: 1, and the output signal is transmitted to a driver 5002. The semiconductor laser LD5003 always outputs light of a constant intensity, and an external modulator 5004 driven by the driver 5002 absorbs or non-absorbs light according to the output of the driver 5002 and transmits the light to the optical fiber 502. ing. The transmission module shown in FIG. 30 is a so-called external modulation type.
Alternatively, it is possible to employ a direct modulation type that directly controls the light emission of the semiconductor laser LD. However, in general, transmission using the external modulation type does not spread the spectrum oscillation due to chirp, and has a high speed and a long period. Suitable for distance transmission.

FIG. 31 is an example of a block diagram of a multiplexing circuit (MUX) to which the bipolar transistor according to the present invention is applied. The electric signal input to the transmitter is converted into a signal with a high transmission speed by a multiplexing circuit (MUX), and then output to a laser driver. The multiplexing circuit itself has a well-known configuration, and thus details are omitted. By employing the transistor according to the present invention as a transistor constituting the multiplex circuit (MUX), the performance of the entire multiplex circuit can be significantly improved.

FIG. 32 is an example of a circuit diagram of a driver to which the bipolar transistor according to the present invention is applied. The driver amplifies the signal converted into a signal with a high transmission rate by the multiplexing circuit to an amplitude sufficient to drive the optical modulator, and outputs the signal to the optical modulator. Since the driver itself has a well-known configuration, the details are omitted. By employing the transistor according to the present invention as a transistor constituting the driver, the performance of the entire driver circuit can be significantly improved.

FIG. 33 shows an optical receiving type module 510 of the optical communication system using the preamplifier circuit 300 and the front end module shown in FIGS. 28 and 29. In the figure, reference numeral 520 indicates a front-end module unit.
21 and a preamplifier 522 for amplifying the output of the light receiver. The electric signal amplified by the preamplifier 522 is input to the main amplifier 530 and amplified.

The main amplifier section 530 is an automatic gain controller (hereinafter referred to as AGC) to which the output of the main amplifier 532 is fed back in order to keep the output constant while avoiding variations due to the optical transmission distance and manufacturing deviation. ) 531. The main amplifier section 530 may employ a limit amplifier for limiting the output amplitude, in addition to the configuration for adjusting the gain.
The discriminator 540 is configured to perform 1-bit analog-to-digital conversion in synchronization with a predetermined clock, digitizes the output of the main amplifier unit 530, and converts the output of the main amplifier unit 530 into a separation circuit (DM).
UX) 570, for example, the signal is separated into 1: 4 and input to the digital signal processing circuit 560 in the subsequent stage, where predetermined processing is performed.

The clock extracting section 550 is for forming a clock for controlling the operation timing of the discriminator 540 and the separating circuit (DMUX) 570 from the converted electric signal. Is rectified by a full-wave rectifier 551 and filtered by a filter 552 having a narrow band to extract a signal serving as a clock signal. The signal extracted by the filter 552 is input to the phase shifter 553. This phase shifter 553 is a phase shifter for adjusting the phase of the filter output and the analog signal, and delays the filter output based on a predetermined delay amount. The output of the phase shifter 553 is supplied to the discriminator 540 via the limit amplifier 554 and the separation circuit DMUX.
570 is input as a clock signal.

FIG. 34 is an example of a circuit diagram of an AGC 531 to which the bipolar transistor according to the present invention is applied. The signal converted into a voltage signal by the preamplifier is received, the signal is adjusted to a constant amplitude, and the signal is output to the clock extraction system and the discriminator. Since the AGC itself has a well-known configuration, details are omitted. By employing the transistor according to the present invention as a transistor constituting the AGC, the performance of the entire AGC can be significantly improved.

FIG. 35 is an example of a circuit diagram of a full-wave rectifier 551 to which the bipolar transistor according to the present invention is applied. With the function to wrap the input signal from its center value,
Outputs the 2nd harmonic. Since the full-wave rectifier itself is well known, details are omitted. By employing the transistor according to the present invention as a transistor constituting the full-wave rectifier, the performance of the entire full-wave rectifier can be significantly improved.

FIG. 36 is an example of a circuit diagram of a limit amplifier 554 to which the bipolar transistor according to the present invention is applied. The signal sent from the AGC to the clock extraction system is input to a limit amplifier through a full-wave rectifier and a filter. The limit amplifier outputs the clock signal to the discriminator after shaping the waveform of the signal and limiting the amplitude of the signal. Since the limit amplifier itself is well known, the details are omitted. By employing the transistor according to the present invention as a transistor constituting the limit amplifier, the performance of the entire limit amplifier can be significantly improved.

FIG. 37 is an example of a block diagram of a discriminator (540) to which the bipolar transistor according to the present invention is applied. The discriminator 540 has a function of converting the output of the AGC 531 into a digital signal and outputting a signal to the separation circuit (DMUX) 570 in synchronization with the clock supplied from the limit amplifier 554. It has a configuration. In FIG.
f. “ckt” is a cascode type differential amplifier circuit, “MS-F
"F" is a master-slave type flip-flop circuit,
“Selector” is a selector, “Wide Ban
d Amp. "" Indicates a broadband amplifier circuit, and "EF2" and "EF3" indicate level shifters.

FIG. 38 is an example of a circuit diagram of a selector used in the discriminator shown in FIG. 37. FIG. 39 is an example of a circuit diagram of a wideband amplifier circuit used in the discriminator shown in FIG.
0 is an example of a circuit diagram of a cascode type differential amplifier circuit used in the discriminator shown in FIG. 37, and FIG. 41 is a circuit diagram of a master-slave type flip-flop circuit used in the discriminator shown in FIG. One example is shown, and the details are omitted because each has a well-known circuit configuration. By employing the transistor according to the present invention as a transistor constituting such a discriminator, the performance of the discriminator as a whole can be significantly improved.

FIG. 42 is a block diagram of an isolation circuit (DMUX) 570 to which the bipolar transistor according to the present invention is applied. The separation circuit (DMUX) has a function of distributing the digital signal output from the discriminator to a plurality of parallel data channels having a low transmission speed. This separation circuit (DMU
By employing the transistor according to the present invention as the transistor constituting X), the performance of the entire separation circuit (DMUX) can be significantly improved.

As described in detail above, in the optical communication system, each circuit including the preamplifier 522, the main amplifier 532, and the limit amplifier 554 is provided with the present invention having the configuration described in the first to tenth embodiments. Such a bipolar transistor can be used. In particular, a circuit having a configuration shown in FIG. 28 can be used for each amplifier. The bipolar transistor according to the present invention manufactured according to the above embodiment has a cutoff frequency fT and a maximum cutoff frequency fT.
Since the high-speed operation is possible at a maximum of 100 GHz, a large-capacity signal of 40 Gbits per second can be transmitted and received at a high speed. By using the high-speed bipolar transistor according to the present invention, the performance of the entire system can be greatly improved.

Conventionally, for a circuit requiring such a high-speed operation, it is necessary to use an expensive GaAs transistor whose operation speed is faster than that of a silicon bipolar transistor. However, in the present invention, an inexpensive silicon bipolar transistor can be used for a circuit requiring such a high-speed operation, so that the cost of the entire optical communication system can be reduced.

Embodiment 12 Next, an embodiment in which the bipolar transistor according to the present invention is applied to another circuit will be described. FIG. 43 is a block diagram of a frequency divider to which the bipolar transistor according to the present invention is applied. It has a function of dividing a clock serving as an operation reference and providing it as a clock to a low-speed operation circuit.

FIG. 44 is an example of a circuit diagram of a clock input circuit used in the frequency divider shown in FIG. 43, and FIG.
43 shows an example of a circuit diagram of an inter-stage buffer circuit used in the frequency divider shown in FIG. 46. FIG. 46 shows an example of a circuit diagram of an output buffer circuit used in the frequency divider shown in FIG. Therefore, the details are omitted. By employing the transistor according to the present invention as a transistor constituting such a frequency divider, the performance of the entire frequency divider can be significantly improved.

<Thirteenth Embodiment> FIG. 47 is a diagram showing a thirteenth embodiment of a bipolar transistor according to the present invention, and is a block diagram of a mobile wireless portable device to which the bipolar transistor according to the present invention is applied. . In this embodiment,
The bipolar transistor according to the present invention described in the first to tenth embodiments constitutes each block of a mobile wireless portable device such as a low-noise amplifier 603, a synthesizer 606, and a PLL (Phase Locked Loop) 611. This is an example in which the present invention is applied to a circuit that performs the following.

Next, the operation of the mobile radio portable device of this embodiment shown in FIG. 47 will be described. First, the input from the antenna 601 is amplified by the low noise amplifier 603, and the
06 is oscillated from the oscillator 605, and the signal from the low noise amplifier 603 is down-converted to a lower frequency by the down mixer 604 using the signal oscillated from the oscillator 605. Further, the frequency emitted from the PLL 611 is oscillated from the oscillator 610, and the signal from the down mixer 604 is demodulated by the demodulator 609 using the signal oscillated from the oscillator 610, and the signal is processed by the baseband unit 613 that handles a lower frequency. Perform

The signal emitted from baseband unit 613 is modulated by modulator 612 using the signal from PLL 611, and further up-converted by up-mixer 608 to a high frequency based on the signal from synthesizer 606. Thereafter, the signal is amplified by the power amplifier 607 and transmitted from the antenna 601. Here, the switch 602 is a switch for switching between transmission and reception of a signal, and receives and transmits a control signal (not shown) from the baseband unit 613 to control its transmission and reception. Further, a speaker, a microphone, and the like (not shown) are connected to the baseband unit 613, and input and output of an audio signal are enabled.

The respective blocks shown in FIG. 47 constituting the mobile radio portable device of this embodiment, in particular, the blocks of the low noise amplifier 603, the synthesizer 606 and the PLL 611 are the same as those of the first to tenth embodiments. Each of the circuits can be configured by applying any of such bipolar transistors. Since the transistor according to the present invention can reduce the base resistance and the collector-base capacitance, the low noise amplifier 603 and the synthesizer 6
06 and the PLL 611 can achieve low noise and low power consumption. This makes it possible to realize a mobile wireless portable device that can be used for a long time with low noise as a whole system.

<Embodiment 14> FIG. 48 shows a bipolar transistor according to a fourteenth embodiment of the present invention.
FIG. 3 is a D flip-flop circuit diagram for a prescaler of a PLL of a mobile wireless portable device to which the bipolar transistor according to the present invention is applied. In the present embodiment, the bipolar transistor according to the present invention described in the above-described first to tenth embodiments will be described with reference to FIG.
Transistors 701 to 7 on the circuit shown in FIG. 8 (D flip-flop circuit for PLL prescaler)
12 is an example used.

The input signal, clock signal and output signal of this D flip-flop circuit have only two states of a high potential and a low potential. An input signal and an inverted input signal are input to terminals 719 and 720, respectively, and a clock signal and an inverted clock signal are input to terminals 721 and 722, respectively, and an output signal and an inverted output signal are obtained from terminals 723 and 724.

The current paths flowing through the current sources 717 and 718 are switched to one of the transistors 709 or 710 and 711 or 712, respectively, by the clock signal. Further, the on / off of the transistors 701 to 704 is determined by the input signal (719/720) and the clock signal (72).
1/722) and the potential at the lower end of the resistor caused by the current flowing through the resistors 713 and 714. In this circuit, the output signal (723/724) outputs an input value when the clock signal 721 changes from a low potential to a high potential, and otherwise retains the previous input value.

Each of the circuits can be formed by applying any of the bipolar transistors according to the present invention described in the first to tenth embodiments. Since the transistor according to the present invention can reduce the base resistance and the collector-base capacitance, the power consumption of the PLL of the mobile wireless portable device can be reduced.

As described above, the optical communication system, the frequency divider, the mobile radio portable device, and the like have been described as the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments.
It goes without saying that various design changes can be made without departing from the spirit of the present invention. For example, the bipolar transistor according to the present invention can be applied to all circuit devices and systems including the bipolar transistor, and the operation of the circuit device and system can be accelerated by replacing the bipolar transistor with the bipolar transistor according to the present invention. Can be.

As described above, according to the present embodiment,
Since the intrinsic base layer and the external base layer are connected regardless of the irregularities on the surface of the external base layer, the base resistance can be reduced and the collector-base capacitance can be reduced due to the large peripheral thickness of the low concentration collector layer As a result, high-speed operation of an electronic circuit device or a system using a bipolar transistor becomes possible. Further, since the variation in the base resistance can be reduced, the performance of the circuit operation can be improved. Furthermore, to form the emitter, collector and base in a self-aligned manner,
The capacitance between the emitter-base and the collector-base can be reduced, and high-speed operation of the circuit device using the bipolar transistor becomes possible.

That is, according to the bipolar transistor and the method of manufacturing the same according to the present invention, it is possible to reduce the emitter-base capacitance, the collector-base capacitance, the base resistance, and the variation of the base resistance. Thus, a bipolar transistor operable at high speed and high frequency can be configured. Therefore, by using the bipolar transistor according to the present invention in an electronic circuit device or system that requires high-speed operation, such as an optical communication system, the performance of the electronic circuit device and the entire system can be improved.

[0125]

As described above in detail, according to the present invention, a bipolar transistor capable of high-speed operation with a low external base resistance, a small variation in the base resistance, and a small collector-base capacitance is provided. Its manufacturing method,
An electronic circuit device and an optical communication system using the bipolar transistor can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a bipolar transistor according to the present invention.

2 is a characteristic diagram showing a germanium composition ratio and an impurity concentration profile of the bipolar transistor shown in FIG.

FIG. 3 is a diagram schematically showing an energy band structure of a bipolar transistor having the profile shown in FIG.

4 is a partially enlarged cross-sectional view showing a method of manufacturing the active region of the bipolar transistor shown in FIG. 1 according to the present invention in the order of steps.

FIG. 5 is a partially enlarged cross-sectional view sequentially showing the steps subsequent to FIG. 4;

FIG. 6 is a partially enlarged cross-sectional view sequentially showing the steps subsequent to FIG. 5;

FIG. 7 shows the maximum thickness and germanium composition ratio of single crystal silicon / germanium that can be selectively grown on a silicon oxide film and a silicon nitride film without depositing polycrystalline silicon / germanium at a growth temperature of 650 ° C. FIG. 4 is a characteristic diagram showing the relationship between

FIG. 8 shows a total HCl gas flow rate at which a single-crystal silicon-germanium can be selectively grown without depositing polycrystalline silicon-germanium on a silicon oxide film and a silicon nitride film at a growth temperature of 650 ° C. FIG. 4 is a characteristic diagram showing a relationship between a ratio to germanium and a germanium composition ratio.

FIG. 9 shows a maximum thickness and a germanium composition ratio of single crystal silicon / germanium which can be selectively grown on a silicon oxide film and a silicon nitride film without depositing polycrystalline silicon / germanium at a growth temperature of 600 ° C. FIG. 4 is a characteristic diagram showing the relationship between

FIG. 10 shows a second example of the bipolar transistor according to the present invention.
It is sectional drawing which shows Example of (a).

FIG. 11 shows the relationship between the maximum thickness of single-crystal silicon-germanium that can be selectively grown without depositing polycrystalline silicon-germanium on polycrystalline silicon and the germanium composition ratio at a growth temperature of 575 ° C. FIG. 6 is a characteristic diagram.

FIG. 12 shows a third example of the bipolar transistor according to the present invention.
It is sectional drawing which shows Example of (a).

13 is a characteristic diagram showing a germanium composition ratio and an impurity concentration profile of the bipolar transistor shown in FIG.

14 is a diagram schematically showing an energy band structure of the bipolar transistor having the profile shown in FIG.

FIG. 15 shows a fourth example of the bipolar transistor according to the present invention.
It is sectional drawing which shows Example of (a).

FIG. 16 shows a fifth example of the bipolar transistor according to the present invention.
FIG. 5 is a characteristic diagram showing germanium composition ratios and impurity concentration profiles showing Examples of the present invention.

FIG. 17 is a diagram schematically showing an energy band structure of the bipolar transistor having the profile shown in FIG.

FIG. 18 shows a sixth embodiment of the bipolar transistor according to the present invention.
FIG. 5 is a characteristic diagram showing germanium composition ratios and impurity concentration profiles showing Examples of the present invention.

19 is a diagram schematically showing an energy band structure of the bipolar transistor having the profile shown in FIG.

FIG. 20 shows a seventh embodiment of the bipolar transistor according to the present invention.
FIG. 5 is a characteristic diagram showing germanium composition ratios and impurity concentration profiles showing Examples of the present invention.

21 is a diagram schematically showing an energy band structure of a bipolar transistor having the profile shown in FIG.

FIG. 22 shows an eighth embodiment of the bipolar transistor according to the present invention.
FIG. 5 is a characteristic diagram showing germanium composition ratios and impurity concentration profiles showing Examples of the present invention.

FIG. 23 is a diagram schematically showing an energy band structure of the bipolar transistor having the profile shown in FIG.

FIG. 24 is a ninth embodiment of the bipolar transistor according to the present invention;
FIG. 5 is a characteristic diagram showing germanium composition ratios and impurity concentration profiles showing Examples of the present invention.

25 is a diagram schematically showing the energy band structure of the bipolar transistor having the profile shown in FIG.

FIG. 26 shows a first example of a bipolar transistor according to the present invention.
FIG. 7 is a characteristic diagram showing a germanium composition ratio and an impurity concentration profile showing Example 0.

FIG. 27 is a diagram schematically showing an energy band structure of the bipolar transistor having the profile shown in FIG. 26;

FIG. 28 shows a first example of a bipolar transistor according to the present invention.
FIG. 2 is a diagram illustrating a first embodiment, and is a circuit diagram of a preamplifier circuit used in an optical communication system.

29 is a sectional view of a front-end module of an optical communication system in which the preamplifier circuit shown in FIG. 28 is integrated on a mounting board.

FIG. 30 is a block diagram of a transmitting-side module of an optical communication system using the circuits and modules shown in FIGS. 28 and 29.

FIG. 31 is a block diagram of a multiplexing circuit (MUX) to which the bipolar transistor according to the present invention is applied.

FIG. 32 is a circuit diagram of a driver to which the bipolar transistor according to the present invention is applied.

FIG. 33 is a block diagram of a receiving module of the optical communication system.

FIG. 34 is a circuit diagram of an AGC 531 to which the bipolar transistor according to the present invention is applied.

FIG. 35 is a circuit diagram of a full-wave rectifier 551 to which the bipolar transistor according to the present invention is applied.

FIG. 36 is a circuit diagram of a limit amplifier 554 to which the bipolar transistor according to the present invention is applied.

FIG. 37 is a block diagram of a discriminator (540) to which the bipolar transistor according to the present invention is applied.

FIG. 38 is a circuit diagram of a selector used in the discriminator shown in FIG. 37;

FIG. 39 is a circuit diagram of a broadband amplifier circuit used in the discriminator shown in FIG. 37.

40 is a circuit diagram of a cascode type differential amplifier circuit used in the discriminator shown in FIG. 37.

FIG. 41 is a circuit diagram of a master-slave type flip-flop circuit used in the discriminator shown in FIG. 37;

FIG. 42 is a block diagram of a separation circuit (DMUX) 570 to which the bipolar transistor according to the present invention is applied.

FIG. 43 shows a first example of a bipolar transistor according to the present invention.
FIG. 9 is a diagram showing a second embodiment, and is a block diagram of a frequency divider to which the bipolar transistor is applied.

FIG. 44 is a circuit diagram of a clock input circuit used in the frequency divider shown in FIG.

FIG. 45 is a circuit diagram of an interstage buffer circuit used in the frequency divider shown in FIG. 43;

FIG. 46 is a circuit diagram of an output buffer circuit used in the frequency divider shown in FIG. 43.

FIG. 47 shows a first example of a bipolar transistor according to the present invention.
FIG. 13 is a diagram showing a third embodiment, and is a block diagram of a mobile wireless portable device to which a bipolar transistor according to the present invention is applied.

FIG. 48 shows a first example of a bipolar transistor according to the present invention.
FIG. 14 is a diagram showing Example 4 of the present invention, and is a circuit diagram of a D pre-scaler D flip-flop of a PLL of a mobile wireless portable device to which a bipolar transistor according to the present invention is applied.

FIG. 49 is a cross-sectional view showing a conventional bipolar transistor using single crystal silicon / germanium for an intrinsic base.

50 is a view illustrating a step of manufacturing an active region which is a main part of the bipolar transistor of the conventional example shown in FIG. 49 (part 1);

FIG. 51 is a view illustrating a step of manufacturing an active region which is a main part of the bipolar transistor of the conventional example shown in FIG. 49 (part 2);

[Explanation of symbols]

1, 31: silicon substrate, 2, 32: high-concentration n-type buried layer, 3, 33: low-concentration n-type collector layer (single-crystal silicon), 4, 5, 34: collector / base isolation insulating film,
6, 38: Collector extraction layer (high-concentration n-type single crystal silicon), 7, 35: Base extraction layer (p-type polycrystalline silicon or polycrystalline silicon / germanium)
4: Collector extraction layer (high-concentration n-type polycrystalline silicon), 9, 19, 20, 36, 37, 42 ... Emitter /
Base isolation insulating film, 10, 11, 12, 14 ... insulating film,
13... N-type collector layer (selective ion implantation layer), 15
... openings in the insulating film, 16a, 16, 39 ... low-concentration n-type collector layer (single-crystal silicon / germanium), 17a,
17b, 17, 41: p-type external base layer (polycrystalline silicon / germanium), 18, 40: intrinsic base layer (p-type single crystal silicon / germanium), 21, 43 ... emitter extraction layer (high-concentration n-type polycrystalline) Silicon), 22, 4
5 ... emitter region, 23, 46 ... insulating film, 24, 47 ...
Electrodes, 25: low-concentration p-type cap layer (single-crystal silicon or single-crystal silicon / germanium), 26: low-concentration p-type polycrystalline layer (polycrystalline silicon or polycrystalline silicon-germanium), 27: emitter layer (single-crystal) Silicon or single crystal silicon / germanium) 300: semiconductor integrated circuit (preamplifier circuit), 301: power supply terminal, 30
2 ... ground terminal, 303 ... decoupling capacitance, 401 ...
Optical fiber, 402: lens, 403: photodiode, 404: semiconductor integrated circuit (preamplifier circuit IC),
405 wiring, 406 output terminal, 407 substrate, 50
0: transmission module, 5001: multiplex circuit (MUX),
5002 ... Driver, 5003 ... Semiconductor laser, 500
4 External modulator, 501 Electric signal, 502 Optical fiber, 510 Optical receiving module, 520 Front end module, 521 Optical receiver, 522 Preamplifier, 530 Main amplifier section, 531 AGC, 532
... Main amplifier, 540 ... Identifier, 544 ... Optical fiber, 550 ... Clock extraction unit, 551 ... Full-wave rectifier, 5
52: Filter, 553: Phase shifter, 554: Limit amplifier, 560: Digital signal processing device ", 570: Separation circuit (DMUX), 580: DC / DC converter, 601
... antenna, 602 ... switch, 603 ... low noise amplifier, 604 ... down mixer, 605 ... oscillator, 606 ...
Synthesizer, 607 power amplifier, 608 up mixer, 609 demodulator, 610 oscillator, 611 PL
L, 612: modulator, 613: baseband unit,
701-712: Bipolar transistors, 713-7
16: resistor, 717, 718: current source, 719 to 724
... terminals.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F082 AA06 AA25 BA22 BA26 BA31 BC01 CA01 EA23 EA24 EA25 FA20 GA01 GA02 GA04 GA05 HA13 HA25 HA42 HA43 HA52 HA57 HB06 HB14 HB22 HB37

Claims (19)

[Claims] A first conductive type single-crystal silicon layer, a first insulating film having an opening provided on a surface of the first conductive type single-crystal silicon layer, and a second insulating film. A multilayer film comprising a second conductivity type polycrystalline layer having a conductivity type opposite to the first conductivity type and a third insulating layer; and a low-conductivity film comprising a first conductivity type single crystal silicon / germanium layer provided in the opening. A concentration collector region, a base region comprising a second conductivity type single crystal silicon / germanium layer provided on the first conductivity type single crystal silicon / germanium layer, and a base region comprising the second conductivity type single crystal silicon / germanium layer. At least an emitter region provided, and a second conductivity type polycrystalline silicon / germanium layer provided in contact with any of the second conductivity type single crystal silicon / germanium layer and the second conductivity type polycrystalline layer. A bipolar transistor, wherein the thickness of the first conductivity type single crystal silicon-germanium layer is larger at the periphery than at the center of the opening. 2. The bipolar transistor according to claim 1, wherein said second conductivity type polycrystalline layer is a polycrystalline silicon layer or a polycrystalline silicon / germanium layer. 3. The film thickness of the first conductivity type single crystal silicon / germanium layer around the opening is at least 5
3. The bipolar transistor according to claim 2, wherein the thickness is not less than nm. 4. A second second conductivity type single crystal layer provided on the second conductivity type single crystal silicon / germanium layer and having a lower impurity concentration than the second conductivity type single crystal silicon / germanium layer. The bipolar transistor according to claim 1, wherein the bipolar transistor is provided. 5. The bipolar transistor according to claim 4, wherein said second second conductivity type single crystal layer is a single crystal silicon layer or a single crystal silicon / germanium layer. 6. The bipolar transistor according to claim 1, wherein said emitter region comprises a second first conductivity type single crystal layer formed by epitaxial growth. 7. The bipolar transistor according to claim 6, wherein the second first conductivity type single crystal layer is a single crystal silicon layer or a single crystal silicon / germanium layer. 8. The bipolar transistor according to claim 1, wherein said second insulating film is a silicon nitride film. 9. The bipolar transistor according to claim 1, wherein said third insulating film is a silicon oxide film. 10. The method according to claim 1, wherein the composition ratio of germanium in the second conductivity type single crystal silicon-germanium layer decreases from the first conductivity type single crystal silicon layer side toward the surface. 2. The bipolar transistor according to claim 1. 11. The composition ratio of germanium in the first conductivity type single crystal silicon-germanium layer increases from the first conductivity type single crystal silicon layer side toward the surface,
The bipolar transistor according to claim 1, wherein the bipolar transistor has a region in which a germanium composition ratio is constant on a surface side. 12. The method according to claim 1, wherein the composition ratio of germanium in said first conductivity type single crystal silicon-germanium layer increases from the first conductivity type single crystal silicon layer side toward the surface. 2. The bipolar transistor according to claim 1. 13. The composition ratio of germanium in the second conductivity type single crystal silicon / germanium layer and the first conductivity type single crystal silicon / germanium layer increases from the first conductivity type single crystal silicon layer to the surface. The slope in the first conductivity type single crystal silicon-germanium layer is smaller than the slope of the germanium composition ratio in the second conductivity type single crystal silicon-germanium, according to any one of claims 1 to 9, Bipolar transistor. 14. A composition ratio of germanium in the second conductivity type single crystal silicon / germanium layer and the first conductivity type single crystal silicon / germanium layer from the first conductivity type single crystal silicon layer side toward the surface. The slope in the first conductivity type single crystal silicon-germanium layer is smaller than the slope of the germanium composition ratio in the second conductivity type single crystal silicon-germanium;
The bipolar transistor according to any one of claims 1 to 9, wherein the bipolar transistor has a region in which the germanium composition ratio increases from the first conductivity type single crystal silicon side toward the surface in the conductivity type single crystal silicon. 15. A first insulation film, a second insulation film, a second conductivity type polycrystalline layer having a conductivity type opposite to the first conductivity type, and a third insulation film on a surface of the first conductivity type single crystal silicon layer. Forming a multi-layered film including a plurality of layers, providing an opening in the multi-layered film, providing a first-conductivity-type single-crystal silicon-germanium layer in the opening; Providing a second-conductivity-type single-crystal silicon-germanium layer on the layer; and combining the second-conductivity-type single-crystal silicon-germanium layer with the second-conductivity-type single-crystal silicon-germanium layer. Wherein the first conductive type single crystal silicon-germanium layer is thicker in a peripheral portion than in a center of the opening. And providing the second conductivity type single crystal silicon-germanium layer by epitaxial growth, wherein the epitaxial growth is performed at a temperature of 500 ° C. to 800 ° C. and a pressure during the growth. Is carried out under conditions not exceeding 100 Pa (Pascal). 16. An electronic circuit device using the bipolar transistor according to claim 1. Description: 17. An optical communication system using the bipolar transistor according to claim 1. Description: 18. A light receiving element that receives an optical signal and outputs an electric signal, a first amplifier circuit that receives an electric signal from the light receiving element, a second amplifier circuit that receives an output of the first amplifier circuit, A discriminator for converting an output of the second amplifier circuit into a digital signal in synchronization with a predetermined clock signal, wherein the first amplifier circuit has a base on the light receiving element. A first bipolar transistor connected thereto, and a second bipolar transistor having a base connected to the collector of the first bipolar transistor and having a collector connected to an input of the second amplifier circuit. 15. A light, wherein at least one of the first and second bipolar transistors is constituted by the bipolar transistor according to any one of claims 1 to 14. Shin system. 19. The semiconductor device according to claim 18, wherein said first and second bipolar transistors are formed on a single semiconductor chip, and said semiconductor chip and said light receiving element are mounted on a single substrate. Optical communication system.