JPH1027883A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a fine resistance element with high precision by a method wherein the electrode of the first polycrystalline silicon layer is led out through the intermediary of the second polycrystalline silicon layer in the same conductivity type as that of the first polycrystalline silicon layer. SOLUTION: A silicon dioxide film 11 as an insulating film is formed on a silicon substrate 1 so as to form the first polycrystalline silicon film 21 as a resistance layer. Next, the second oxide film 12 is deposited on the substrate 1 to form a photoresist pattern for the formation of a photoresist pattern further to form the first contact hole 41. Successively, the second polycrystalline silicon layer 22 having high concentration impurities in the same conductivity type as that of the first polycrystalline silicon layer 21 is formed so as to lead out the electrode 32 of the first polycrystalline silicon layer 21 through the intermediary of the second polycrystalline silicon layer 22. Through these procedures, a fine resistance element can be formed with high precision.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using a polycrystalline silicon resistor which is finer and has a smaller variation in resistance value than in the prior art, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional technique relating to a resistor using single crystal silicon is disclosed in, for example, IEE Transactions on Electron Devices, E28, No. 7 (1981) No. 818.
Page to 830 (IEEE Trans. Electron Devices, ED-2
8, No. 7 (1981) pp. 818-830) discloses a configuration in which an impurity diffusion layer provided in a semiconductor substrate is used as a resistance element.
9 illustrates a cross-sectional structure illustrated in FIG. 7 and a planar structure illustrated in FIG. Here, FIG. 7 is a cross-sectional view indicated by a symbol AA in FIG. It should be noted that sectional views taken along the same positional relationship and direction are also shown in drawings other than FIG. However, the plan view of FIG. 8 is shown as a schematic diagram of the layout of the mask pattern.

The conventional resistor shown in FIG. 7 has been manufactured by the following method. First, using a well-known ion implantation technique, an impurity of a conductivity type opposite to that of the silicon substrate 1 is implanted to form an impurity diffusion layer 3. Subsequently, an impurity of the opposite conductivity type to that of the impurity diffusion layer 3 is implanted so that the impurity diffusion layer 3 is separated from the substrate by a PN junction, and heat treatment is performed to form the impurity diffusion layer 2. Then, an oxide film 1 is formed on the substrate surface.
After depositing No. 1, the contact hole 42 is formed by patterning the oxide film 11 using a known photo-etching technique. Further, a metal electrode 32 made of aluminum or the like is deposited so as to cover the contact hole, and this is patterned to form a lead electrode.

Further, by reducing the parasitic capacitance of the resistor,
As a technique for reducing the operation time of a semiconductor circuit, a technique using a polycrystalline silicon layer provided on an insulating film as a resistance element is disclosed in, for example, Analysis and Design of Integrated Circuits (1981), 11th edition, 2nd edition.
Pages 2 to 119 (Analysis and Design of AnalogInte
grated Circuits, pp112-119, 2nd-Edi., Gray and Mey
er, 1984, John Wiley & Sons., Inc.). This conventional example has a cross-sectional structure shown in FIG. 9 and a planar structure shown in FIG.

The conventional polycrystalline silicon resistor shown in FIG. 9 has been manufactured by the following method. First, an insulating film 11 is formed on a silicon substrate 1, and a polycrystalline silicon 21 having a desired thickness is deposited on the oxide film 11. afterwards,
The polycrystalline silicon 21 is formed by using a well-known ion implantation technique.
Impurities are implanted therein and heat treatment is further performed. Next, the polycrystalline silicon 21 is patterned using a known photo-etching technique. Thereafter, an oxide film 12 is deposited on the surface of the substrate, and the contact hole 42 is formed by patterning the oxide film 12 using a known photoetching technique. Further, a metal electrode 32 made of aluminum or the like is deposited so as to cover the contact hole 42, and this is patterned to form a lead electrode.

[0006]

Generally, a single-crystal silicon resistor has features such as good integration with an LSI process, easy control of the resistance value, small variation in characteristics, and high reliability. However, in order to achieve electrical insulation between the resistance layers, it is necessary to provide an opposite conductivity type impurity layer called an isolation layer so as to cover the resistance layers. Therefore, since a PN junction is formed between the isolation layer and the resistance layer, miniaturization is difficult, the parasitic capacitance is large, the soft error due to α rays is weak, and the resistance value is determined by the potential of the isolation layer and the substrate. Has a drawback that a substrate bias effect in which the fluctuation occurs occurs.

On the other hand, since the polycrystalline silicon resistor has a polycrystalline silicon layer on an insulating film as a resistance element, it has a higher degree of freedom in layout than a single crystal silicon resistor, has extremely small parasitic capacitance, and has a low It has features such as almost no error or substrate bias effect. Therefore, it is an indispensable passive element for a high-performance integrated circuit.

However, since polycrystalline silicon has a grain boundary, its electrical characteristics are significantly changed depending on the concentration, existence state, and crystal structure of impurities contained therein. Therefore, in order to obtain stable characteristics, it is necessary to keep the impurity concentration in the film at a certain value or more. For this reason, when the sheet resistance is increased with miniaturization, the film thickness is reduced in order not to lower the impurity concentration. On the other hand, the resistance contact hole (electrode lead portion) is also miniaturized, and therefore, the formation of the contact hole generally uses a selective dry etching technique that is easy to perform fine processing. Therefore, when the insulating film on the resistance layer is etched, the surface of the resistance layer is shaved, which causes a problem that the contact resistance increases in combination with the above-described reduction in the film thickness.

The above relationship will be described with reference to FIGS. FIG. 11A schematically shows the flow of the current in the contact portion of the resistor. In the figure, the current flowing from the left corner of the electrode flows through the resistance layer immediately below the contact portion to the right corner. To go. This is because, if the materials of the resistance layer and the electrode are different, a contact resistance is generated between the two materials, so that the current does not concentrate on the right end of the electrode but flows from the entire surface of the electrode as shown in the figure. Current flow has already been conducted by IEE Transactions on Solid State Electronics, Volume 15, (1972).
Pages 145 to 158 (IEEE Trans. Solid-State El
ectronics, Vol. 15, (1972) pp. 145-158), and the contact resistance can be represented by a distributed constant type equivalent circuit as shown in b). In this case, the contact resistance and the sheet resistance have the relationship of the mathematical formula shown in FIG. Therefore, when the resistance layer of the contact portion is over-etched and the sheet resistance of this portion increases, the contact resistance increases.

FIG. 12 shows the relationship between the amount d of over-etching of the resistance layer and the contact resistance when the contact hole is formed. When the thickness of the resistance layer immediately below the contact hole decreases, the sheet resistance increases and the contact resistance decreases. It can be seen that it increases. Actually, the contact resistance of the micro-resistive element is susceptible to the processing variation, and has a disadvantage that the characteristic variation is large. Furthermore, the finer contact hole causes a decrease in the contact area between the metal electrode and the resistance layer, so that the ratio of the contact resistance to the total resistance value increases, and the ratio of the contact resistance variation to the resistance value variation increases. Was.

[0011] The problem of the resistance element as described above is as follows.
This hinders performance improvement of various semiconductor integrated circuits using such a resistance element, and furthermore, of a system using the same. The problem of the resistance value variation of the resistance element not only hinders the speeding up of the circuit and the system, but also becomes a problem in designing a highly reliable circuit and system. In particular, when constructing a circuit / system of an optical communication system of the order of several tens of Gbps, which is required to operate at high speed, or a portable terminal device for mobile radio, which is required to operate at high speed and miniaturization, a highly accurate and minute resistance is required. The realization of an element has been desired.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a highly accurate and fine resistance element and a method of manufacturing the same. Another object of the present invention is to provide a circuit and a system having a resistive element that can operate at high speed and with high accuracy.

[0013]

In order to achieve the above object, a semiconductor device according to a typical embodiment of the present invention has a support substrate, that is, a silicon substrate 1 as shown in FIGS.
A first polycrystalline silicon layer 21 serving as a resistance layer is provided on a silicon dioxide film (hereinafter, simply referred to as an oxide film) 11 as an upper first insulating film. The electrode is drawn out through a second polycrystalline silicon layer 22 having the same conductivity type as that of the first polycrystalline silicon layer and having a high impurity concentration. Here, in the semiconductor device, the second polycrystalline silicon layer 22 has a sufficiently low sheet resistance, and a first polycrystalline silicon layer 22 having a sufficient remaining film thickness even if overetched by dry etching during contact formation. It is preferable that the film thickness is larger than that of the polycrystalline silicon layer 21.

Alternatively, as shown in FIGS. 3 and 4, the semiconductor device of the present invention comprises a first polycrystalline silicon layer serving as a resistance layer on a first oxide film 11 on a supporting substrate, ie, a silicon substrate 1. And a second polycrystalline silicon layer 22 of the same conductivity type and high impurity concentration as the first polycrystalline silicon layer 21 and a second polycrystalline silicon layer. It is characterized in that it is performed via a low-resistance first metal film 31 selectively formed on a silicon layer. At this time, it is preferable that the dimensions of the contact hole 41 and the thickness of the second polycrystalline silicon layer 22 are selected so that the first metal film is embedded in the contact hole 41.

Alternatively, as shown in FIG. 5, the semiconductor device of the present invention comprises a first polycrystalline silicon layer 21 serving as a resistance layer on a support substrate, ie, a first oxide film 11 on a silicon substrate 1. A second polycrystalline silicon layer 22 having the same conductivity type as that of the first polycrystalline silicon layer and having a high impurity concentration; and a second polycrystalline silicon layer 22 having the same conductivity type as the first polycrystalline silicon layer. Resistance first metal film 3 selectively formed on the substrate
1 and a portion of the second polycrystalline silicon layer is
In contact with the oxide film. In the semiconductor device, it is preferable that the dimensions of the contact hole and the thickness of the second polycrystalline silicon layer are selected so that the first metal film is embedded in the contact hole 41.

Alternatively, as shown in FIG. 6, the semiconductor device of the present invention has a first polycrystalline silicon layer 21 serving as a resistance layer on a first oxide film 11 on a supporting substrate, that is, a silicon substrate 1. Then, the electrode extraction of the first polycrystalline silicon layer is performed via the second polycrystalline silicon layer 22 having the same conductivity type and high impurity concentration as the first polycrystalline silicon layer, and the second polycrystalline silicon layer near the resistance is obtained. The crystal silicon layer and the electrode have the same planar shape.

A method of manufacturing a semiconductor device according to a typical embodiment of the present invention includes a step of sequentially depositing a first insulating film and a low impurity concentration first semiconductor layer on a supporting substrate; That is, referring to FIG. 13, a step of forming a laminated substrate having an oxide film 11 and a polycrystalline silicon layer 21 on a silicon substrate, and a step of adding impurities to the polycrystalline silicon layer using a known ion implantation technique A step of patterning the polycrystalline silicon layer using a known photoetching technique; a step of depositing a second oxide film 12 on the substrate surface as shown in FIG. A step of forming a contact hole 41 by anisotropically etching a part of the oxide film 12 using a well-known photo-etching technique so that the contact hole 41 is exposed, and as shown in FIG. A step of depositing a polycrystalline silicon layer 22 having a high impurity concentration to which an impurity of the same conductivity type as that of the polysilicon layer 21 is added, and a step of patterning the polycrystalline silicon layer using a known photoetching technique, as shown in FIG. Forming a contact hole 42 by depositing the third oxide film 13 and partially etching the same, and thereafter, forming a lead electrode so as to cover the contact hole 42. .

Another method of manufacturing a semiconductor device according to a typical embodiment of the present invention is a step of sequentially depositing a first insulating film and a low impurity concentration first semiconductor layer on a supporting substrate. In other words, referring to FIG. 17, a step of forming a laminated substrate having an oxide film 11 and a polycrystalline silicon layer 21 on a silicon substrate, and adding an impurity to this polycrystalline silicon layer using a well-known ion implantation technique , A step of patterning the polycrystalline silicon layer using a known photo-etching technique, a step of depositing a second oxide film 12 on the substrate surface as shown in FIG. Forming a contact hole 41 by anisotropically etching a part of the oxide film 12 using a well-known photo-etching technique so that a part of the substrate is exposed, and as shown in FIG. Many Depositing a high impurity concentration polycrystalline silicon layer 22 doped with an impurity of the same conductivity type as the polycrystalline silicon layer 21; patterning the polycrystalline silicon layer using a known photoetching technique; A step of selectively growing a low-resistance metal film 31 on silicon, and a step of depositing a third oxide film 13 and etching a part of the third oxide film 13 to form a contact hole 42 as shown in FIG. Forming a lead electrode so as to cover the contact hole 42, and thereafter.

Another method of manufacturing a semiconductor device according to a typical embodiment of the present invention is a step of sequentially depositing a first insulating film and a low impurity concentration first semiconductor layer on a supporting substrate. In other words, referring to FIG. 21, a step of forming a laminated substrate having an oxide film 11 and a polycrystalline silicon layer 21 on a silicon substrate, and adding an impurity to this polycrystalline silicon layer using a well-known ion implantation technique. , A step of patterning the polycrystalline silicon layer using a known photo-etching technique, a step of depositing a second oxide film 12 on the substrate surface as shown in FIG. A portion of the oxide film 12 and a portion of the polycrystalline silicon layer 21 are anisotropically etched using a known photoetching technique so that a portion of the oxide film 11 and a portion of the oxide film 11 are exposed. The shape A step of, as shown in FIG. 23,
A step of depositing a high impurity concentration polycrystalline silicon layer 22 doped with an impurity of the same conductivity type as the polycrystalline silicon layer 21 on the substrate surface, and a step of patterning the polycrystalline silicon layer using a known photoetching technique. 24, a step of selectively growing a low-resistance metal film 31 on the polycrystalline silicon; and, as shown in FIG. 24, a third oxide film 13 is deposited and a part thereof is etched to form a contact hole 42. The method is characterized by comprising a forming step, and thereafter, a step of forming a lead electrode so as to cover the contact hole 42.

Another method of manufacturing a semiconductor device according to a typical embodiment of the present invention is a step of sequentially depositing a first insulating film and a low-impurity-concentration first semiconductor layer on a supporting substrate. That is, referring to FIG. 25, a step of forming a laminated substrate having an oxide film 11 and a polycrystalline silicon layer 21 on a silicon substrate, and adding an impurity to the polycrystalline silicon layer by using a well-known ion implantation technique. 26, a step of patterning this polycrystalline silicon layer using a known photoetching technique, a step of depositing a second oxide film 12 on the substrate surface as shown in FIG. Forming a contact hole 41 by anisotropically etching a part of the oxide film 12 using a known photo-etching technique so that a part of the contact hole 41 is exposed; and as shown in FIG. So as to cover the hole 42, characterized in that it consists of a step of forming the electrode lead-out and the polycrystalline silicon layer 22 of high impurity concentration doped polycrystalline silicon layer 21 of the same conductivity type on the substrate surface.

According to such a semiconductor device according to a typical embodiment of the present invention, since the extraction of the electrode of the polycrystalline silicon layer serving as the resistance is performed using the low specific resistance polycrystalline silicon layer, Even if the resistive layer is over-etched during the contact hole processing, no contact resistance occurs between the two polysilicon layers. Therefore, even if the sheet resistance of the resistive layer below the contact hole increases due to the overetch, the contact resistance does not increase. Further, since the extraction of the electrode of the resistance layer is performed through a high impurity concentration polycrystalline silicon layer or a high impurity concentration polycrystalline silicon layer and a low resistance metal film provided on the polycrystalline silicon layer, the polycrystalline silicon The contact area between the metal electrode and the metal electrode is increased, and the contact resistance can be significantly reduced. Further, even if the contact hole between the resistive layer and the polycrystalline silicon for leading out the electrode is miniaturized, an extreme increase in the contact resistance does not occur. Therefore, the miniaturization of the resistance width becomes easy, and a resistance with a small parasitic capacitance can be realized. . for that reason,
Compared with the same resistance value, a resistor having higher accuracy and less parasitic capacitance than the conventional polycrystalline silicon resistor can be realized. Therefore, if this resistor is used for a high-performance integrated circuit, the circuit performance can be dramatically improved.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the semiconductor device and the method of manufacturing the same according to the present invention will be described below in detail with reference to the accompanying drawings. In the accompanying drawings, main parts are shown larger than other parts for easy understanding.
Further, the material, conductivity type, manufacturing conditions, and the like of each part are not limited to those described in the present embodiment.

<First Embodiment of the Invention> A first embodiment will be described with reference to FIGS. FIG. 1 is a sectional view of a main part of a resistor showing one embodiment of a semiconductor device of the present invention, and FIG. 2 is a layout pattern diagram schematically showing a planar structure thereof. Here, FIG. 1 is a schematic diagram of a cross-sectional structure indicated by a symbol AA in FIG. It should be noted that even in cases other than FIG. 1, a cross-sectional structure when cut along the same positional relationship and direction is shown.

As shown in FIG. 1, the semiconductor device of the present invention has a first polycrystalline silicon layer 21 serving as a resistance layer on a supporting substrate, ie, an oxide film 11 serving as a first insulating film on a silicon substrate 1. Then, the electrode of the first polycrystalline silicon layer is led out via the second polycrystalline silicon layer 22 having the same conductivity type as that of the first polycrystalline silicon layer and having a high impurity concentration.

Therefore, no contact resistance is generated between both polycrystalline silicon layers, so that the resistance layer is over-etched at the time of forming the contact hole, thereby preventing the contact resistance from increasing even if the sheet resistance of the resistance layer below the contact hole increases. it can.
Furthermore, since the degree of freedom of the layout of the contact between the high-concentration polycrystalline silicon layer for extracting the electrode and the metal electrode increases,
The contact area between the polycrystalline silicon and the metal electrode can be increased, and the contact resistance can be significantly reduced. Also, even if the contact hole between the resistive layer and the polycrystalline silicon for extracting the electrode is miniaturized, an extreme increase in the contact resistance does not occur.
Miniaturization of the resistance width is facilitated, and a resistance with small parasitic capacitance can be realized. Therefore, when compared with the same resistance value, it is possible to realize a resistor having higher accuracy and less parasitic capacitance than a conventional polycrystalline silicon resistor.

FIG. 28 shows an example in which the resistor of this embodiment is applied to a conventional bipolar integrated circuit. Since the parasitic capacitance of the resistor is small and the accuracy is high, an integrated circuit with higher performance than the conventional one can be realized.

Hereinafter, an example of a method for manufacturing the semiconductor device of the present invention shown in FIG. 1 will be sequentially described with reference to FIGS. Here, FIGS. 13 to 16 are cross-sectional structures sequentially showing the manufacturing process of the semiconductor device according to the present embodiment, and show the structure before the cross-sectional structure of FIG.

(1) Referring to FIG. 13, first, an oxide film is formed on silicon substrate 1 by thermal oxidation or CVD, and then a polycrystalline silicon layer is formed thereon by CVD. 21 are formed. Next, impurities are implanted into the polycrystalline silicon layer 21 using a well-known ion implantation technique. Thereafter, after forming a photoresist pattern on the substrate, the polycrystalline silicon layer 21 is anisotropically dry-etched using the photoresist pattern as a mask,
This resist is removed.

(2) Referring to FIG. 14; a second oxide film 12 is deposited on the surface of the substrate, and a photoresist pattern is formed on the substrate. Thereafter, a part of oxide film 12 on polycrystalline silicon layer 21 is anisotropically dry-etched using this photoresist pattern as a mask to form first contact hole 4.
Form one.

(3) Referring to FIG. 15, a polycrystalline silicon layer 22 having the same conductivity type as the polycrystalline silicon layer 21 and having a high impurity concentration of 10 ²⁰ / cm ³ or more is formed on the substrate surface.
It is deposited by the VD method. At this time, as shown in FIG. 15, the polycrystalline silicon layer 22 has a thickness enough to fill the contact hole, that is, at least a half or more of the contact hole dimension, and is overetched at the time of forming the contact hole described later. Even so, a sufficient film thickness is deposited so as not to cause an extreme increase in sheet resistance. Here, instead of depositing polycrystalline silicon 22 containing high-concentration impurities, deposition of low-impurity-concentration polycrystalline silicon and impurity implantation by ion implantation may be combined. Thereafter, a photoresist pattern is formed on the substrate, and then the polycrystalline silicon layer 22 is anisotropically dry-etched using the photoresist pattern as a mask. Next, after removing the resist, high-temperature heat treatment is performed to activate the impurities.

(4) Referring to FIG. 16, an oxide film 13 is deposited on the substrate surface by using the CVD method. After that, a contact hole is formed at a required position using a known photoetching technique.

After passing through the manufacturing steps described in the above (1) to (4), an aluminum film 32 is deposited, and an aluminum electrode is processed so as to cover the contact hole 42. A polycrystalline silicon resistor can be realized.

<Second Embodiment> A second embodiment will be described with reference to FIGS. FIG. 3 is a sectional view of a main part of a resistor showing one embodiment of the semiconductor device of the present invention, and FIG. 4 is a layout pattern diagram schematically showing a planar structure thereof. Here, FIG. 3 is a schematic diagram of a cross-sectional structure indicated by a symbol AA in FIG. In addition, even in cases other than FIG. 3, a cross-sectional structure when cut along the same positional relationship and direction is shown.

As shown in FIG. 3, the semiconductor device of the present invention
A first polycrystalline silicon layer 21 serving as a resistance layer is provided on an oxide film 11 serving as a first insulating film on a support substrate, that is, a silicon substrate 1. A second polycrystalline silicon layer 22 of the same conductivity type as the first polycrystalline silicon layer and having a high impurity concentration, and a first metal film 31 of low resistance selectively formed on the second polycrystalline silicon layer
And through the structure.

As a result, no contact resistance is generated between both polycrystalline silicon layers, so that the resistance layer is over-etched at the time of forming the contact hole, thereby preventing the contact resistance from increasing even if the sheet resistance of the resistance layer below the contact hole increases. it can.
Further, since the extraction of the resistance electrode is performed through the high impurity concentration polycrystalline silicon layer 22 and the low resistance metal film 31 on the polycrystalline silicon layer 22, the contact area between the polycrystalline silicon 22 and the metal electrode 31 is increased. And the contact resistance can be greatly reduced. Further, even if the contact hole between the resistance layer 21 and the high impurity concentration polycrystalline silicon 22 is miniaturized,
Since no extreme increase in the contact resistance occurs, the resistance width can be easily miniaturized, and a resistance with small parasitic capacitance can be realized. Therefore, when compared with the same resistance value, it is possible to realize a resistor having higher accuracy and less parasitic capacitance than a conventional polycrystalline silicon resistor.

Hereinafter, an example of a method of manufacturing the semiconductor device of the present invention shown in FIG. 3 will be sequentially described with reference to FIGS. Here, FIGS. 17 to 20 are cross-sectional structures sequentially showing the manufacturing steps of the semiconductor device according to the present embodiment, and show the structure before the cross-sectional structure of FIG.

(5) Referring to FIG. 17, first, an oxide film is formed on silicon substrate 1 by thermal oxidation or CVD, and then a polycrystalline silicon layer is formed thereon by CVD. 21 are formed. Next, impurities are implanted into the polycrystalline silicon layer 21 using a well-known ion implantation technique. Thereafter, after forming a photoresist pattern on the substrate, the polycrystalline silicon layer 21 is anisotropically dry-etched using the photoresist pattern as a mask,
This resist is removed.

(6) Referring to FIG. 18, a second oxide film 12 is deposited on the surface of the substrate, and a photoresist pattern is formed on the substrate. Thereafter, a part of oxide film 12 on polycrystalline silicon layer 21 is anisotropically dry-etched using this photoresist pattern as a mask to form first contact hole 4.
Form one.

(7) Referring to FIG. 19, a polycrystalline silicon layer 22 having the same conductivity type as the polycrystalline silicon layer 21 and having a high impurity concentration of 10 ²⁰ / cm ³ or more is formed on the substrate surface.
It is deposited by the VD method. Thereafter, a photoresist pattern is formed on the substrate, and then the polycrystalline silicon layer 22 is anisotropically dry-etched using the photoresist pattern as a mask. Next, after removing the resist, high-temperature heat treatment is performed to activate the impurities. Thereafter, a low-resistance metal film 31 such as tungsten is selectively deposited on the polycrystalline silicon layer 22 using selective CVD. Here, instead of depositing polycrystalline silicon 22 containing high-concentration impurities, deposition of low-impurity-concentration polycrystalline silicon film and impurity implantation by ion implantation may be combined, or deposition of tungsten film by selective CVD. Instead, a combination of ordinary tungsten deposition by CVD and patterning by photoetching may be used.

(8) Referring to FIG. 20, an oxide film 13 is deposited on the substrate surface by using the CVD method. After that, a contact hole is formed at a required position using a known photoetching technique.

After the manufacturing steps described in the above (5) to (8), an aluminum film 32 is deposited, and an aluminum electrode is processed so as to cover the contact hole 42. A polycrystalline silicon resistor can be realized.

<Embodiment 3> A third embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional structural view of a main part of a resistor showing one embodiment of the semiconductor device of the present invention. The layout pattern schematically showing the planar structure of FIG. 5 is the same as that of FIG. Here, FIG. 5 is a schematic diagram of a cross-sectional structure indicated by a symbol AA in FIG. It should be noted that even in cases other than FIG. 5, a cross-sectional structure when cut along the same positional relationship and direction is shown.

As shown in FIG. 5, the semiconductor device of the present invention
A first polycrystalline silicon layer 21 serving as a resistance layer is provided on an oxide film 11 serving as a first insulating film on a support substrate, that is, a silicon substrate 1. A second polycrystalline silicon layer 22 of the same conductivity type as the first polycrystalline silicon layer and having a high impurity concentration, and a first metal film 31 of low resistance selectively formed on the second polycrystalline silicon layer
And a portion of the second polycrystalline silicon layer 22 is in contact with the first oxide film.

Therefore, no contact resistance is generated between the two polycrystalline silicon layers, so that the resistance layer is over-etched at the time of forming the contact hole, and even if the sheet resistance of the resistance layer below the contact hole increases, the increase in the contact resistance is prevented. it can.
Furthermore, since the electrode of this resistance is formed through a polycrystalline silicon layer having a high impurity concentration and a metal film having a low resistance, the contact area between the polycrystalline silicon and the metal electrode is increased, and the contact resistance is greatly reduced. it can. Also, even if the contact hole between the resistance layer and the high impurity concentration polycrystalline silicon is miniaturized,
Since the contact resistance does not increase extremely, miniaturization of the resistance width becomes easy, and a resistance with small parasitic capacitance can be realized. Therefore, when compared with the same resistance value, it is possible to realize a resistor having higher accuracy and less parasitic capacitance than a conventional polycrystalline silicon resistor.

Hereinafter, an example of a method of manufacturing the semiconductor device of the present invention shown in FIG. 5 will be sequentially described with reference to FIGS. Here, FIG. 21 to FIG. 24 are cross-sectional structures sequentially showing the manufacturing process of the semiconductor device according to the present embodiment, and show the structure before the cross-sectional structure of FIG.

(9) Referring to FIG. 21, first, an oxide film is formed on silicon substrate 1 by thermal oxidation or CVD, and then a polycrystalline silicon layer is formed thereon by CVD. 21 are formed. Next, impurities are implanted into the polycrystalline silicon layer 21 using a well-known ion implantation technique. Thereafter, after forming a photoresist pattern on the substrate, the polycrystalline silicon layer 21 is anisotropically dry-etched using the photoresist pattern as a mask,
This resist is removed.

(10) Referring to FIG. 22, a second oxide film 12 is deposited on the surface of the substrate, and a photoresist pattern is formed on the substrate. Then, using this photoresist pattern as a mask, a part of oxide film 12 and polycrystalline silicon layer 2 are formed.
1 is anisotropically dry-etched to expose a part of the oxide film 11 and a part of the polycrystalline silicon 21 to form a first contact hole 41 as shown in FIG.

(11) Referring to FIG. 23; next, the same conductivity type of 10 ²⁰ / cm ^{3 as} polycrystalline silicon layer 21 is formed on the substrate surface.
The polycrystalline silicon layer 22 having the above high concentration of impurities is deposited by the CVD method. Thereafter, a photoresist pattern is formed on the substrate, and then the polycrystalline silicon layer 22 is anisotropically dry-etched using the photoresist pattern as a mask. Next, after removing the resist, high-temperature heat treatment is performed to activate the impurities. Thereafter, a low-resistance metal film 31 such as tungsten is selectively deposited on the polycrystalline silicon layer 22 using selective CVD.
Here, instead of depositing polycrystalline silicon 22 containing high-concentration impurities, deposition of low-impurity-concentration polycrystalline silicon film and impurity implantation by ion implantation may be combined, or deposition of tungsten film by selective CVD. Instead, a combination of ordinary tungsten deposition by CVD and patterning by photoetching may be used.

(12) Referring to FIG. 24;
An oxide film 13 is deposited on the substrate surface by using the method. afterwards,
A contact hole is formed at a required location using a known photoetching technique.

After the manufacturing steps described in the above (9) to (12), an aluminum film 32 is deposited and an aluminum electrode is processed so as to cover the contact hole 42.
The high-performance polycrystalline silicon resistor shown in FIG. 5 can be realized.

<Embodiment 4> A fourth embodiment will be described with reference to FIG. FIG. 6 is a sectional view of a main part of a resistor showing one embodiment of the semiconductor device of the present invention.

As shown in FIG. 6, the semiconductor device of the present invention
A first polycrystalline silicon layer 21 serving as a resistance layer is provided on an oxide film 11 serving as a first insulating film on a support substrate, that is, a silicon substrate 1. The structure is performed through a second polycrystalline silicon layer 22 having the same conductivity type as that of the first polycrystalline silicon layer and having a high impurity concentration.

Therefore, even if the resistive layer is over-etched during the processing of the contact hole, the sheet resistance under the contact hole does not increase, and the contact resistance can be prevented from increasing. Further, since the high-concentration polycrystalline silicon layer for extracting the electrode and the extracted metal electrode have the same pattern, the contact area can be widened irrespective of the layout of the resistance layer, so that the contact resistance can be greatly reduced. Further, even if the contact hole is miniaturized, an extreme increase in the contact resistance does not occur, so that the resistance width can be easily miniaturized and a resistance with a small parasitic capacitance can be realized. Therefore, when compared with the same resistance value, it is possible to realize a resistor having higher accuracy and less parasitic capacitance than a conventional polycrystalline silicon resistor.

Hereinafter, an example of a method of manufacturing the semiconductor device of the present invention shown in FIG. 6 will be described in order with reference to FIGS. Here, FIG. 21 to FIG. 24 are cross-sectional structures sequentially showing the manufacturing process of the semiconductor device according to the present embodiment, and show the structure before the cross-sectional structure of FIG.

(13) Referring to FIG. 25, first, an oxide film is formed on silicon substrate 1 by thermal oxidation or CVD to form silicon dioxide 11, and then a polycrystalline silicon layer is formed thereon by CVD. 21 are formed. Next, impurities are implanted into the polycrystalline silicon layer 21 using a well-known ion implantation technique. Thereafter, a photoresist pattern is formed on the substrate, and then the polycrystalline silicon layer 21 is anisotropically dry-etched using the photoresist pattern as a mask to remove the resist.

(14) Referring to FIG. 26; a second oxide film 12 is deposited on the surface of the substrate, and a photoresist pattern is formed on the substrate. Thereafter, a part of oxide film 12 on polycrystalline silicon layer 21 is anisotropically dry-etched using this photoresist pattern as a mask to form first contact hole 41.

(15) Referring to FIG. 27; next, 10 ²⁰ / cm ³ of the same conductivity type as polycrystalline silicon layer 21 is formed on the substrate surface.
The polycrystalline silicon layer 22 having the above high concentration of impurities is deposited by the CVD method. Here, instead of depositing polycrystalline silicon 22 containing high-concentration impurities, deposition of low-impurity-concentration polycrystalline silicon film and impurity implantation by ion implantation may be combined. Thereafter, a heat treatment at, for example, 900 ° C. or higher is performed to activate the impurities.

After the manufacturing steps described in the above (13) to (15), an aluminum film 32 is deposited, and an aluminum electrode and a polycrystalline silicon film are processed so as to cover the contact hole 42. Can be realized.

<Fifth Embodiment of the Invention> FIG. 29 shows a fifth embodiment relating to a circuit and a system formed using the above-described resistance element of the present invention. The circuit shown in FIG. 29 is a circuit diagram showing a preamplifier circuit used in an optical transmission system. As is well known, an optical transmission system requires high-speed transmission of several tens of Gbps, and its preamplifier circuit particularly requires high-speed operation. Therefore, by employing the resistance element according to each of the above-described embodiments as a transistor constituting the amplifier circuit, it is possible to significantly improve the performance of the entire amplifier circuit.

In FIG. 29, reference numeral 300 denotes a semiconductor integrated circuit constituting a preamplifier circuit formed on a single semiconductor substrate. PD is a photodiode which is a light receiving element for receiving an optical signal transmitted through an optical transmission cable, 303 is a decoupling capacitor connected between a power supply line and a ground line for short-circuiting an AC component, and a semiconductor circuit. It is externally attached to 300. The bipolar transistors Q1 and Q2 are bipolar transistors forming an amplifier circuit. The diode D1 is a diode for level shift and uses a bipolar transistor.
It can be formed by short-circuiting between the base and collector, and if necessary, a plurality of diodes can be connected in series. Also, R1, R
2 and R3 are resistors, respectively, to which the resistance element of the present invention is applied. OUT is an output terminal, and an output buffer circuit is inserted between the output terminal and the emitter of the transistor Q2 as necessary.

In this embodiment, an optical signal transmitted through the optical transmission cable is converted into an electric signal by the photodiode PD, and the signal is amplified by the amplifying transistors Q1 and Q2 via the input terminal IN of the semiconductor circuit 300. It operates so as to be output from the output terminal OUT.

FIG. 30 shows a front end module of an optical transmission system in which the photodiode PD and the preamplifier circuit 300 shown in FIG. 29 are integrated. In the figure, reference numeral 401 denotes an optical fiber, 402 denotes a lens, 403 denotes a photodiode, and 404 denotes a semiconductor integrated circuit on which a preamplifier is formed. 407 is a photodiode and preamplifier 40
4 is a substrate on which is mounted, and is connected to an output terminal 406 via a wiring 406 for connecting a diode, an amplifier and the like. Reference numeral 408 denotes a hermetically sealed package such as a metal case. Although not shown, the capacitor 303 shown in FIG. 29 is also mounted on the substrate 407. Thus, by configuring the photodiode and the preamplifier constituting the front end in the same module,
The signal path can be shortened, so that noise is hard to get on and the parasitic L component and C component can be suppressed small.

This embodiment is an example in which a resistor element manufactured by the above-described method is used for a preamplifier circuit, which is used as an integrated circuit chip, and is applied to a front-end module.
The optical signal input from the optical fiber 401 is
And the light is converted into an electric signal by the photodiode IC 403. The electric signal is amplified by the preamplifier IC 404 through the wiring 405 on the substrate 407, and is amplified by the output terminal 406.
Output from

FIGS. 31 and 32 show FIGS. 29 and 30 respectively.
1 is a system configuration diagram of an optical transmission system using a preamplifier and a front-end module shown in FIG.

FIG. 31 shows a transmission side system 500 of the optical transmission system. The electric signal 501 to be transmitted is input to the multiplexer MUX and multiplexed, for example, at a ratio of 4: 1, and the output signal is transmitted to the driver 502. The semiconductor laser LD always outputs light of a constant intensity, and the external modulator 5 driven by the driver 502
Numeral 03 is configured to absorb or non-absorb light according to the output of the driver 502 and transmit the light to the optical fiber 504.

The transmission module shown in FIG. 31 is called an external modulation type. In this embodiment, instead of this, it is also possible to employ a direct modulation type that directly controls the light emission of the semiconductor laser, but in general, transmission by the external modulation type does not spread the spectrum oscillation due to chirp, Suitable for high-speed, long-distance transmission.

FIG. 32 shows an optical receiving module 510 of the optical transmission system according to this embodiment.

In this drawing, reference numeral 520 denotes a front end module to which the embodiment of the present invention shown in FIGS. 29 and 30 can be applied. The electric signal amplified by the preamplifier 522 of the front end module 520 is input to the main amplifier 530 and amplified. Main amplifier 53
0 avoids variations due to optical transmission distance and manufacturing deviation,
In order to keep the output constant, the output of the main amplifier 532 is input to an automatic gain adjuster (AGC) 531 which is fed back. The main amplifier may employ a limit amplifier for limiting the output amplitude, in addition to the configuration for adjusting the gain. The discriminator 540 is configured to perform 1-bit analog-to-digital conversion in synchronization with a predetermined clock, digitizes the output of the main amplifier unit, and separates the output of the main amplifier unit into, for example, 1: 4 by a separator DMUX. The data is input to 560 and predetermined processing is performed.

The clock extracting section 550 is for forming an electric signal obtained by converting a clock for controlling the operation timing of the discriminator 540 and the separator DMUX, and outputs the output of the main amplifier section 530 to the full-wave rectifier 551. And a signal to be a clock signal is extracted by filtering with a filter 552 having a narrow band. The output of the filter 552 is a phase shifter for matching the phase of the filter output with the analog signal, and delays the filter output based on a predetermined delay amount.

In the optical communication system according to the present embodiment, a circuit can be formed by using the transistor element having the above-described structure at various points. Similarly, the main amplifier 5
The circuit constituting 32 can also be constituted by the circuit shown in FIG.

<Sixth Embodiment of the Invention> FIG. 33 shows a sixth embodiment of the present invention, and shows a configuration of a mobile radio terminal to which a resistance element according to the present invention is applied. In the present embodiment, a low noise amplifier 603, a synthesizer 606, and a PLL (Phase Locked)
Loops (phase-locked loops) 611 and the like can be formed as circuits constituting each block of the mobile wireless portable device.

In this embodiment, the input from the antenna is amplified by the low-noise amplifier 603, the frequency emitted from the synthesizer 606 is oscillated from the oscillator 605, and the signal from the low-noise amplifier 603 is used by using the signal oscillated from the oscillator 605. , The down-mixer 604 down-converts to a lower frequency. Further, the frequency emitted from the PLL 611 is oscillated from the oscillator 610, and the down mixer 604
From the signal oscillated from the oscillator 610,
The signal is demodulated by the demodulator 609 and signal processing is performed by the baseband unit 613 that handles lower frequencies. The signal emitted from the baseband unit 613 is modulated by the modulator
The signal is modulated using the signal from the LL 611, further up-converted to a high frequency by the up mixer 608 based on the signal from the synthesizer 606, amplified by the power amplifier 607, and transmitted from the antenna 601. Reference numeral 602 denotes a switch for switching between transmission and reception of a signal. The switch 602 receives a control signal (not shown) from the baseband unit 613 and controls transmission and reception. In addition, a speaker, a microphone, and the like (not shown) are connected to the baseband unit 613 so that audio signals can be input and output.

The semiconductor device manufactured according to the above-described manufacturing method includes each block of the present embodiment, in particular, the low noise amplifier 60.
3, each circuit can be configured by applying to the synthesizer 606 and the PLL 611. Since the transistor according to the present invention can reduce the base resistance and the base / collector capacitance, the low noise amplifier 603, the synthesizer 606, and the PLL 611 can achieve low noise and low power consumption. This makes it possible to realize a mobile wireless portable device that can be used for a long time with low noise as a whole system.

FIG. 34 is a circuit diagram of a D flip-flop used for a prescaler of a PLL of a mobile radio portable device. The resistive elements of the present invention are used as the resistive elements 713 to 716.

The input signal, the clock signal, and the output signal have only two states, a high potential and a low potential. An input signal and an inverted input signal are input to terminals 719 and 720, respectively, and a clock signal and an inverted clock signal are input to terminals 721 and 722, respectively, and an output signal and an inverted output signal are obtained from terminals 723 and 724. The current paths flowing through the current sources 718 and 719 are switched to one of the transistors 709 or 710 and 711 or 712, respectively, by the clock signal. Further, the on / off of the transistors 701 to 706 is determined by the input signal, the clock signal,
Is determined by the potential at the lower end of the resistor caused by the current flowing through In this circuit, the output signal outputs an input value when the clock signal changes from a low potential to a high potential, and otherwise retains the previous input value.

The resistance element according to the present invention can reduce the variation in the resistance value and the parasitic capacitance.
The power consumption of the LL can be reduced.

According to the resistance element of the present invention, a resistor having a small parasitic resistance can be obtained with high accuracy, and by using such a resistor, a circuit and a system with high speed and low power consumption can be constructed. In addition, by using the fine resistive element of the present invention which can be formed with high precision, the area occupied by the circuit and the system can be reduced.

[0078]

According to the embodiment of the present invention, since a low-resistivity polycrystalline silicon layer is used for extracting a resistance electrode, even if the resistance layer is over-etched at the time of processing the contact hole, the lower portion of the contact hole can be formed. The sheet resistance does not increase and the contact resistance can be prevented from increasing. Furthermore, since the extraction of the resistance electrode is performed through a low-resistance polycrystalline silicon layer or a low-resistance polycrystalline silicon layer and a low-resistance metal film provided on the polycrystalline silicon, an equivalent contact area is obtained. And the contact resistance can be greatly reduced. Further, even if the contact hole between the resistive layer and the polycrystalline silicon having a high impurity concentration is miniaturized, an extreme increase in contact resistance does not occur. Therefore, the miniaturization of the resistance width becomes easy, and a resistance with a small parasitic capacitance can be realized. . Therefore, when compared with the same resistance value, it is possible to realize a resistor having higher accuracy and less parasitic capacitance than a conventional polycrystalline silicon resistor. Therefore, if this resistor is used for a high-performance integrated circuit, the circuit performance can be dramatically improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a semiconductor device of the present invention.

FIG. 2 is a layout diagram schematically showing a planar structure of the semiconductor device of the present invention shown in FIG. 1;

FIG. 3 is a sectional view showing another embodiment of the semiconductor device of the present invention.

FIG. 4 is a layout diagram schematically showing a planar structure of the semiconductor device of the present invention shown in FIG. 3;

FIG. 5 is a sectional view showing another embodiment of the semiconductor device of the present invention.

FIG. 6 is a sectional view showing another embodiment of the semiconductor device of the present invention.

FIG. 7 is a sectional view showing a conventional single crystal silicon resistor.

FIG. 8 is a layout diagram schematically showing a planar structure of the conventional semiconductor device shown in FIG. 7;

FIG. 9 is a sectional view of a conventional polycrystalline silicon resistor.

FIG. 10 is a layout diagram schematically showing a planar structure of the conventional semiconductor device shown in FIG. 9;

FIG. 11 is an explanatory diagram showing the relationship between current flow in a contact portion, dimensions and constants of each portion, and contact resistance in a conventional polycrystalline silicon resistor.

FIG. 12 is an explanatory diagram showing a relationship between a contact overetch amount and a contact resistance in a conventional polycrystalline silicon resistor.

FIG. 13 is a sectional view of the semiconductor device in FIG. 1 in a manufacturing step;

FIG. 14 is a sectional view of the semiconductor device in FIG. 1 in a manufacturing step;

FIG. 15 is a sectional view of the semiconductor device in FIG. 1 in a manufacturing step;

FIG. 16 is a sectional view of the semiconductor device in FIG. 1 in a manufacturing step;

FIG. 17 is a sectional view of the semiconductor device in FIG. 3 in a manufacturing step;

FIG. 18 is a sectional view of the semiconductor device in FIG. 3 in a manufacturing step;

FIG. 19 is a sectional view of the semiconductor device in FIG. 3 in a manufacturing step;

FIG. 20 is a sectional view of the semiconductor device in FIG. 3 in a manufacturing step;

FIG. 21 is a sectional view of the semiconductor device in FIG. 5 in a manufacturing step;

FIG. 22 is a sectional view in a manufacturing step of the semiconductor device in FIG. 5;

FIG. 23 is a sectional view of the semiconductor device in FIG. 5 in a manufacturing step;

FIG. 24 is a sectional view of the semiconductor device in FIG. 5 in a manufacturing step;

FIG. 25 is a sectional view of the semiconductor device in FIG. 6 in a manufacturing step;

FIG. 26 is a sectional view of the semiconductor device in FIG. 6 in a manufacturing step;

FIG. 27 is a sectional view in a manufacturing step of the semiconductor device in FIG. 6;

FIG. 28 is a cross-sectional view of a bipolar integrated circuit to which the embodiment shown in FIG. 1 is applied.

FIG. 29 is a circuit diagram showing an example of an electronic circuit formed using the resistance element of the present invention.

30 is a sectional view of a front-end module of the optical transmission system in which the circuit of FIG. 29 is integrated.

FIG. 31 is a block diagram showing a configuration of an optical transmission system using a resistance element according to the present invention.

FIG. 32 is a block diagram showing a configuration of an optical transmission system using a resistance element according to the present invention.

FIG. 33 is a block diagram showing a configuration of a mobile radio terminal using a resistive element according to the present invention.

FIG. 34 is a circuit diagram of a D flip-flop used for a PLL prescaler of a mobile wireless terminal using a resistive element according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Support substrate, 11, 12, 13 ... Silicon dioxide (insulating film), 21, 22 ... N-type polycrystalline silicon, 31 ... Tungsten film, 32 ... Aluminum electrode, 41, 42 ... Contact hole.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Eiji Oue 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd. Inside the Central Research Laboratory of the Works (72) Inventor Yukihiro Ouchi 1-280 Higashi Koikekubo, Kokubunji-shi, Tokyo Inside the Central Research Laboratory of Hitachi, Ltd. Central Research Laboratory

Claims (13)

[Claims] A first conductive type first polycrystalline silicon layer and a second insulating film disposed on a supporting substrate with a first insulating film interposed therebetween; and the second insulating film and the first polycrystalline silicon layer. A second polycrystalline silicon layer arranged so as to be in contact with a part of the crystalline silicon layer, wherein the second polycrystalline silicon layer is of the same conductivity type as the first polycrystalline silicon layer and has a high impurity concentration; A semiconductor device, wherein the electrode of the first polycrystalline silicon layer is extracted through the second polycrystalline silicon layer. 2. The semiconductor device according to claim 2, wherein said second polysilicon layer is
Contact with the insulating film and a part of the first polycrystalline silicon layer, and a part of the first insulating film, and contact a contact surface between the first insulating film and the first polycrystalline silicon film with the first polycrystalline silicon layer. 2. The semiconductor device according to claim 1, wherein a contact surface between the first insulating film and the second polycrystalline silicon film is in contact with a contact surface between the first polycrystalline silicon film and the second polycrystalline silicon film. 3. The semiconductor device according to claim 2, wherein a contact surface between said first polycrystalline silicon film and said second polycrystalline silicon film is perpendicular to said support substrate. 4. The semiconductor device according to claim 1, wherein said first low-resistance metal film is provided so as to cover said second polycrystalline silicon film. 5. The second polycrystalline silicon film and the first low-resistance metal film provided in an opening of the second insulating film provided for taking out an electrode of the first polycrystalline silicon layer. 5. The semiconductor device according to claim 1, wherein the semiconductor device has a structure in which is embedded. 6. A step of sequentially depositing a first insulating film and a low-impurity-concentration first polycrystalline silicon layer on a supporting substrate; and ion-implanting impurities into the supporting substrate perpendicularly to the first substrate. Implanting impurities into said polycrystalline silicon layer, anisotropically etching and patterning a portion of said first polycrystalline silicon layer, and forming a second polycrystalline silicon film so as to cover said first polycrystalline silicon film. Depositing a second insulating film on the substrate surface; anisotropically etching the second insulating film on the first polycrystalline silicon layer to expose the first polycrystalline silicon film; Providing the second polycrystalline silicon film having the same conductivity type as that of the first polycrystalline silicon film and having a high impurity concentration so as to cover the opening of the second insulating film; Part of silicon layer is anisotropically etched and patterned That step a method of manufacturing a semiconductor device after depositing a third insulating film on the substrate surface, characterized in that comprising the step of forming the lead-out electrode which is patterned into a desired shape. 7. The method according to claim 1, further comprising: anisotropically etching said second insulating film to expose said first polycrystalline silicon film;
7. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of exposing the first insulating film by anisotropically etching the polycrystalline silicon film. 8. An additional step of selectively depositing a low-resistance metal film on the surface of the second polycrystalline silicon film after anisotropically etching and patterning the second polycrystalline silicon film. A method for manufacturing a semiconductor device according to claim 6. 9. A step of selectively depositing a low-resistance metal film on a substrate surface after anisotropically etching and patterning the second polycrystalline silicon film, and anisotropically etching and patterning the metal film. 8. The method for manufacturing a semiconductor device according to claim 6, further comprising the step of: 10. A semiconductor integrated circuit comprising at least one of the semiconductor device according to claim 1, 2, 3, 4 or 5, and a semiconductor device using the manufacturing method according to claim 6, 7, 8, or 9. 11. A light receiving element for receiving an optical signal and outputting an electric signal, a first amplifier circuit for receiving the electric signal from the light receiving element, and a second amplifier circuit for receiving an output of the first amplifier circuit. And the second clock in synchronization with a predetermined clock signal.
A discriminator for converting an output of the amplifier circuit into a digital signal, wherein the first amplifier circuit includes: a first bipolar transistor having a base connected to the light receiving element; A second bipolar transistor having its base connected to the collector of one bipolar transistor and having its emitter connected to the input of the second amplifier circuit; and a first bipolar transistor connected to the collector of the first bipolar transistor. A resistor, a first diode having an anode connected to the emitter of the second transistor, a second resistor connected between a cathode of the first diode and a power supply terminal, A third resistor connected between the cathode and the base of the first bipolar transistor; Kutomo One aspect 1,2,3,
10. An optical receiving system comprising a semiconductor device according to claim 4 or 5, and a semiconductor device using the manufacturing method according to claim 6, 7, 8, or 9. 12. Each of the first to third resistors includes:
An optical receiving system comprising the semiconductor device according to claim 1, 2, 3, 4, or 5, and a semiconductor device using the manufacturing method according to claim 6, 7, 8, or 9. 13. The method according to claim 12, wherein
A light receiving system in which the resistor is formed on a single semiconductor chip, and the light receiving element and the semiconductor chip are mounted on a single substrate.