JPH04179158A - Semiconductor signal generating circuit - Google Patents

Abstract

PURPOSE:To restrain a semiconductor signal generating circuit from increasing in assembly cost by a method wherein a variable capacitor and a voltage controlled oscillator are formed on the same chip. CONSTITUTION:A voltage feedback type oscillation circuit is provided, where the output of an amplifier A1 is fed back to an input through a capacitor C1. A resonance circuit composed of an inductor L1, a variable capacitance diode D1, and a capacitor C2 is connected to an input terminal. A control voltage is applied to the variable capacitance diode D1 through a resistor R. All these components excluding an inductor L1 are integrated on the same chip. Q1 and Q2 are bipolar transistors, and the emitters of them are connected to a constant current source. A feedback circuit is connected to the base of the transistor Q1 through the capacitors C1 and C2 via the collector of the transistor Q2. By this setup, as a variable capacitance diode is built in, a control voltage feed terminal can be dispensed with, and as an inductor can be mounted very close to an oscillation circuit, a resonance circuit small in loss can be constituted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a phase-locked loop (hereinafter abbreviated as Pr, L) used in a frequency synthesizer and FM demodulator for selecting a frequency in a wireless transmitter/receiver, etc. It belongs to the semiconductor signal generation circuit that constitutes the

In particular, a PLC that uses a voltage-controlled oscillator and a frequency divider circuit, etc., in the same chip, which is used in the low power supply voltage and high frequency range.
It belongs to LL integrated circuit.

[Conventional technology]

A known example of PLL is “A 700MHz
Nonolithic Phased-Locked
Loop", 1.985 LEEE International
onal So]j, d-5tate Cj, rcuj
tConference.

υAM2.1. pp, 22-23J. That is, in the conventional voltage controlled oscillator, a single variable capacitance diode was used to change the frequency of the voltage controlled oscillator, as shown in FIG. 3 on page 22 of the above-mentioned known document. In this configuration, a control voltage for the variable capacitance diode is obtained according to the output of the phase detection circuit.

Therefore, it was necessary to assemble a voltage controlled oscillator, a variable diode, a loop filter, an inductance, a capacitor, etc. on the board. Therefore, there are problems such as the influence of unnecessary radiation on the board and an increase in assembly cost, and these problems have not been taken into consideration. Furthermore, high-frequency radio transmitters and receivers such as cellular telephones require a frequency synthesizer with a fast response, and a voltage-controlled oscillator is used as the signal source. In order to realize a frequency synthesizer with high-speed response, complex control is required, resulting in a large-scale circuit configuration. Therefore, the aforementioned problems become increasingly important.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems such as the influence of unnecessary radiation on the board and increase in assembly cost, and to provide a high-performance semiconductor signal generation circuit. Another object of the present invention is to provide a high-speed, high-performance frequency synthesizer using the semiconductor signal generation circuit described above. The technical challenges for this purpose are to facilitate the controllability of the voltage-controlled oscillator, and to prevent unnecessary radiation and reduce assembly costs by integrating many circuits on the same chip. Another object of the present invention is to use the frequency synthesizer to realize a transmitter/receiver for a cellular telephone or the like that operates at a low power supply voltage of 5 µm or less.

[Means to solve the problem]

In the present invention, in order to facilitate the controllability of the voltage controlled oscillator, a variable capacitance diode is formed on the same chip as the voltage controlled oscillator. Furthermore, in PLL, the oscillation frequency is divided in order to compare it with the reference frequency, and this frequency dividing circuit is also integrated on the same chip.

Furthermore, when high-speed frequency division is required, power loss in the frequency divider circuit also increases. Therefore, emitter-coupled circuits (ECLs) are used for high-speed frequency divider circuits, and integrated injection logic circuits (integrated injection logic circuits) are used for low-speed circuits.
IIL), a portion of both are connected in series and a portion of the supplied current is shared, thereby reducing loss.

[Effect]

By forming the variable capacitance diode on the same chip as the voltage-controlled oscillator, it becomes easy to supply a control voltage for determining the capacitance value. In other words, the control voltage is generated from the relationship between the oscillator frequency and the reference frequency, but if both are on the same chip, the assembly will not become complicated even if the control voltage generation method is complicated or large-scale. do not have. In addition, integration of frequency divider circuits on the same chip also improves response speed.
Helps reduce assembly costs.

〔Example〕

Hereinafter, the present invention will be explained in detail according to examples.

FIG. 1 is for explaining a first embodiment of the present invention, which is a voltage feedback type oscillation circuit. The output of amplifier A1 is fed back to the input via capacitor C1. The input terminal has an inductance Ll, a variable capacitance diode D1, and a capacitor C2.
A resonant circuit consisting of is connected. A control voltage is applied to the variable capacitance diode through a resistor R. All of these components except the inductance are integrated on the same chip. FIG. 2 is a specific circuit diagram of this embodiment. Ql, Q2 are bipolar transistors whose emitters are connected to a constant current source. The feedback circuit is from the collector of Q2 to CI.

Connected to the base of Ql through C3.

A bias voltage VBB is applied to the base of Ql. Since this circuit has a built-in variable capacitance diode, there is no need for a control voltage supply terminal that is conventionally required.

Second, since the inductance can be mounted very close to the oscillation circuit, there is an advantage that a resonant circuit with low loss can be constructed.

FIG. 3 shows a second embodiment of the present invention, in which a voltage controlled oscillation circuit and a circuit for generating a control voltage to be applied to a variable capacitance diode are formed on the same chip. Conventional TV tuners, etc. have a variable frequency range of 300
In order to increase the frequency to about MHz, the control voltage is 20 to 30V.
was needed. However, in the present invention, the control voltage can be reduced because it is designed in a high frequency region and the frequency variable width is as narrow as 40 MHz, and therefore a control voltage generation circuit can be built-in.

FIG. 4 shows a cross-sectional structure of a specific integrated circuit for realizing a voltage controlled oscillation circuit according to an embodiment of the present invention.

Antimony is diffused at a high concentration into a p-type silicon substrate 1 of 10 Ω·cm to form an n-type region 7°7'. 2 on top of that
After forming an n-type layer 6.6' with a thickness of .mu.m by an epitaxial method, approximately 1.5 .mu.m of silicon is removed from areas other than the active region and the area corresponding to the electrode removal portion. A silicon oxide film 8 is formed on the portion where the silicon has been removed, and polycrystalline silicon 2, 3.3' is further formed on a portion thereof so as to be in contact with the side wall of the convex shape. Phosphorus is diffused at a high concentration into a portion of the convex silicon to form an n-type layer 9°9'. Boron is diffused into silicon through polycrystalline silicon 2 and 3 to form pJHt4. , I.Q.

After forming 10', phosphorus is diffused through the polycrystalline silicon 3, 3' to form n-type regions 11, 11'. The p-type layer 4 serves as a region to the base contact 1. The p-type region 12 formed by ion implantation from the surface serves as a base, and the n-type layer 5 serves as an emitter. On the other hand, the n-type layer 10 and the n-type layer 11.6'.

Since the pn junction between 7' and 7' is a super-step junction, it functions as a variable capacitance diode with a large rate of change.

Moreover, since the n-type layer 10 and ]O' are formed symmetrically, the n-type layer 6' between them is pinched off at 3 to 4 cm. By selecting the interval to', a variable capacitance diode with very low series resistance, ie, high Q, can be obtained. In this structure, the cathode 7' and p of the variable capacitance diode
Since a pn junction is formed with the shaped substrate 1, the circuit can be expressed as shown in FIG. 5(a). D4 in the figure can act as C2 in Figure 2, but since the resistance of the p-type substrate 1 is large, it is necessary to connect a capacitor with a small series resistance in parallel to obtain a high Q resonance circuit. There is.

On the other hand, in FIG. 4, if the n-type layers 10 and 10' are made into separate anode terminals, and the n-type layers 6' and 7' are made into a common cathode, a resonant circuit as shown in FIG. 5(b) is created. can be realized. In the same figure, D5. Since D6 functions as a variable capacitance diode with low loss, a high Q resonance circuit can be configured efficiently.

FIG. 6 shows the reverse bias voltage dependence of the variable capacitance diode in the embodiment shown in FIG. 4. p
Since the gap between the shaped layers 1.0 and 1.0' becomes a depletion layer when the gap is about 3 .mu., the change in capacitance becomes small at a voltage of 3 .mu. or more.

As is clear from the figure, maximum 0,5 pF/
The rate of change of V is obtained.

FIG. 7 is for explaining a third embodiment of the present invention, and shows a cross-sectional structure of a semiconductor integrated circuit. In this embodiment, high concentration p-type silicon is used as the semiconductor substrate 2. First, a high concentration of antimony is diffused onto the substrate 12.
A shaped layer 14 is formed.

Next, an n-type layer 13 of 10 Ω·Cm is formed on the substrate 12 by an epitaxial method. A p-type region 15 is formed by diffusing high concentration boron into the n-type layer 13, and an n-type region 16 is formed by diffusing high concentration antimony into the n-type layer 13. The following forming method was the same as that of the embodiment shown in FIG. 4. In this example, n
Since a pn junction diode is formed between the p-type layer 14 and the p-type substrate] 2, and the n-type layer 14 and the cathode 16 of the variable capacitance diode are directly connected, as shown in FIG.
) A resonant circuit consisting of two diodes can be easily realized. Moreover, since the series resistance of both diodes is small, a high Q resonant circuit can be obtained.

FIG. 8 is for explaining a fourth embodiment of the present invention, and shows a cross-sectional structure of a semiconductor integrated circuit including variable capacitance diodes on the same chip. In FIG. 8, 101 is a low resistance n-type substrate, 102 is a p-type layer, 103, 103'
is an n-type epitaxial layer, 1.04 is an n-type buried layer, 10
5 is a p-type layer for isolation, 1.07 is a base, 108 is an emitter, ], 09 is a p-type layer which is an anode of a variable capacitance diode. Bipolar transistors are formed in regions separated by p-type layers. Although not shown in the figure, it is clear that a CMO8 circuit or the like can also be formed in a region separated by a p-type layer. In this example, the cathode of the variable capacitance diode is a low resistance n-type substrate, so
The series resistance was significantly reduced, and a high Q variable capacitance diode was realized.

Hereinafter, the manufacturing process (4) of the fourth embodiment of the present invention will be explained with reference to FIG. First, as shown in FIG. 9(a), an n-type silicon substrate 1 with a resistance of 4i0.01Ω and a cry+
01-, the silicon in the region where element isolation is to be performed is removed by etching to a depth of 15 μm. next,
An n-type layer 112 approximately 20 μm thick is epitaxially grown. By polishing and polishing, the silicon surface is flattened, an n-type buried layer], 04 is formed, and the resistivity is 2.
．． An n-type layer 103 of 5Ω, cm is epitaxially grown. After forming the p-type separation layer and the n-swelled diffusion layer 106,
After forming elements such as bipolar transistors and completing most of the high-temperature heat treatment, a P-type layer 109 that will become the anode of the variable capacitance diode is formed.

Therefore, the pn junction of the variable capacitance diode becomes steep,
We were able to increase the rate of change.

FIG. 10 shows a method of applying a control voltage to a variable capacitance diode in a fourth embodiment of the present invention. In this embodiment, since the cathode of the variable capacitance diode is an n-type substrate, the substrate is connected to a power source. Therefore, a DC blocking capacitor C1,06 is connected in series to the external inductance.

FIG. 11 is for explaining the fifth embodiment of the present invention, which is a semiconductor device consisting of a voltage controlled oscillator including a variable capacitance diode on the same chip, a control voltage generation circuit, a frequency dividing circuit, and a phase comparator circuit. 1 shows a block diagram of an integrated circuit. In the same figure, the oscillation frequency is divided and the base ! (The phase is compared with the phase signal, a control voltage corresponding to the phase difference is generated, and this is fed back to the variable capacitance diode to form a phase-locked loop (PLL) and stabilize the frequency.

Since this integrated circuit has a built-in variable capacitance diode, troubles caused by assembly can be avoided.

Figures 1-2 are for explaining a sixth embodiment of the present invention, which consists of a voltage-controlled oscillator including a variable capacitance diode on the same chip, a control voltage generation circuit, a frequency divider circuit, and a phase comparison circuit. 1': Indicates a part of the conductor laminated circuit. In this embodiment, the resonant circuit of the voltage controlled oscillator is a variable capacitance diode I)], O.

It is composed of DC+i14 stopping capacitance C11 and inductance LIO. As in the fourth embodiment, the control voltage for controlling the frequency uses the voltage from the control voltage generation circuit, but in addition, a control voltage corresponding to the target frequency is set in advance, and this value is set in advance. By applying both at the same time, the response speed is increased. The initial value is set using an external control signal. [If the target frequency changes, the frequency division ratio of the frequency divider circuit must also be changed, so this is also done by an external control signal. Also in this embodiment, since the variable capacitance diode is built-in, troubles caused by assembly can be avoided. Moreover, since the initial value of the control voltage can be easily set, a PLL with high-speed response can be configured. 1 shows a portion of a semiconductor signal generation circuit that obtains a frequency of . In this example, since the input frequency is a high-speed frequency of 240 M I (z or more), an ECL circuit is used for the high-speed section and an IIL circuit is used for the low-speed section. In the figure, the input frequency fin After dividing the frequency by 4 in ECL circuit 1 and further dividing by 64 in ECL circuit 2, I
The frequency is divided by the IL circuit to obtain an output frequency of 1°. Ec r, circuit, and III, circuit are both circuits based on current switches, so current is constantly supplied. In this embodiment, the bias current of each circuit is E C
L circuit 1 is 0.8 mA, E CL @ route 2 is 1.2 m
A, Level shift 1~Circuit and others are 0,6 m A, L
i1. , circuit 1 is O, '3 m A, 1. i
I-.

Circuit 2 has a current of 1.2mA. Assuming these currents are provided individually, the total current is 4.2 mA. However, since the 1111 circuit operates with a power supply voltage of approximately 1V, ECr, circuit 2 and TIT, circuit 2 are connected in series, and the supply current Is to the ECL circuit is directly connected to I
It was supplied to L circuit 2. Here, since ECL circuit 1 operates at high speed, considering the influence on other circuits,
No cascade connection with the IL circuit is made. Similarly, for NIL circuit 1, since it operates at high speed as a T T L circuit, ECr
- No cascade connections with circuits are made. In this example,
Since part of the supply current (]8) was shared, the supply current could be reduced by 1.2 mA. That is, a reduction in power consumption of approximately 30% was achieved. It is clear that this circuit configuration has the advantage that the rate of reduction in power consumption increases as the scale of the cascade-connected circuits increases. In addition, if the present invention is used, a voltage controlled oscillator and a control voltage generation circuit including variable capacitance diodes on the same chip.

In a semiconductor integrated circuit comprising a frequency divider circuit and a phase comparator circuit, there is an advantage that a frequency divider circuit with low loss can be provided.

FIG. 14 is for explaining the eighth embodiment of the present invention, and shows a block diagram of a frequency synthesizer using the signal generation circuit of the present invention. The synthesizer includes a semiconductor integrated circuit that includes a fixed frequency divider circuit for frequency dividing a reference signal, a voltage controlled oscillator including a variable capacitance, a variable frequency divider circuit for dealing with frequency settings, a phase comparison circuit, etc. External components such as a control circuit that controls the frequency, a low-pass filter, and an inductance are made up of components. Since this synthesizer uses a voltage-controlled oscillator that includes a variable capacitor, there are no problems such as parasitic oscillation, and high-speed response is possible.

FIG. 15 is for explaining a ninth embodiment of the present invention, and shows a block diagram of a wireless transceiver using the signal generation circuit of the present invention. In this configuration, the transmission and reception frequencies are controlled using the signal generator of the present invention. Since the radio frequency bandwidth is 30 M I-I z, a variation width of about 30% of the variable capacitance is sufficient. Therefore, by using the structure of the present invention, it was possible to achieve an amplitude of the control voltage of about 2. That is, there is no need for a high control voltage as in the conventional device, the control voltage generation circuit can also be operated with a 5V power supply, and miniaturization has also been achieved.

〔Effect of the invention〕

As described above, by configuring the variable capacitor on the same chip as the voltage-controlled oscillator, problems such as the influence of unnecessary radiation on the board and increased assembly cost can be solved. Further, since the control voltage can be reduced by using the structure of the present invention in which the rate of change in capacitance is large in the low voltage region, it is possible to configure a frequency synthesizer with one power supply including the control voltage. Furthermore, in order to facilitate the controllability of the voltage controlled oscillator, a variable capacitance diode is formed on the same chip as the voltage controlled oscillator, and a frequency dividing circuit is also integrated on the same chip, thereby improving performance. Cost reduction can be achieved. Furthermore, by using an emitter-coupled circuit (ECL) for the high-speed frequency divider circuit and an integrated injection logic circuit (IIL) for the low-speed circuit, and by connecting parts of both in series, a part of the supply current can be shared. By doing so, it is possible to reduce loss and provide a high-performance frequency synthesizer. In addition, by using the structure of the present invention, a large frequency variable width can be achieved with a control voltage amplitude of about 2V, which eliminates the need for high-voltage control voltages as in conventional devices, allowing for miniaturized wireless transceivers. It can be achieved.

[Brief explanation of drawings]

FIG. 1 is a circuit of a voltage controlled oscillator showing a first embodiment of the present invention, FIG. 2 is a specific circuit diagram, FIG. 3 is a voltage controlled oscillator of a second embodiment, and FIG. is a cross-sectional structure of a semiconductor integrated circuit, FIG. 5 is an equivalent circuit of a resonant circuit, FIG. 6 is a voltage dependence of capacitance, FIG. 7 is a cross-sectional structure of a third embodiment, and FIG. 8 is a fourth embodiment. 9 is an explanatory diagram of the manufacturing process, FIG. 10 is a diagram showing the control voltage application method, FIG. 111 is a block diagram of the fifth embodiment, and FIG. 12 is the P of the sixth embodiment.
FIG. 13 is a block diagram of the seventh embodiment, FIG. 14 is a block diagram of a frequency synthesizer using a semiconductor signal generation circuit, and FIG. 15 is a block diagram of a wireless transceiver. Dl... Variable capacitance diode, Ll... Inductance, 1... P-type substrate, 2... Polycrystalline silicon, 4...
...p-type region, 6...n-type layer, 6'...n-type layer, 1
0... N type layer, 11... N type layer, 12... Low resistance p type substrate, 13... N type layer, 14... Low resistance n type region, 20... N type Layer, 101...Low resistance n-type substrate, 1
02...n-type layer, 109 [-Id'l lips h N Q to Uichi-OL,) \ノ () ・, Nohi←
(←

Claims (1)

[Claims] 1. A semiconductor signal generation circuit that includes a voltage-controlled oscillator and a variable capacitor for controlling its frequency on the same chip. 2. A semiconductor signal generation circuit including, on the same chip, a voltage-controlled oscillator, a variable capacitance for controlling its frequency, and a control voltage generation circuit for generating a voltage for controlling the capacitance of a variable capacitance diode. 3. The semiconductor signal generating circuit according to claim 2, wherein the control voltage generating circuit according to claim 2 is supplied with power from the same power source as other circuits on the same chip. 4. The semiconductor signal generating circuit according to claim 2 or 3, wherein the control voltage is 5 V or less in the control voltage generating circuit according to claim 2 or 3. 5. The semiconductor signal generation circuit according to any one of claims 1 to 4, comprising a voltage controlled oscillator, its control voltage generation circuit, a frequency dividing circuit, and a phase comparison circuit on the same chip. 6. Claim 1, characterized by comprising means for initially setting the frequency of the voltage controlled oscillator using an external control signal and means for controlling it using an internal control voltage.
6. The semiconductor signal generation circuit according to any one of items 5 to 5. 7. A voltage-controlled oscillator is constructed using a low-resistance n-type region formed in a semiconductor substrate, an n-type convex silicon region formed on a portion of the same region, and a polygonal oscillator formed on the sidewall or surface of the same region. A bipolar transistor is formed using a crystalline silicon layer, a p-type base/contact region formed by diffusion from the same polycrystalline silicon layer, and a base and emitter formed from the surface of the convex silicon region. A low resistance n-type region formed, an n-type convex silicon region formed on a part of the region, a polycrystalline silicon layer formed on the sidewall or surface of the region, and a polycrystalline silicon layer formed by diffusion from the polycrystalline silicon layer. 7. The semiconductor signal generating circuit according to claim 1, wherein a variable capacitance diode formed of p-type and n-type regions is used to control frequency. 8. A voltage-controlled oscillator is formed on a p-type high-resistance layer formed on a low-resistance p-type semiconductor substrate, a low-resistance n-type region formed within the p-type high-resistance layer, and a part of the same region. a polycrystalline silicon layer formed on the sidewall or surface of the n-type convex silicon region; a p-type base contact region formed by diffusion from the polycrystalline silicon layer; and a surface of the convex silicon region. An n-type low resistance layer formed in a semiconductor substrate, a p-type high resistance layer formed on the n-type low resistance layer, and a p-type bipolar transistor formed using a bipolar transistor consisting of a base and an emitter formed from a semiconductor substrate. A low-resistance n-type region formed within a high-resistance layer, an n-type convex silicon region formed on a portion of the same region, a polycrystalline silicon layer formed on the sidewall or surface of the same region, the same polycrystalline silicon region 7. The semiconductor signal according to claim 1, wherein a variable capacitance diode comprising p-type and n-type regions formed by diffusion from a silicon layer is used for frequency control. generation circuit. 9. A claim characterized in that the pn junction capacitance formed by the semiconductor substrate according to claim 8 and a low resistance n-type region formed on the semiconductor substrate is used as a coupling capacitance or a bypass capacitance. The semiconductor signal generation circuit according to any one of Items 1 to 6 and Item 8. 10. Step of forming a p-type region on a low-resistance n-type substrate;
The process of removing a part of the epitaxial layer or converting it into an n-type layer, using the buried p-type layer formed by growing an n-type epitaxial layer for element isolation, and using the p-type layer formed within the n-type epitaxial layer as an anode. 7. The semiconductor signal generating circuit according to claim 1, wherein a variable capacitance diode is formed with a low resistance n-type substrate as a cathode to control the frequency. 11. In a signal generation circuit that obtains a desired frequency by a frequency dividing function, the high-speed operation circuit is configured with an emitter coupled circuit (ECL), the low-speed operation circuit is configured with an integrated injection logic circuit (IIL), and the A semiconductor signal generation circuit characterized in that a part of the current supplied from a power supply is shared by connecting parts of both circuits in series. 12. The semiconductor signal generating circuit according to claim 11, wherein the signal generating circuit obtains a desired frequency by a frequency dividing function, and includes a voltage controlled oscillator on the same chip. 13. Claim 11, characterized in that a signal generation circuit that obtains a desired frequency by a frequency dividing function includes a voltage controlled oscillator and a variable capacitor for controlling the frequency on the same chip. The semiconductor signal generation circuit described in . 14. A frequency synthesizer circuit using the semiconductor signal generation circuit according to any one of claims 1 to 13. 15. A wireless transceiver using the semiconductor signal generation circuit according to any one of claims 1 to 13.