JPH08298328A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To improve the drain saturation current of MOSFET and the with stand voltage between the source and the drain, and enable the high speed operation by reducing the parasitic resistances of the source and the drain and the gate parasitic capacitance. CONSTITUTION: Source.drain electrodes 12 composed of a single crystal silicon film of low resistance are formed on a thin source-drain diffusion layer 12. The angle of gate side end portion of the silicon film is smaller than 90 deg.. A gate electrode 13 is isolated from the source.drain electrodes 12 by an isolation oxide film 9. The portion where the source drain electrodes are the most adjacent to the gate electrode 13 is isolated by a gate oxide film 11. Thereby the leak current due to punch through between the source and the drain and withstand voltage deterioration are abated, and parasitic resistances of the source and the drain are reduce, so that the drain saturation current is increased, the gate parasitic capacitance is reduce, and the operation speed is remarkably improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it suppresses a leak current between a source electrode and a drain electrode of a field effect transistor to increase a drain saturation current, thereby increasing parasitic capacitance and parasitic capacitance. A semiconductor device suitable for reducing series resistance and this semiconductor device are
The present invention relates to a method for manufacturing a semiconductor device that can be formed by a self-alignment technique.

[0002]

2. Description of the Related Art Conventional MOS (Metal-Oxcide-Semiconduc)
In a tor) type field effect transistor (hereinafter referred to as MOSFET), when the gate length is shortened, the leak current caused by the punch-through phenomenon between the source electrode and the drain electrode is suppressed, and the field effect transistor between the source electrode and the drain electrode is suppressed. In order to increase the drain saturation current and reduce the operation delay time of a semiconductor integrated circuit by reducing the parasitic series resistance, a method of stacking low resistance electrodes on the source and drain diffusion layers is disclosed in, for example, Japanese Patent Laid-Open No. -3614, JP-A-55-4964 and JP-A-56-66074.

Among these, Japanese Patent Application Laid-Open No. 58-3614 discloses a transistor having a sectional structure shown in FIG. In this transistor, a low-resistance source electrode 76 and a low-resistance drain electrode 77 made of high-impurity concentration silicon are stacked on the source diffusion layer 73 and the drain diffusion layer 74, respectively. Inter-electrode separation insulation film 7
It is equipped with 5. By stacking the low-resistance source electrode 76 and the drain electrode 77 on the source diffusion layer 73 and the drain diffusion layer 74, respectively,
It has an advantage that the parasitic series resistance between the source electrode 76 and the drain electrode 77 can be reduced, thereby increasing the drain saturation current. The transistors disclosed in JP-A-55-4964 and JP-A-56-66074 also have the same structure and advantages.

In addition, the 1992 International Electron Devices Meeting, IE
DM92), 853 to 856, see Figure 4 (b).
A transistor having the cross-sectional structure shown in is disclosed. A source electrode 84 and a drain electrode 85 made of a silicon film formed on the semiconductor substrate 80, and a source diffusion layer 86 and a drain diffusion layer 8 formed thereon.
7, the gate electrode 82 formed on the semiconductor substrate 80 via the gate oxide film 81, and the inter-electrode isolation insulating film 8
3 is provided.

This transistor is different from the transistor shown in FIG. 4A in that a source electrode 84 and a drain electrode 85 formed on a semiconductor substrate 80, respectively.
Of the side surface on the side of the gate electrode 82 and the upper surface of the semiconductor substrate 80 is smaller than 90 degrees, and the impurity ions inside the source electrode 84 and the drain electrode 85 are near the surface of the source and drain electrodes 84, 85. Two points are that it is injected into a part. Due to the former difference, the gate parasitic capacitance between the stacked electrodes 84 and 85 and the gate electrode 82 can be reduced, and due to the latter difference, the source electrode 84 and the drain electrode 85.
The parasitic junction capacitance between the semiconductor substrate 80 and the semiconductor substrate 80 can be reduced.

[0006]

In the conventional transistor shown in FIG. 4A, the bottom of the isolation insulating film 75 is in direct contact with the source diffusion layer 73 and the drain diffusion layer 74, respectively, and between them. The low resistance source electrode 76 and drain electrode 77 are not interposed. Therefore, if the diffusion depth of both diffusion layers 73 and 74 is made shallow for the purpose of suppressing punch-through between the source diffusion layer 73 and the drain diffusion layer 74, the film resistance of both diffusion layers 73 and 74 increases, The parasitic series resistance between the electrode 76 and the drain electrode 77 increases, and the drain saturation current decreases. In order to solve this problem, if the isolation insulating film 75 is eliminated or thinned, the source electrode 76 and the drain electrode 7 are removed.
A leak current flows between the gate electrode 7 and the gate electrode 72, or the gate parasitic capacitance increases.

In the conventional transistor shown in FIG. 4B, the source diffusion layer 86 and the drain diffusion layer 87 are also included.
If the diffusion depth of is reduced, the film resistance of these diffusion layers 86 and 87 increases, the parasitic series resistance between the source electrode 84 and the drain electrode 85 increases, and the drain saturation current decreases. Particularly, in the conventional transistor shown in FIG. 4B, the portions of the source diffusion layer 86 and the drain diffusion layer 87 formed in the semiconductor substrate 80 are
Since it is only inside the end portions of the source electrode 84 and the drain electrode 85 and is not formed immediately below both electrodes 84, 85, the film resistance between the two stacked electrodes 84, 85 is extremely high, and the source electrode 84 The parasitic series resistance between the drain electrode 85 and the drain electrode 85 increases remarkably.
It has been difficult to speed up integrated circuits using SFETs.

An object of the present invention is to solve the problems of the above-described conventional transistor, and to prevent current leakage and breakdown voltage deterioration due to the punch-through phenomenon between the source electrode and the drain electrode, which occurs with the miniaturization of the gate length of the MOSFET. A semiconductor device capable of high-speed operation and a semiconductor device capable of forming this semiconductor device with high accuracy by suppressing increase in electrode parasitic resistance, decrease in drain saturation current and increase in inter-electrode parasitic capacitance It is to provide a manufacturing method of.

[0009]

To achieve the above object, the present invention forms a shallow source / drain diffusion layer having a second conductivity type in a surface region of a semiconductor layer having a first conductivity type, The high-concentration silicon film having the second conductivity type and the gate electrode, which are stacked on the surface of the shallow source / drain diffusion layer, are insulated and separated from each other by an isolation insulating film, and the gate of the silicon film is formed. The end portion on the electrode side is inclined by 90 degrees or less with respect to the surface of the semiconductor layer.

That is, FIG. 3 and FIG. 1 respectively show an example of the planar structure of the MOSFET of the present invention and its AA ′ sectional structure. As is clear from FIG. 1, this MO
The SFET is formed on the thin single crystal silicon film 3 having the first conductivity type formed on the silicon oxide film 2,
In the single crystal silicon film 3, there is formed a second crystal opposite to the first conductivity type.
Impurity diffusion layers 7 and 12 having a conductivity type are formed, and further, a source / drain electrode 8 and a gate oxide film 11 made of a low resistance silicon film having a second conductivity type stacked on the single crystal silicon film 3 are formed. A gate electrode 13, 15, a metal source electrode 14, a metal drain electrode 16 and a silicon oxide film 9 for separating these electrodes 14, 16 from each other are provided.

The low resistance silicon film 8 is formed on the gate electrode 13
In the part closest to the gate oxide film 11
And the ends are separated from each other. The angle between the side surface of the low resistance silicon film 8 on the gate electrode 13 side and the surface of the single crystal silicon film 3 is 90 degrees or less. Further, the second conductivity type impurity ions are uniformly and highly implanted inside the low resistance silicon film 8.
The conductivity type impurity diffusion layer 12 is formed by impurity diffusion from the low resistance silicon film 8, and the impurity diffusion depth is appropriately controlled by controlling the heat treatment temperature and time at that time.

[0012]

The impurity diffusion layer 12 having the second conductivity type formed on the surface of the single crystal silicon film 3 is the low resistance silicon film 8
Since it is formed by solid-phase diffusion using as a diffusion source, a very shallow diffusion layer 12 having a diffusion depth of 50 nm or less can be formed, and a punch-through phenomenon between the source and drain electrodes and this phenomenon when the gate length is shortened. It is possible to effectively suppress the leakage current and the breakdown voltage deterioration based on the above. Although the film resistance is increased because the impurity diffusion layer 12 is thin, the low resistance silicon film 8 is formed thereon, and the gate electrode 1 is formed through the extremely thin gate oxide film 11 having a film thickness of 10 nm or less.
3, the increase in the source and drain electrode parasitic series resistance is effectively suppressed.

The diffusion of the second conductivity type impurity from the low resistance silicon film 8 also occurs in the lateral direction, and the gate insulating film 11 separating the low resistance silicon film 8 and the gate electrode 13 is extremely thin, so that the impurity diffusion layer 12 is formed. And the gate electrode 13 can be overlapped, and the drain saturation current is effectively increased.

Since the angle between the side surface of the low resistance silicon film 8 on the gate electrode 13 side and the surface of the single crystal silicon film 3 is 90 degrees or less, the isolation oxide film interposed between the low resistance silicon film 8 and the gate electrode 13 is formed. The thickness of 9 becomes thicker in the upper part,
An increase in the gate parasitic capacitance between the source electrode 14 and the drain electrode 16 and the gate electrode 15 is suppressed. In addition,
As is apparent from FIG. 1, the second conductivity type impurity diffusion layer 7
However, since it reaches the surface of the thick oxide film 2, the parasitic junction capacitance between the thin second conductivity type impurity diffusion layer 12 and the single crystal silicon film 3 is reduced.

As is apparent from the measurement results of the electrical characteristics shown in FIG. 5, the characteristics 51 and 53 obtained by the present invention.
Are characteristics 50 and 5 obtained by the conventional MOSFET.
Compared with 2, it is possible to efficiently increase the drain saturation current while suppressing an increase in the gate parasitic capacitance.

[0016]

EXAMPLES Example 1 A first example of the present invention in which a MOSFET is formed using a thin film silicon substrate will be described with reference to FIGS. 1, 3 and 6 to 11. FIG. 1 shows the M shown in FIG.
FIG. 6 is a cross-sectional view taken along the line AA ′ of the OSFET, and FIGS. 6 to 11 are process diagrams showing the method for manufacturing the FET.

First, as shown in FIG. 6, single crystal silicon is grown on a silicon oxide film 2 formed on a silicon substrate 1 by a known method to have a thickness of about 50 nm.
Thin monocrystalline silicon film 3 is formed, the monocrystalline silicon film 3 is processed into a desired shape, and then a silicon nitride film 4 having a thickness of approximately 200 nm is formed by a known CVD method. Was processed into a predetermined shape by reactive ion etching. The processed silicon nitride film 4 crosses the single crystal silicon film 3.

Next, as shown in FIG. 7, the film thickness is 10 nm.
After forming the front and rear thin silicon oxide films 5 on the entire surface, a polycrystal silicon film having a film thickness of about 100 nm is formed on the whole surface, and the polycrystal silicon film is subjected to full anisotropic dry etching to obtain the silicon nitride film 4 described above. The polycrystalline silicon film 6 is left only on the side walls of the above, and removed from other portions. In this state, the second conductivity type impurity ions were implanted into the single crystal silicon film 3 through the silicon oxide film 5 to form the second conductivity type impurity diffusion layer 7.

After removing the polycrystalline silicon film 6 and the silicon oxide film 5, the concentration is 1 × 10 ²⁰ / cm 2 by a well-known low pressure chemical vapor deposition method (hereinafter referred to as LPCVD method).
A high-concentration single crystal low resistance silicon film 8 having a film thickness of about 100 nm containing ^three or more second conductivity type impurities is selectively grown only on the single crystal silicon film 3 so that the second conductivity type impurities are evenly distributed. A single crystal low resistance silicon film 8 diffused at a high concentration was formed. At this time, a surface called a facet having a different crystal orientation from the surface of the single crystal silicon film 3 and forming a certain angle with the surface of the single crystal silicon film 3 is a low resistance silicon film near the silicon nitride film 4. 8 was formed. As a result, the angle of the side surface of the single crystal low resistance silicon film 8 in the vicinity of the silicon nitride film 4 with respect to the surface of the single crystal silicon film 3 was 60 degrees or less, as shown in FIG. The growth conditions for the single crystal low resistance silicon film 8 are as follows: temperature 700 to 800 ° C., gas pressure 0.1 to 10 Torr, impurity concentration 1 × 10 ¹⁹ to 1 × 10 ²¹ / cm ³ , source gas and carrier gas. The mixing ratio is preferably 1: 1 to 1: 1000, and a good single crystal silicon film could be formed by growing under this condition.

After forming a silicon oxide film having a thickness of about 200 nm on the entire surface, anisotropic dry etching is performed to remove unnecessary portions, and as shown in FIG. The silicon oxide film 9 is left.

The silicon nitride film 4 is removed, and impurity ions of the first conductivity type are selectively implanted only in the region where the silicon nitride film 4 has been removed to punch-through stopper layer 10.
Then, the exposed surface of the single crystal silicon film 3 was oxidized to form a thin gate oxide film 11 having a film thickness of 10 nm or less as shown in FIG. At this time, the exposed surface of the single crystal low resistance silicon film 8 was simultaneously oxidized.

A heat treatment is performed by a well-known short-time annealing method such as a lamp annealing method to diffuse the second conductivity type impurity from the single crystal low resistance silicon film 8 to the single crystal silicon film 3, and the diffusion depth is 50 nm or less. The shallow impurity diffusion layer 12 was formed. The silicon nitride film 4 is formed by forming a metal film such as tungsten and performing well-known selective etching.
The gate electrode 13 made of the above metal is formed in the region where
Was formed. Further, a metal film such as tungsten is selectively formed only on the surfaces of the gate electrode 13 and the single crystal low resistance silicon film 8 by the formation of a well-known metal film and its selective etching, and the source electrode 14, the gate electrode 1
5 and the drain electrode 16 were formed to form the MOSFET shown in FIG. Finally, necessary wiring such as internal wiring and power supply wiring was performed to complete a semiconductor integrated circuit using this MOSFET.

According to the present embodiment, punch-through is prevented, so that deterioration of breakdown voltage and occurrence of leak current due to punch-through are much less, drain saturation current is higher, and source and drain electrodes are used. Many remarkable effects such as a small parasitic junction capacitance between the gate electrodes were recognized, and a high-speed MOSFET could be obtained.

The IV characteristic obtained by the present invention is shown in FIG.
Shown in 2. As is clear from this figure, for example, in an nMOSFET having a gate length of about 0.1 μm, the drain saturation current is reduced to 1 while suppressing a decrease in the threshold voltage due to the short channel effect and a deterioration in the breakdown voltage between the source and the drain.
It was possible to obtain good characteristics of about mA.

<Embodiment 2> This embodiment is an example in which the MOSFET shown in FIG. 2 is formed by partially changing the manufacturing process of Embodiment 1 described above. In this embodiment, in order to simplify the manufacturing process shown in the first embodiment, the thickness of the single crystal silicon film 3 is reduced to about 30 nm or less, and the second conductivity type diffusion layer 7 and the first conductivity type punch are formed. The formation of the through stopper layer 10 is eliminated, and the second conductivity type diffusion layer 12 is in contact with the silicon oxide film 2. Further, the cross-sectional shape of the end portion of the single crystal low resistance silicon film 8 on the gate electrode 13 side was partially changed as shown in FIG. Also in this embodiment, the same effect as that of the above-mentioned Embodiment 1 was obtained, and a high-speed MOSFET could be realized.

<Third Embodiment> A third embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 12, a thin film silicon substrate including a silicon oxide film 22 and a silicon film 23 formed thereon with a thickness of about 50 nm is prepared, and the silicon film 23 is formed by well-known photoetching. Was processed into a desired shape.

Next, the exposed surface of the silicon film 23 is oxidized to form a thin gate oxide film 24 having a film thickness of 10 nm or less, and then a film having a film thickness of 100 nm and a second conductivity type impurity having a concentration of 1 are formed.
High-concentration polycrystalline silicon film containing x10 ²⁰ / cm ³ or more 2
5 and a silicon nitride film 26 having a film thickness of 150 nm are laminated and processed into a predetermined shape by well-known reactive ion etching, and as shown in FIG. 13, a polycrystalline silicon gate electrode 25 and a gate step 26 are formed. Was formed.
The planar structure in this state is the polycrystalline silicon gate electrode 2
5 and the gate step 26 are structured to cross the silicon film 23.

Thin silicon oxide film 2 having a thickness of 20 nm or less
7 is formed on the entire surface, then impurity ions of the first conductivity type are implanted into the silicon film 23 through the thin silicon oxide film 27 to form the punch-through stopper layer 2 having the first conductivity type.
8 was formed.

The thin silicon oxide film 27 is etched by anisotropic dry etching to leave the silicon oxide film 27 only on the sidewalls of the gate step 26 and the gate electrode 25, as shown in FIG. Was removed.

Next, by the well-known LPCVD method, the second
A high-concentration single-crystal silicon film 30 having a film thickness of 100 nm was added while containing conductive impurities at a concentration of 1 × 10 ²⁰ / cm ³ or more.
It was selectively grown only on the punch-through stopper layer 28. At this time, a plane (referred to as a facet plane) having a different crystal orientation from that on the punch-through stopper layer 28 and forming a predetermined angle with the surface of the silicon film 23 is a silicon film around the gate electrode 25. 30 was formed.
By doing so, the upper surface of the single crystal silicon film 30 around the gate step has an angle of 60 degrees or less with respect to the surface of the silicon film 23, as shown in FIG.

Next, a silicon oxide film 3 having a film thickness of 200 nm is formed.
1 is formed on the entire surface, and as shown in FIG. 15, anisotropic dry etching is performed to remove unnecessary portions, then first conductivity type impurity ions are implanted into the silicon film 30, and further annealing is performed, The implanted first conductivity type impurity ions are diffused from the silicon layer 30 into the punch-through stopper layer 28 thereunder, so that a second conductivity type impurity diffusion layer 32 is formed in the silicon film 23.

The silicon nitride film 26 is removed, and a desired short-time anneal such as a lamp anneal method is performed to use the single crystal silicon film 30 as a solid-phase diffusion source to introduce impurities of the second conductivity type into the silicon film 23. Diffuse with a diffusion depth of 5
A shallow impurity diffusion layer 33 having a thickness of 0 nm or less was formed on the surfaces of the punch-through stopper layer 28 and the impurity diffusion layer 32. At this time, the impurity diffusion layer 33 and the gate electrode 25 were overlapped by making the lateral diffusion distance deeper than the film thickness of the sidewall silicon oxide film 27.

Next, a metal film of tungsten or the like is applied to the polycrystalline silicon gate electrode 2 and the single crystal silicon film 30.
The source electrode 34, the gate electrode 35, and the drain electrode 36 were selectively formed only on the exposed surface, and the MOSFET shown in FIG. 16 was formed. Here, a single layer film of metal silicide made of a compound of metal and silicon may be used instead of each electrode made of a two-layer film of a metal film such as tungsten and a silicon film. Finally, perform necessary wiring such as internal wiring and power supply line,
A semiconductor integrated circuit using FETs has been completed.

In this embodiment, unlike the first embodiment, a thin silicon oxide film 29 is used for separating the electrodes.
Since the film thickness is 20 nm or less, which is very thin, the electrode parasitic resistance is reduced and the drain saturation current is increased as in the case of the first embodiment. It was realized.

<Embodiment 4> A fourth embodiment of the present invention will be described with reference to FIG. In the fourth embodiment, the silicon film is
When selectively growing only on the silicon film 23 by the LPCVD method, first, impurities of the second conductivity type are not included,
A single crystal silicon film 40 having a film thickness of about 30 nm is selectively grown, and then an impurity source gas having a second conductivity type is allowed to flow at the same time as the growth, so that the second conductivity type impurity has a concentration of 1
A film containing x10 ²⁰ / cm ³ or more was grown thereon, and a high-concentration single crystal silicon film 41 with a total film thickness of 70 nm was selectively grown.

Next, in the same manner as in Example 3, second conductivity type impurity ion implantation was performed to form a second conductivity type impurity diffusion layer 42 inside the silicon film 23. further,
A short-time anneal such as a lamp anneal is performed to use the high-concentration second-conductivity-type single-crystal silicon film 41 as a solid-phase diffusion source to introduce the second-conductivity-type impurities into the silicon film 40 to a depth of 10 nm.
Diffused. As a result, from the single crystal silicon film 41 to the second
The single crystal silicon film 40 with a film thickness of 20 nm in which the conductive impurities were not diffused remained.

After removing the polycrystalline silicon electrode 25, the sidewall silicon oxide film 27 and the silicon oxide film 24, a thin gate oxide film 43 having a film thickness of 10 nm or less and a gate electrode 44 made of metal such as tungsten are formed. The MOSFET shown in FIG. 17 was formed in the same manner as in Example 3.

In this embodiment, the high-concentration second-conductivity-type single-crystal silicon film 41 to be the source and drain diffusion layers is
Since the gate oxide film 43 is located at a position higher than the surface of the silicon film 23 provided, a leak current between the source and drain electrodes due to the punch-through phenomenon is generated.
It could be suppressed more effectively. In addition, the above-mentioned Example 1
The same effect as was obtained, and a high-speed MOSFET could be realized.

<Embodiment 5> The present invention is a complementary MOSFET.
An embodiment applied to (hereinafter referred to as CMOSFET),
This will be described with reference to FIGS. In these figures, the nMOSFET is shown on the left side and the pMOSFET is shown on the right side.

First, as shown in FIG. 18, the element isolation trench 103 in which the element isolation silicon oxide film 102 and the insulating film are filled in the silicon substrate 101 and the p-type well diffusion are used by a known method such as thermal oxidation. A layer 104 and an n-type well diffusion layer 105 were formed, and a silicon film 106 having a film thickness of 20 nm was formed on the entire surface. At this time, the silicon substrate 1
A single crystal silicon film was grown on the region where the surface of 01 was exposed, and a polycrystalline silicon film was formed on the element isolation silicon oxide film 102.

Next, after the silicon film 106 is processed into a desired shape by known photo-etching, a film thickness of 2 is obtained.
A silicon nitride film 107 having a thickness of 00 nm was formed, and as shown in FIG. 19, processed into a predetermined shape by dry etching. Looking at the planar shape in this state, the silicon nitride film 107 crosses the silicon film 106. p
Type and n-type impurity ions are selectively implanted into the silicon substrate 101 and the silicon film 106 to form the p-type punch-through stopper layer 108 and the n-type punch-through stopper layer 109, respectively.

Using the well-known LPCVD method, the n-type impurity is contained at a concentration of 1 × 10 ²⁰ / cm ³ or more and the film thickness is 10
The n ⁺ -type single crystal silicon film 110 of 0 nm is
Selectively grows only on the silicon film 106 in the ET region,
Further, the p ⁺ -type single crystal silicon film 11 having a film thickness of 100 nm is added while containing the p-type impurity at a concentration of 1 × 10 ²⁰ / cm ³ or more.
1 was selectively grown only on the silicon film 106 in the pMOSFET region. At this time, as shown in FIG. 20, a facet plane, which has a different crystal orientation from the surface of the silicon film 106 and forms a predetermined angle with the surface of the silicon film 106, is a silicon near the silicon nitride film 107. Membrane 1
10 and 111 respectively. as a result,
Silicon nitride film 1 of single crystal silicon films 110 and 111
The side surface on the 07 side is 60 with respect to the surface of the silicon film 106.
The angle was less than or equal to a degree, and the silicon films 110 and 111 became high-concentration polycrystalline silicon films on the element isolation oxide film 102.

After forming a 200 nm-thickness silicon oxide film on the entire surface, anisotropic dry etching is performed to leave the silicon oxide film 112 on the side wall of the silicon nitride film 107.
The other part was removed. Next, the silicon films 110 and 1
The exposed surface of 11 was oxidized to form a silicon oxide film 113 having a film thickness of 50 nm as shown in FIG.
Next, a desired heat treatment is performed using a short-time annealing device such as lamp annealing, and the silicon films 110 and 111
N-type impurities and p-type impurities are respectively diffused into the silicon film 106 from the
-Type impurity diffusion layer 115 and shallow p-type impurity diffusion layer 11
6 was formed. At this time, the diffusion depth was controlled so that the impurity diffusion layers 115 and 116 reach the element isolation silicon oxide film 102, respectively. In addition, the impurity diffusion layer 115,
The concentration of 116 is the punch-through stopper layers 108, 10
Since the impurity concentrations of the punch-through stopper layers 108 and 109 are adjusted so as to be one digit or more higher than the impurity concentration of 9, the n-type impurity diffusion layer 115 and the p-type impurity diffusion layer 116 can be formed. did it.

The silicon nitride film 107 is removed, the exposed surface of the silicon film 106 is oxidized to form a thin gate oxide film 114 having a film thickness of 10 nm or less, and a metal film such as tungsten is formed and selective etching is performed. To form the gate electrode 117 made of metal, and the CM shown in FIG.
The OSFET was formed. Finally, necessary wiring such as internal wiring and power supply wiring was performed to complete the semiconductor integrated circuit.

Since this embodiment also includes the transistor having the same characteristics as described above, it is natural that the same characteristics can be obtained, and an extremely high speed CMOS is obtained.
I realized the FET.

<Embodiment 6> A sixth embodiment of the present invention is shown in FIG.
3 will be used for the explanation. The present embodiment is an example in which the manufacturing process in Embodiment 5 is partially changed to form a CMOSFET. In this example, the position of the punch-through stopper layer 108 in Example 5 is set below the gate electrode region,
Further, the gate oxide film 114 is replaced with a tantalum oxide film 119 having a high dielectric constant of about 25. As the high dielectric gate insulating film, it is possible to use a ferroelectric film such as lead zirconate titanate other than the tantalum oxide film. Also in this embodiment, the same effect as that of the above-mentioned Embodiment 5 was obtained, and a high-speed CMOSFET could be realized.

<Embodiment 7> A seventh embodiment of the present invention is shown in FIG.
4 will be described. In this embodiment, the position of the punch-through stopper layer 108 in the fifth embodiment is set below the gate region, and before the gate oxide film 114 is formed, only the exposed silicon film 106 has a film thickness of 20 nm
The single crystal silicon film 120 containing no impurity ions is selectively grown, and then the gate oxide film 114 is formed. By doing so, the low-concentration channel layer 120 is formed.
Was formed, and the drain saturation current could be effectively increased. Also in this embodiment, the same effect as that of the above-mentioned Embodiment 5 was obtained, and a high-speed CMOSFET could be realized.

<Embodiment 8> Another embodiment in which a MOSFET is formed on a silicon substrate will be described with reference to FIGS. First, as shown in FIG. 25, the silicon substrate 131
An element isolation trench 133 filled with an element isolation silicon oxide film 132 and an insulating film was formed in a predetermined portion of the above, and a first conductivity type well diffusion layer 134 was formed.

Next, a silicon nitride film having a film thickness of 200 nm is formed, and the silicon nitride film 135 is dry-etched.
After being processed into a desired shape, a single crystal silicon film 136 having a film thickness of 100 nm was selectively grown only on the exposed silicon substrate 131 by the LPCVD method. At this time, as shown in FIG. 26, it is called a facet surface,
A crystal orientation different from that of the surface of the silicon substrate 131 and forming a certain angle with the surface of the silicon substrate 131 was formed in the single crystal silicon film 136 around the silicon nitride film 135. As a result, the side surface of the single crystal silicon film 136 in the vicinity of the silicon nitride film 135 is formed on the silicon substrate 13
An angle of 60 degrees or less was formed with respect to one surface.

By implanting the second conductivity type impurity ions near the surface of the single crystal silicon film 136 and controlling the implantation acceleration energy at that time, the diffusion depth is 10 nm and the surface impurity concentration is 1 ×. 10 ²⁰ / cm ³
A shallow first-conductivity-type impurity diffusion layer 137 is formed on the front and back. Then, a 200 nm-thickness silicon oxide film was formed and anisotropic dry etching was performed to leave the silicon oxide film 138 on the sidewall of the silicon nitride film 135 as shown in FIG.

After the exposed surface of the silicon film 136 is oxidized to form a silicon oxide film with a film thickness of about 50 nm,
By implanting the first conductivity type impurity ions into the single crystal silicon film 136 and controlling the implantation acceleration energy, the diffusion depth is about 80 nm and the peak impurity concentration is 1 × 10 ²⁰ / cm ³ or more. A high concentration first conductivity type impurity diffusion layer 139 was formed. After performing a short-time annealing such as a lamp annealing method to activate the implanted first conductivity type impurity ions, the silicon nitride film 135 is formed.
Is removed, the exposed surface of the silicon substrate 131 is oxidized to form a thin gate oxide film 140 having a film thickness of 10 nm or less, and a metal film of tungsten or the like is formed and selective etching is performed by a known means. Then, a gate electrode 141 made of the above metal is formed, and the MOSFE shown in FIG.
Formed T.

Finally, necessary wiring such as internal wiring and power supply wiring was performed to complete a semiconductor integrated circuit using this MOSFET. Also in the present embodiment, the first conductivity type impurity diffusion layer 137 serving as the source and drain diffusion layers is close to the gate electrode 141 through the gate oxide film 140, and the single crystal silicon serving as the source and drain electrodes is formed. Since the side surface of the film 136 has a structure inclined at an angle of 60 degrees or less with respect to the surface of the silicon substrate 131, the drain saturation current can be increased and the gate parasitic capacitance can be reduced as described above. It was

Furthermore, the first conductivity type impurity diffusion layer 139.
However, since it is distant from the second conductivity type well diffusion layer 134, the parasitic junction capacitance is reduced and a high-speed MOSFET is realized.

<Embodiment 9> A ninth embodiment of the present invention will be described.
This will be described with reference to FIG. 29, which is a computer system configuration diagram.
This embodiment is a processor 500 that processes instructions and operations.
Is an example in which a high-speed semiconductor integrated circuit composed of the semiconductor devices obtained in the above-described first to eighth embodiments is applied to a high-speed large-scale computer system in which a plurality of them are connected in parallel. In this embodiment, since the high-speed semiconductor integrated circuit used is highly integrated, the processor 500 for processing instructions and operations, the system controller 501 and the main memory 50.
2 and the like could be configured by a silicon semiconductor chip having one side of about 10 to 30 mm. A data communication interface 503 including a processor 500 that processes these commands and operations, a system controller 501, and a compound semiconductor integrated circuit.
Were mounted on the same ceramic substrate 506. Further, the data communication interface 503 and the data communication control device 50
4 was mounted on the same ceramic substrate 507.

The ceramic substrate on which these ceramic substrates 506 and 507 and the main memory device 502 are mounted is mounted on a substrate having a side of about 50 cm or less, and a central processing unit 508 of a large-scale computer is formed. Data communication in the central processing unit 508, data communication between a plurality of central processing units, or data communication between the data communication interface 503 and the board 509 on which the input / output processor 505 is mounted is indicated by double-headed arrow lines in FIG. This is done via the optical fiber 510 shown.

In this computer, a processor 500 for processing instructions and operations, a silicon semiconductor integrated circuit such as a system controller 501 and a main memory 502 operate in parallel at high speed, and data communication is performed optically. Since it was performed on the medium, the number of instruction processings per second could be significantly increased.

<Embodiment 10> A tenth embodiment of the present invention will be described with reference to FIG. 30 showing the configuration of an optical transmission system. The present embodiment is an example in which the semiconductor device obtained in any of the first to eighth embodiments is applied to both transmission systems of an optical transmission module 613 that transmits data at an ultra-high speed and an optical reception module 614 that receives the data. .

In this embodiment, the transmission side electric signal 610 is generated by the semiconductor device manufactured in the above-mentioned first to eighth embodiments.
An optical transmission module 613 including a multiplex conversion digital circuit 601 for processing the signal, a semiconductor laser driving analog circuit 602 for driving the semiconductor laser 603, and
These are analog circuits and digital circuits of a preamplifier 605, an automatic gain control amplifier 606, a clock extraction circuit 607, and a discrimination circuit 608, which amplifies a reception side electric signal 612 obtained by converting a transmitted optical signal 611 by a photodiode 604. The optical receiving module 614 including the separation conversion circuit 609 and the like is configured.

Since the semiconductor devices obtained in the above Examples 1 to 8 can operate at an extremely high speed, 1
A large-capacity signal of 0 Gbit could be transmitted and received at an extremely high speed.

<Embodiment 11> A fourth embodiment of the present invention will be described with reference to FIG. This embodiment is the same as the above-described first to eighth embodiments.
FIG. 31 shows an example in which a signal transmission processing device is configured by a semiconductor device formed in any one of them, and particularly relates to an asynchronous transmission system signal transmission processing device (called an ATM switch), and the configuration is shown in FIG.

As shown in FIG. 31, an information signal transmitted serially at high speed by an optical fiber is converted into an electrical signal (O / E conversion) and parallelized (S / P conversion). It was introduced into an integrated circuit (BFMLSI) composed of the MOSFET obtained in any of Examples 1 to 8 of the present invention. The electrical signal subjected to the addressing processing by the integrated circuit is serialized (P / S conversion) and converted into an optical signal (E / O conversion), and is output through the optical fiber. The BFMLSI is composed of a multiplexer (MUX), a buffer memory (BEM) and a separator (DMUX).

The BFM LSI is controlled by a memory control LSI and an LSI having an empty address distribution control function (empty address FIFO memory LSI). The signal transmission processing device is a device having a function of a switch for transmitting an ultra-high speed transmission signal sent to a desired address at an ultra high speed regardless of an address to be transmitted. Since the operation speed of BFMLSI is significantly slower than the transmission speed of the input optical signal, the input signal cannot be directly switched, and the input signal is temporarily stored,
A method is used in which the stored signal is switched, converted into an ultrahigh-speed optical signal, and transmitted to a desired address.

If the operating speed of the BFMLSI is slow, a large storage capacity is required. In the ATM switch of this embodiment, since the BFMLSI is composed of the MOSFET formed in any one of the above-mentioned first to eighth embodiments, the operating speed is three times as high as that of the conventional BFMLSI, and it is inexpensive. , It is possible to reduce the storage capacity of BFMLSI to about 1/3 of the conventional one. As a result, the manufacturing cost of the TM exchanger could be reduced.

[0064]

According to the present invention, as described above,
The leakage current between the source and the drain is reduced, the drain saturation current and the breakdown voltage between the source and the drain are improved, and the parasitic capacitance of the gate, the source and the drain, and the electrode parasitic resistance are reduced. Therefore, the semiconductor integrated circuit using the semiconductor device according to the present invention is remarkably speeded up, and the speeding up of various systems configured using this semiconductor device can be easily realized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of the present invention,

FIG. 2 is a sectional view showing a second embodiment of the present invention,

FIG. 3 is a plan view showing Embodiment 1 of the present invention,

FIG. 4 is a sectional view showing a conventional technique,

FIG. 5 is a characteristic diagram showing the effect of the present invention,

FIG. 6 is a process chart for explaining the first embodiment of the present invention,

FIG. 7 is a process chart for explaining the first embodiment of the present invention,

FIG. 8 is a process drawing for explaining the first embodiment of the present invention,

FIG. 9 is a process drawing for explaining the first embodiment of the present invention,

FIG. 10 is a process drawing for explaining the first embodiment of the present invention,

FIG. 11 is a process drawing for explaining the first embodiment of the present invention,

FIG. 12 is a process drawing for explaining the third embodiment of the present invention,

FIG. 13 is a process drawing for explaining the third embodiment of the present invention,

FIG. 14 is a process drawing for explaining the third embodiment of the present invention,

FIG. 15 is a process drawing for explaining the third embodiment of the present invention,

FIG. 16 is a process drawing for explaining the third embodiment of the present invention,

FIG. 17 is a cross-sectional view showing Embodiment 4 of the present invention,

FIG. 18 is a process drawing for explaining the fifth embodiment of the present invention,

FIG. 19 is a process chart for explaining the fifth embodiment of the present invention,

FIG. 20 is a process drawing for explaining the fifth embodiment of the present invention,

FIG. 21 is a process drawing for explaining the fifth embodiment of the present invention,

FIG. 22 is a process drawing for explaining the fifth embodiment of the present invention,

FIG. 23 is a sectional view showing Embodiment 6 of the present invention,

FIG. 24 is a sectional view showing Embodiment 7 of the present invention,

FIG. 25 is a process drawing for explaining the eighth embodiment of the present invention,

FIG. 26 is a process drawing for explaining the eighth embodiment of the present invention,

FIG. 27 is a process drawing for explaining the eighth embodiment of the present invention,

FIG. 28 is a process drawing for explaining the eighth embodiment of the present invention,

FIG. 29 is a computer system configuration diagram for explaining the ninth embodiment of the present invention;

FIG. 30 is a block diagram of an optical transmission system for explaining the tenth embodiment of the present invention;

FIG. 31 is a configuration diagram of a signal transmission processing device for explaining an eleventh embodiment of the present invention,

FIG. 32 is a curve diagram showing the effect of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Silicon oxide film, 3 ... Thin film silicon film, 4 ... Silicon nitride film, 5 ... Silicon oxide film, 6 ... Polycrystalline silicon film, 7 ... First conductivity type impurity diffusion layer, 8 ... High concentration Single crystal silicon growth film, 9 ...
Silicon oxide film, 10 ... Punch through stopper layer, 1
1 ... Gate oxide film, 12 ... First conductivity type impurity diffusion layer,
13 ... Metal gate electrode, 14 ... Metal source electrode,
15 ... Metal gate electrode, 16 ... Metal drain electrode,
21 ... Silicon substrate, 22 ... Silicon oxide film 23 ... Silicon film, 24 ... Gate oxide film, 25 ... Polycrystalline silicon gate electrode, 26 ... Silicon nitride film, 27 ... Silicon oxide film, 28 ... Punch through stopper layer, 30
High concentration single crystal silicon growth film, 31 ... Silicon oxide film, 32 ... First conductivity type impurity diffusion layer, 33 ... First conductivity type impurity diffusion layer, 34 ... Metal source electrode, 35 ... Metal gate electrode, 36 ... Metal Drain electrode, 40 ... Single crystal silicon growth film, 41 ... High concentration first conductivity type single crystal silicon growth film, 42 ... First conductivity type impurity diffusion layer,
43 ... Gate oxide film, 44 ... Metal gate electrode, 50
... Characteristics of conventional MOSFET, 51 ... MOS of the present invention
FET characteristics, 52 ... Conventional MOSFET gate parasitic capacitance, 53 ... MOSFET MOSFET gate parasitic capacitance, 70 ... Silicon substrate, 71 ... Gate oxide film, 7
2 ... Polycrystalline silicon gate electrode, 73 ... Source diffusion layer, 74 ... Drain diffusion layer 75 ... Silicon oxide film,
76 ... Stacked source electrode, 77 ... Stacked drain electrode, 80 ... Silicon substrate, 81 ... Gate oxide film,
82 ... Polycrystalline silicon gate electrode, 83 ... Silicon oxide film, 84 ... Stacked source electrode, 85 ... Stacked drain electrode, 86 ... Source diffusion layer, 87 ... Drain diffusion layer, 101 ... Silicon substrate, 102 ... Element isolation silicon oxide film , 103 ... Element isolation groove, 104 ...
p-type well diffusion layer, 105 ... n-type well diffusion layer, 1
06 ... Silicon growth film, 107 ... Silicon nitride film,
108 ... P-type punch through stopper layer, 109 ... N-type punch through stopper layer, 110 ... High concentration n-type single crystal silicon growth film, 111 ... High concentration p-type single crystal silicon growth film, 112 ... Silicon oxide film, 113 ... Silicon oxide film, 114 ... Gate oxide film, 115 ... N-type impurity diffusion layer, 116 ... P-type impurity diffusion layer, 117 ... Metal gate electrode, 119 ... Tantalum oxide film 120 ... Single crystal silicon growth film, 131 ... Silicon substrate, 132
... element isolation silicon oxide film, 133 ... element isolation trench,
134 ... Second conductivity type well diffusion layer, 135 ... Silicon nitride film, 136 ... Single crystal silicon growth film, 137 ...
First conductivity type impurity diffusion layer, 138 ... Silicon oxide film,
139 ... First conductivity type impurity diffusion layer, 140 ... Gate oxide film, 141 ... Metal gate electrode, 500 ... Processor, 501 ... System control device, 502 ... Main memory device, 503 ... Data communication interface, 504 ...
Data communication control device, 505 ... Input / output processor,
506 ... Ceramic substrate, 507 ... Ceramic substrate,
Reference numeral 508 ... Central processing unit, 509 ... Input / output processor mounting board, 510 ... Optical fiber, 601 ... Multiplex conversion digital circuit, 602 ... Semiconductor laser driving analog circuit, 603 ... Semiconductor laser, 604 ... Photodiode, 605 ... Preamplifier, 606 ... Automatic gain control amplifier, 607 ... Clock extraction circuit, 608 ... Discrimination circuit, 609 ... Separation conversion digital circuit, 610 ... Transmission side electric signal, 611 ... Transmitted optical signal, 612 ...
Receiving side electric signal, 613 ... Optical transmission module, 614
… Optical receiver module.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shun Uchino 1-280, Higashi Koikeku, Kokubunji, Tokyo, Hitachi, Central Research Laboratory (72) Inventor, Kazuhiro Onishi 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Yukihiro Kiyota 1-280 Higashi Koikekubo, Kokubunji, Tokyo Hitachi Central Research Laboratory (72) Inventor Hiromi Shimamoto 3681 Hayano, Mobara, Chiba Hitachi Device Engineering Co., Ltd.

Claims (18)

[Claims] 1. A drain diffusion layer having a second conductivity type opposite to the first conductivity type, which is provided in a surface region of a semiconductor substrate having the first conductivity type so as to face each other with a predetermined distance therebetween, and A source diffusion layer, a gate insulating film formed on the surface of the semiconductor substrate between the drain diffusion layer and the source diffusion layer, a gate electrode formed on the gate insulating film, the drain diffusion layer and the source The drain electrode and the source electrode, which are respectively formed along the surface of the diffusion layer and are formed of the low-resistance semiconductor film having the second conductivity type, the portion of the drain electrode and the source electrode that is closest to the gate electrode, and At least isolation insulating films respectively interposed between the gate electrodes are provided, and the thickness of the isolation insulating film is equal to the thickness of the gate insulating film or the drain expansion film. Between the end of the drain electrode and the source electrode on the side of the gate electrode and the surface of the semiconductor substrate, which is smaller than the diffusion depth of the portion of the layer and the source diffusion layer closest to the gate electrode. A semiconductor device having an angle smaller than 90 degrees. 2. The semiconductor device according to claim 1, wherein the isolation insulating film is a portion of the gate insulating film extending on a side portion of the gate electrode. 3. The semiconductor device according to claim 1, wherein a film thickness of an upper portion of the isolation insulating film is larger than a film thickness of a lower portion thereof. 4. The isolation insulating film is selectively formed on a side portion of the gate electrode.
The semiconductor device according to. 5. The semiconductor device according to claim 4, wherein the source diffusion layer and the drain diffusion layer extend below the isolation insulating film. 6. The semiconductor device according to claim 1, wherein each of the drain electrode and the source electrode is made of single crystal silicon. 7. The semiconductor device according to claim 5, wherein a metal drain electrode and a metal source electrode are formed on the drain electrode and the source electrode, respectively. 8. An insulating film having an upper film thickness larger than a lower film thickness interposed between the drain electrode and the source electrode and the gate electrode.
8. The semiconductor device according to any one of 2, 4, 5, 6 and 7. 9. Under the drain diffusion layer and the source diffusion layer, the drain diffusion layer and the source diffusion layer are thicker than the drain diffusion layer and the source diffusion layer, and the distance from the end of the gate electrode is smaller than that of the gate electrode and the drain diffusion layer. 9. A second drain diffusion layer and a second source diffusion layer having the second conductivity type, which are respectively larger than the distance between the source diffusion layer and the source diffusion layer, are formed. The semiconductor device according to 1. 10. A channel stopper layer having the first conductivity type is formed in the semiconductor substrate between the second drain diffusion layer and the second source diffusion layer. Item 9. The semiconductor device according to item 9. 11. The first semiconductor substrate is a single crystal silicon film formed on an insulating film.
11. The semiconductor device according to any one of items 1 to 10. 12. The semiconductor device according to claim 11, wherein bottom portions of the source diffusion layer and the drain diffusion layer are in contact with the insulating film. 13. The area of the upper surface of the gate electrode is larger than the area of the bottom surface, and the source diffusion layer and the drain diffusion layer extend below the upper surface of the gate electrode. To 33 and 8 to 12
The semiconductor device according to any one of 1. 14. A method of manufacturing a semiconductor device including the following steps. (1) a step of forming a silicon nitride film having a predetermined shape on the surface of a semiconductor substrate having the first conductivity type, (2) a step of forming a thin first silicon oxide film on the entire surface, (3) the above nitriding A step of selectively forming a polycrystalline silicon film on the side portion of the silicon film via the first silicon oxide film, (4) via the exposed portion of the first silicon oxide film, A step of doping a semiconductor substrate with a second conductivity type impurity opposite to the first conductivity type to form a second conductivity type impurity diffusion layer, (5) forming the polycrystalline silicon film and the first silicon oxide film After the removal, epitaxial growth is performed to include the high-concentration second conductivity type impurity, and the angle of the end portion on the silicon nitride film side with respect to the surface of the semiconductor substrate is 9 degrees.
A step of forming a single crystal silicon film having a temperature of 0 degrees or less, and (6) forming a second silicon oxide film having a predetermined shape to fill the concave portion between the silicon nitride film and the single crystal silicon film. And (7) after removing the silicon nitride film, performing an oxidation treatment to form a gate insulating film on the exposed portion of the semiconductor substrate, (8) performing a heat treatment, and then performing the single crystal silicon film. Diffusing the second conductivity type impurity contained in the surface of the semiconductor substrate to form a source diffusion layer and a drain diffusion layer, (9) forming a conductive film on the gate insulating film to form a gate electrode. Forming process. 15. In the step (7), after removing the silicon nitride film, prior to forming the gate insulating film, an impurity having the first conductivity type is doped into the exposed portion of the semiconductor substrate. 2. A step of forming a punch-through stopper layer is additionally provided.
4. The method for manufacturing a semiconductor device according to item 4. 16. The semiconductor substrate in the step (1) is an SOI substrate made of a single crystal silicon film formed on an insulating film.
5. The method for manufacturing a semiconductor device according to item 5. 17. The step (4) is omitted, and the step (8) is performed so that the end faces of the source diffusion layer and the drain diffusion layer reach the insulating film. Item 17. A method of manufacturing a semiconductor device according to item 16. 18. A method of manufacturing a semiconductor device including the following steps. (1) A step of oxidizing the surface of a semiconductor substrate having the first conductivity type to form a first silicon oxide film, (2) having a predetermined shape on a predetermined portion of the first silicon oxide film. A step of forming a laminated film of a low-resistance polycrystalline silicon film and a silicon nitride film, (3) After forming a second silicon oxide film on the entire surface, the exposed portion of the second silicon oxide film is interposed. A step of doping an impurity having the first conductivity type and forming a punch-through stopper in the semiconductor substrate; (4) Of the second silicon oxide film, it is formed on a side portion of the laminated film. Leaving the portion and removing the other portion, (5) the second surface is formed on the exposed surface of the semiconductor substrate.
A step of selectively forming a single crystal silicon film having a conductivity type by epitaxial growth, (6) after removing the silicon nitride film, heat treatment is performed to remove impurities having the second conductivity type from the single crystal silicon film. A step of forming a shallow diffusion layer by diffusing into the semiconductor substrate. (7) A step of forming a gate electrode, a source electrode and a drain electrode by removing a predetermined portion after forming a conductive film on the entire surface.