WO1996030946A1

WO1996030946A1 - Semiconductor device and its manufacture

Info

Publication number: WO1996030946A1
Application number: PCT/JP1995/000592
Authority: WO
Inventors: Akihiro Miyauchi; Takeo Shiba; Takashi Uchino; Yukihiro Kiyota; Toshio Ando; Osamu Kasahara; Yosuke Inoue; Takaya Suzuki
Original assignee: Hitachi, Ltd.
Priority date: 1995-03-29
Filing date: 1995-03-29
Publication date: 1996-10-03

Abstract

A MOSFET structure in which a selectively grown silicon film having small facets at the parts in contact with spacers made of an insulator beside a gate electrode and an element isolating insulating film is independent of the area ratio of the silicon substrate and the insulating film. Since the silicon in the source and drain regions is etched, crystal faces appear below the element isolating oxide and the insulating spacers. As a result, facets are hardly formed in the selectively grown silicon film below the oxide and spacers.

Description

Specification

Semiconductor device and manufacturing method thereof

The present invention relates to a structure, a manufacturing method, and a computer system, an optical transmission system, and a signal transmission processing device of an M0SFET in which a silicon film is stacked on source and drain regions, and a silicon film is stacked on the source and drain regions. In particular, it relates to M0SFETs with small facets of the silicon film deposited on the source and drain. Background art

Conventionally, with respect to the structure of an M0SFET in which a silicon film is selectively deposited on source and drain regions, as described in JP-A-55-3614, at least one of the source and drain regions is connected to a channel plane. It was placed on the same plane or above. In addition, a method for selectively depositing a silicon film on the source and drain regions is a method for selectively depositing an extremely flat silicon film with a small facet in a region surrounded by an insulating film, which is required in the M0SFET manufacturing process. As described in Japanese Patent Application Laid-Open No. 60-60716, this has been realized by making the exposed area of the silicon substrate surface larger than the exposed area of the insulating film.

In the above-mentioned prior art, in a structure in which at least one of the source and drain regions is arranged on a plane which is the same as or higher than the channel plane, the silicon film stacked on the source and drain regions is an insulating film for element isolation. Facets are likely to occur in the silicon film due to contact with the insulator spacer of the film gate from the beginning of growth. As a result, a high melting point metal film such as a titanium film or a tungsten film is deposited on the silicon film in the wiring process. When stacked, these metal films penetrate deeper into the portion where the facet has occurred on the semiconductor substrate side, causing a problem that a leak current is generated.

Among the above-mentioned conventional techniques, a method of selectively embedding a silicon film having a small facet in a region surrounded by an insulating film is as follows: the exposed area of the silicon substrate surface is made larger than the exposed area of the insulating film. Therefore, the circuit design when integrating transistors, resistors, and capacitors was limited.

An object of the present invention is to provide a facet at a portion where an insulator spacer next to a gate electrode contacts a selectively grown silicon film or a portion where an insulating film for element isolation contacts a selectively grown silicon film. It is an object of the present invention to provide a MOSFET structure and a manufacturing method capable of depositing a selective silicon film having a small thickness irrespective of a silicon substrate surface or an area ratio of an insulating film. Disclosure of the invention

In order to reduce the facet at the part where the insulator film next to the insulating film for element isolation and the gate and the selectively grown silicon film are small, the selective silicon film must be deposited on the silicon substrate surface. As shown in FIG. 1, the portion where the silicon substrate surface contacts the insulating film for element isolation and the portion where the silicon substrate surface contacts the insulating spacer are shown in FIG. This is achieved by forming a structure in which a part of the selective silicon film 111 can be cut under the insulator spacer 108.

The structure in which a part of the selective silicon film bites under the insulating film for element isolation or the insulator spacer is formed by heat-treating the silicon substrate in vacuum or a hydrogen atmosphere before depositing the selective silicon. it can.

In order to reduce the facet at the portion where the insulator spacer next to the insulating film gate for element isolation and the selectively grown silicon film are reduced, the following method is used. As shown in the figure, before depositing the selective silicon film, the etching region 201 lowering the silicon substrate surface of the source and drain regions to the silicon substrate side with respect to the insulating film for element isolation and the insulator spacer. This is achieved by providing a structure that provides

Note that the structure in which the silicon substrate surface in the source and drain regions is lowered to the silicon substrate side with respect to the insulating film for element isolation and the insulator spacer is that the silicon substrate is treated with hydrochloric acid gas or tri-metal before deposition of the selective silicon. It can be formed by etching with nitrogen fluoride gas or chlorine trifluoride gas. In addition, it can also be formed by wet etching using a mixed solution of hydrofluoric acid and nitric acid / hydrazine instead of gas phase etching using gas.

Before the selective silicon film is deposited on the source and drain regions, the source / drain regions come into contact with the oxide for element isolation, and the source / drain regions come into contact with the insulator spacer next to the gate electrode. A plurality of crystal planes appear in the region where the portion of the selective silicon film cuts into the portion. As a result, facets are less likely to be formed in the selective silicon film deposited in the biting region. Therefore, a selective silicon film with a small facet can be deposited regardless of the area ratio between the silicon surface and the insulating film.

By etching the silicon in the source and drain regions before depositing the selective silicon film in the source and drain regions, multiple crystal planes are formed below the oxide and insulator spacers for element isolation. appear. As a result, it is difficult for the facet to be formed in the oxide for element isolation or in the selective silicon film deposited below the insulator spacer. Therefore, a selective silicon film with a small facet can be deposited regardless of the area ratio between the silicon surface and the insulating film. BRIEF DESCRIPTION OF THE FIGURES

Figure 1 shows where the source and drain regions and the oxide for element isolation are in contact. WO 96/30946 PCT / JP9S / D0S92 and a cross-sectional view of a main part of a MOSFET in which a part of a selective silicon film has cut into a portion where a source / drain region and an insulator spacer next to a gate electrode are in contact. From FIG. 13 to FIG. 13 are cross-sectional views of essential parts for explaining the first embodiment, FIGS. 14 to 25 are cross-sectional views of main parts for explaining the second embodiment, and FIG. FIG. 27 is a computer system configuration diagram for explaining Example 3, FIG. 27 is an optical transmission system configuration diagram for explaining Embodiment 4, and FIG. 28 is a signal transmission processing device configuration for explaining Embodiment 5 FIG. BEST MODE FOR CARRYING OUT THE INVENTION

[Example 1]

Hereinafter, Example 1 of the present invention will be described. FIG. 2 to FIG. 13 are cross-sectional views of essential parts for describing the present embodiment. An oxide film 101 for element isolation is formed on one surface of the substrate 100, which is a part of the silicon wafer having a P-type crystal orientation (100) plane, by the well-known LOCOS method. Formed. The thickness of the oxide film is 350 nm. Through the above process, the structure shown in Fig. 2 was completed.

Next, an oxide film 102 having a thickness of 5 nm is formed by wet oxidation, and a polycrystalline silicon film 103 having a thickness of 200 nm is formed on the oxide film 102 by decompression chemical vapor deposition. Was formed. Through the above steps, the structure shown in Fig. 3 was completed.

Next, a polycrystalline silicon film 103 was added by a known photolithography technique. The width of the polycrystalline silicon film 103 is 0.2 μπι. Then, phosphorus was implanted by an ion implantation method to form an η-type impurity region 106 in the source region 104 and the drain region 105. The conditions for ion implantation are an acceleration voltage of 25 keV and a dose of 5 × 10 ¹³ / cm ² . Through the above process, the structure shown in Fig. 4 was completed.

Next, an oxide film 107 was formed by decompression chemical vapor deposition. Oxide film 1 0 7 Has a thickness of 300 nm. Through the above steps, the structure shown in Fig. 5 was completed.

Next, the oxide film 107 was etched by anisotropic etching to form an insulator spacer 108. Through the above steps, the structure shown in Fig. 6 was completed.

Next, arsenic was implanted into the source region 104 and the drain region 105 by ion implantation to form an n-type impurity region 109. The ion implantation conditions were an acceleration voltage of 40 keV and a dose of 2 × 10 ^le Zcm ² _{c. The} above process completed the structure shown in FIG.

Next, the oxide film 102 on the source region 104 and the drain region 105 was removed by immersion in a hydrofluoric acid solution. Through the above process, the structure shown in Fig. 8 was completed.

Next, by heat treatment at 900 C for 2 minutes in a low pressure chemical vapor deposition apparatus, the source region 104 and the drain region 105 become under-exposed at the portion where they contact the oxide film 101 and the oxide film 108. A cut region 110 was formed. The pressure during the heat treatment is 0.01 Pascal. Through the above steps, the structure shown in Fig. 9 was completed.

Next, the silicon film 111 was selectively formed on the source region 104, the drain region 105, and the polycrystalline silicon film 103 in the same reduced pressure chemical vapor deposition apparatus. The conditions for forming the silicon film 111 are as follows: growth temperature 750 ° C, growth pressure 100 Pascal, dichlorosilane gas flow 10 OccZ, hydrogen chloride gas flow l OccZ, hydrogen gas flow 1 It is Ritano minutes. The thickness of the silicon film 111 is 100 nm. Through the above steps, the structure shown in FIG. 10 was completed.

Next, a titanium film with a thickness of 1 0 0 nm is deposited on the entire surface by sputtering, and heat-treated in a nitrogen atmosphere 7 0 0 ^e C, 1 min. Then immerse in hydrogen peroxide solution As a result, the titanium film on the oxide film 101 and the insulator spacer 108 is removed, and the titanium silicide film 112 is replaced with the source region 104, the drain region 105 and the polycrystalline silicon film 1. 0 3 formed on. The sheet resistance of the titanium silicide film 112 was 25 Ω. Through the above steps, the structure shown in Fig. 11 was completed.

Next, a 1 μm-thick oxide film was deposited on the entire surface by decompression chemical growth,

An S 0 G (Spin On Glass) film was deposited, and an oxide film 113 having a flat surface was formed by a well-known etch-back method. Through the above steps, the structure shown in Fig. 12 was completed.

Next, a contact hole is formed in the upper part of the titanium silicide film 112 by photolithography technology, a tungsten film is buried, and the source electrode 114, the gate electrode 115, and the gate electrode 115 are formed by photolithography technology. Drain electrodes 1 16 were formed. Through the above steps, the nMOSFET shown in Fig. 13 was completed.

In the above nMOSFET fabrication process, a pMOSFET can be fabricated by changing the conductivity type of the substrate and the elements to be implanted. CM0SFET can be fabricated by combining nMOSFET and pMOSFET. Furthermore, although a titanium film was used in the present invention, similar results were obtained by using tungsten, cobalt, molybdenum, tantalum, nickel, and platinum. In this embodiment, a silicon single crystal wafer is used as the substrate 100, but an SII wafer may be used.

The nMOSFET described in the present invention has a structure in which the silicon film 111 is stacked on the source region 104 and the drain region 105, whereby the sheet resistance of the titanium silicide film is reduced, and the gate width is 0.2 μππι. The following worked properly. As a result of evaluating the electrical characteristics of the fabricated nMOSFET, the mutual inductance was 350 milli-Siemens / πιηι at a power supply voltage of 2 V, and the CM0SFET The delay time of the barta was 4 Os.

In the above nMOSFET fabrication process, a hydrogen gas was introduced into the decompression vapor phase growth apparatus at the time of forming the undercut region 110, and the undercut region 110 was formed by heat treatment in a hydrogen atmosphere. You may.

[Example 2]

Hereinafter, a second embodiment of the present invention will be described. FIG. 14 to FIG. 25 are cross-sectional views of essential parts for explaining the present embodiment. On one surface of a substrate 100 which is a part of a silicon wafer having a P-type crystal orientation (100) plane, an oxide film 101 for element isolation is formed on a peripheral portion of an element formation region by a well-known LOCOS method. Was formed. The thickness of the oxide film is 350 nm. Through the above steps, the structure shown in Fig. 14 was completed.

Next, an oxide film 102 having a thickness of 5 nm is formed by wet oxidation, and a polycrystalline silicon film 103 having a thickness of 200 nm is formed on the oxide film 102 by decompression chemical vapor deposition. Was formed. Through the above steps, the structure shown in FIG. 15 was completed. Next, a polycrystalline silicon film 103 was added by a well-known photolithography technique. The width of the polycrystalline silicon film 103 is 0.2 μπι. Then, phosphorus was implanted by an ion implantation method to form an η-type impurity region 106 in the source region 104 and the drain region 105. Ion implantation conditions are an acceleration voltage 2 5 ke V, a dose of ^{^{5 X 1 0 '3 cm 2}} . Through the above steps, the structure shown in Fig. 16 was completed.

Next, an oxide film 107 was formed by low pressure chemical vapor deposition. The thickness of the oxide film 107 is 300 nm. Through the above steps, the structure shown in Fig. 1 was completed.

Next, the oxide film 107 was etched by anisotropic etching to form an insulator spacer 108. Through the above steps, the structure described in Fig. 18 was completed. Next, arsenic was implanted into the source region 104 and the drain region 105 by ion implantation to form an n-type impurity region 109. Conditions of the ion hitting Chikomi acceleration voltage 4 0 ke V, a dose of ^{^{2 X 1 0 '6 Zcm 2}} . Through the above steps, the structure shown in FIG. 19 was completed.

Next, the oxide film 102 on the source region 104 and the drain region 105 was removed by immersion in a hydrofluoric acid solution. In the above steps, the structure shown in FIG. 20 was completed.

Next, the silicon substrate 100 and the polycrystalline silicon film 103 exposed to the source region 104 and the drain region 105 are etched by hydrogen chloride gas in a decompression chemical vapor deposition apparatus. An etched area 201 was formed. The etching conditions were a processing temperature of 900 ° C, a processing time of 2 minutes, a hydrogen chloride gas flow rate of 100 OccZ, a hydrogen gas flow rate of 1 litterano, and a processing pressure of 100 pass pressure. Through the above steps, the structure shown in FIG. 21 was completed.

Next, a silicon film 111 was selectively formed on the source region 104, the drain region 105, and the polycrystalline silicon film 103 in the same low pressure chemical vapor deposition apparatus. The conditions for forming the silicon film 111 are as follows: growth temperature 750 ° C, growth pressure 100 Pascal, dichlorosilane gas flow 10 OccZ, hydrogen chloride gas flow 1 OccZ, hydrogen gas flow 1 Litter minutes. The thickness of the silicon film 111 is 100 nm. Through the above steps, the structure shown in Fig. 22 was completed.

Next, a titanium film was deposited on the entire surface to a thickness of 100 O nm by a sputtering method, and was heat-treated at 700 ° C. for 1 minute in a nitrogen atmosphere. Then, the titanium film on the oxide film 101 and the insulator spacer 108 was removed by immersion in a hydrogen peroxide solution, and the titanium silicide film 112 was replaced with the source region 104 and the drain region 100. 5 and the polycrystalline silicon film 103. The sheet resistance of the titanium silicide film 112 was 25 Ω / port. Structure shown in Fig. 23 in the above process Was completed.

Next, an oxide film with a thickness of 1 μm was deposited on the entire surface by decompression chemical growth, an S0G (Spin On Glass) film was deposited, and the surface was flattened by a well-known etch-back method. An oxide film 113 was formed. Through the above steps, the structure shown in Fig. 24 was completed.

Next, a contact hole is formed in the upper part of the titanium silicide film 112 by photolithography technology, a tungsten film is buried, and the source electrode 114, the gate electrode 115, and the drain electrode are formed by photolithography technology. A pole 1 1 6 was formed. Through the above steps, the nMOSFET shown in Fig. 25 was completed.

In the above nMOSFET fabrication process, a pMOSFET can be fabricated by changing the conductivity type of the substrate and the elements to be implanted. Also, nMOSFET and pMOSFET can be made simultaneously to make CM0SFET. Furthermore, although a titanium film was used in the present invention, similar results were obtained when tungsten, cobalt, molybdenum, tantalum, niggel, and platinum were used. Further, in this embodiment, a silicon single crystal wafer is used as the substrate 100, but an SOI wafer may be used.

The nMOSFET described in the present invention has a structure in which the silicon film 111 is stacked on the source region 104 and the drain region 105, so that the sheet resistance of the titanium silicide film can be reduced and the gate width 0.2. It operated normally even under μπι. As a result of evaluating the electrical characteristics of the fabricated nMOSFET, the mutual inductance was 350 millimeters Zmm at a supply voltage of 2 V, and the delay time of the CM0SFET inverter at no load was 4 Ops.

In the above nMOSFET manufacturing process, the etching region 201 may be formed by introducing nitrogen trifluoride gas into the decompression vapor phase growth apparatus when the etching region 201 is formed. Similarly, the etched area 201 The etching region 201 may be formed by introducing chlorine trifluoride gas into the depressurized vapor phase epitaxy apparatus at the time of forming the etching.

Note that in the above nMOSFET manufacturing process, the etching region 201 may be formed by using a mixed solution of hydrogen fluoride water and nitric acid when the etching region 201 is formed. Similarly, when the etching region 201 is formed, the etching region 201 may be formed with a hydrazine solution.

[Embodiment 3]

Next, a third embodiment of the present invention will be described with reference to a computer system configuration diagram in FIG. In the third embodiment, a high-speed silicon semiconductor integrated circuit constituted by the semiconductor device according to any one of the first and second embodiments is replaced by a high-speed processor 500 in which a plurality of processors 500 for processing instructions and operations are connected in parallel. This is an example applied to a large computer system. In the third embodiment, since the high-speed silicon semiconductor integrated circuit used has a high degree of integration, a processor 500 for processing instructions and arithmetic operations, a system control device 501, a main storage device 502, and the like are provided. It could be composed of about 10 to 3 silicon semiconductor chips on one side. A processor 503 for processing these instructions and operations, a system controller 501, and a data communication interface 503 composed of a compound semiconductor integrated circuit were mounted on the same ceramic substrate 506. In addition, the data communication interface 503 and the data communication control device 504 were mounted on the same ceramic substrate 507. These ceramic substrates 506 and 507, and the ceramic substrate on which the main memory device 502 is mounted, are mounted on a substrate with a side of about 5 Ocm or less, and the center of a large computer. A processing unit 508 was formed. The data communication within the central processing unit 508, the data communication between a plurality of central processing units, or the data communication interface 503 and the board 509 on which the input / output processor 505 is mounted. The data communication was performed via the optical fiber 510 indicated by the double-headed arrow lines in the figure. In this calculator, Silicon semiconductor integrated circuits, such as a processor 503 that processes commands and calculations, a system controller 501, and a main memory 502, operate at high speed in parallel, and use optical media to communicate data. As a result, the number of instructions processed per second was greatly increased.

[Example 4]

Next, a fourth embodiment will be described with reference to FIG. FIG. 27 is an optical transmission system configuration diagram showing the fourth embodiment. In the fourth embodiment, one of the semiconductor devices according to the first and second embodiments is applied to both the optical transmission module 613 for transmitting data at an extremely high speed and the optical receiving module 614 for receiving the data. This is an example. In the fourth embodiment, the semiconductor device manufactured according to any one of the first and second embodiments is used to drive the multiplex conversion digital circuit 6001 for processing the transmission-side electric signal 610 and the semiconductor laser 603. An optical transmitter module 613 comprising a semiconductor laser-driven analog circuit 602 of the present invention, and a receiving-side electrical signal 612 obtained by converting the transmitted optical signal 611 by a photodiode 604. It consists of a preamplifier 605 to amplify, an automatic gain control amplifier 606, a clock extraction circuit 607, an analog circuit of an identification circuit 608, and a separation conversion circuit 609 as a digital circuit. The optical receiving module 6 1 4 was configured. Since the semiconductor device manufactured according to the above-described embodiment can operate at an ultra-high speed, a large-capacity signal of 10 Gbits per second can be transmitted and received at an ultra-high speed.

[Example 5]

Next, a fifth embodiment will be described with reference to FIG. The fifth embodiment relates to a signal transmission processing device 700 constituted by a semiconductor device manufactured based on any one of the first and second embodiments, and particularly relates to an asynchronous transmission system (referred to as an ATM switch). Signal transmission processing device 700 relating to In Fig. 28, the input optical signal transmitted in series at a very high speed by the optical fiber 70 1 Reference numeral 700 denotes an M0SFET manufactured based on any of the first and second embodiments of the present invention via a converter 703 for converting (0 / E conversion) and parallelizing (SZP conversion) an electric signal. Introduced into the integrated circuit 704 composed of The electric signal subjected to address processing in the integrated circuit 704 is serialized (P / S conversion) and converted to an optical signal (E / 0 conversion) by the conversion device 705, and is output from the optical fiber 706. The integrated circuit 704 includes a multiplexer 707, a buffer memory 708, and a separator 709. The integrated circuit 704 is controlled by a memory control LSI 710 and an empty address distribution control LSI 711. The signal transmission processing device 700 is a device having a function of a switch for transmitting an input optical signal 720 transmitted irrespective of an address to be transmitted to a desired address at a very high speed. Since the operating speed of the integrated circuit 704 is significantly slower than the transmission speed of the input optical signal, the input signal cannot be directly switched, the input optical signal 720 is temporarily stored, and the stored signal is switched. A method is used in which the signal is converted into a high-speed optical signal and transmitted to a desired address. If the operation speed of the integrated circuit 704 is low, a large storage capacity is required. In the ATM switch according to the present embodiment, the converging circuit 704 is constituted by the M0SFET manufactured according to any one of the first and second embodiments, so that it operates compared to the conventional integrated circuit 704. Since the speed is three times as fast and inexpensive, it has become possible to reduce the storage capacity of the integrated circuit 704 to about one third of that of the conventional one. As a result, the manufacturing cost of ATM switches could be reduced.

Before the selective silicon film is deposited on the silicon substrate surface, the parts where the silicon substrate surface contacts the insulating film for element isolation and the parts where the silicon substrate surface contacts the insulator spacer are shown in FIG. As shown in the figure, by forming a structure in which a part of the selected silicon film 111 is able to bite under the insulating film 101 for element isolation and the insulator spacer 108, a facet generated in the selected silicon film is formed. Can be made smaller. As a result, in the silicidation process of the selective silicon film, This has the effect of preventing the silicide film from penetrating deeply into the silicon substrate at the portion where the silicon film and the insulating film for element isolation or the insulator spacer are in contact, and has the effect of suppressing the leakage current.

Before the selective silicon deposition, the silicon substrate is heat-treated in a vacuum or in a hydrogen atmosphere to form a structure in which a part of the selective silicon film bites under the insulating film for element isolation or the insulator spacer. This step can be performed in an apparatus for forming a selective silicon film. As a result, there is an effect that the manufacturing process can be simplified.

Before depositing the selective silicon film, a structure is provided in which an etching region 201 for lowering the silicon substrate surface of the source and drain regions to the silicon substrate side is provided for the insulating film for element isolation and the insulator spacer. The facets generated in the selected silicon film can be reduced. As a result, in the silicidation process of the selective silicon film, it is possible to prevent the silicide film from penetrating deeply into the silicon substrate at a portion where the selective silicon film and the insulating film for element isolation or the insulator spacer are in contact with each other. This has the effect of suppressing leakage current.

The step of forming an etching region on the silicon substrate with a hydrochloric acid gas, a nitrogen trifluoride gas, or a chlorine trifluoride gas before the deposition of the selective silicon can be performed in a selective silicon film forming apparatus. As a result, there is an effect that the manufacturing process can be simplified. In addition, wet etching using a mixture of hydrofluoric acid and nitric acid / hydrazine, instead of gas phase etching using gas, has the effect of making the surface of the etching region flatter than gas phase etching. Industrial applicability

The present invention is directed to a selective silicon having a small facet at a portion where an insulator spacer next to a gate electrode contacts a selectively grown silicon film or at a portion where an insulating film for element isolation contacts a selectively grown silicon film. Put the film on the silicon substrate It provides a MOSFET structure and manufacturing method that can be deposited regardless of the area ratio of the insulating film. This is useful for circuit design when integrating transistors, resistors, and capacitors.

Claims

1. A convex second insulating film and a second insulating film are formed on the semiconductor substrate in a region where a transistor is formed, which is surrounded by a trench made of a first insulating material for element isolation. A first conductive film is stacked, and the stacked first conductive film and side walls or side walls of the second insulating film and a surface of the first conductive film are formed on the first conductive film.

In a structure in which the third insulating film is attached and the semiconductor film is deposited in a region surrounded by the first insulator and the third insulator, at least the first insulating film and the semiconductor A semiconductor device, wherein the semiconductor device further cuts into the semiconductor substrate side from the surface in contact with the substrate or cuts into the semiconductor substrate side from the surface in contact with the third insulating film and the semiconductor substrate.

2. A step of forming a trench made of a first insulator for element isolation on a region of the semiconductor substrate where a transistor is to be formed, a step of forming a second insulating film, and a step of forming the second insulating film. Forming a first conductive film on the film, forming the first conductive film on a convex by a known photolithography technique, and forming the first conductive film on the convex. Removing the second insulating film other than the region sandwiched between the film and the silicon substrate; forming an insulating film and forming the insulating film only on the side walls of the second insulating film and the side walls of the first conductive film; Forming a third insulator, depositing a semiconductor film on the substrate region where the semiconductor substrate is exposed, and not depositing the semiconductor film on the first insulator and the third insulator; In the selective growth step, at least the first or third insulator contacts the semiconductor substrate when the semiconductor film is formed. A method of manufacturing a semiconductor device, wherein a part of the semiconductor device is cut into the semiconductor substrate.

3. The semiconductor substrate according to claim 2, wherein the semiconductor substrate is selectively grown before the semiconductor film is selectively grown.

A semiconductor characterized in that by heating to 800 ° C. or more, a portion where the semiconductor substrate bites under the first insulator is formed at a portion where the semiconductor substrate and the first insulator are in contact with each other. Device manufacturing method.

4. The semiconductor substrate according to claim 2, wherein the semiconductor substrate is heated to 800 ° C. or more in a hydrogen atmosphere before selective growth of the semiconductor film, so that the semiconductor substrate is brought into contact with the first insulator. A method of manufacturing a semiconductor device, wherein a portion of a substrate is formed under the first insulator.

5. a step of forming a trench made of a first insulator for element isolation on a region of the semiconductor substrate where a transistor is to be formed, a step of forming a second insulating film, and a step of forming the second insulating film. Forming a first conductive film on the film, processing the first conductive film on a convex by a known photolithography technique, and forming the first conductive film on the convex. Removing the second insulating film other than the region sandwiched between the film and the silicon substrate; and forming an insulating film only on the side walls of the second insulating film and the side walls of the first conductive film. Forming a third insulator, depositing a semiconductor film on the substrate region where the semiconductor substrate is exposed, and not depositing the semiconductor film on the first insulator and the third insulator; In the selective growth step, the substrate region is etched before depositing the semiconductor film. Method of manufacturing location.

6. The semiconductor device according to claim 5, wherein the substrate region is etched with a silicon etching gas containing at least hydrogen chloride gas, nitrogen trifluoride gas, and chlorine trifluoride gas. Production method.

7. A method for manufacturing a semiconductor device according to claim 5, wherein, in the step of etching the substrate region, the substrate region is etched with hydrazine, at least a mixed solution of aqueous hydrogen fluoride and nitric acid.

8. A computer system using the semiconductor device described in claim 1.

9. An optical transmission system using the semiconductor device described in claim 1.

10. A signal transmission processing device using the semiconductor device described in claim 1.