TW200306002A - Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate - Google Patents

Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate Download PDF

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Publication number
TW200306002A
TW200306002A TW092105894A TW92105894A TW200306002A TW 200306002 A TW200306002 A TW 200306002A TW 092105894 A TW092105894 A TW 092105894A TW 92105894 A TW92105894 A TW 92105894A TW 200306002 A TW200306002 A TW 200306002A
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Taiwan
Prior art keywords
film
substrate
silicon
single crystal
thin film
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TW092105894A
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Chinese (zh)
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TWI235486B (en
Inventor
Yutaka Takafuji
Takashi Itoga
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Sharp Kk
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Priority claimed from JP2002086999A external-priority patent/JP2003282885A/en
Priority claimed from JP2002243927A external-priority patent/JP4772258B2/en
Priority claimed from JP2002280036A external-priority patent/JP2004119636A/en
Application filed by Sharp Kk filed Critical Sharp Kk
Publication of TW200306002A publication Critical patent/TW200306002A/en
Application granted granted Critical
Publication of TWI235486B publication Critical patent/TWI235486B/en

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    • H—ELECTRICITY
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
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Abstract

A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.

Description

200306002 ⑴ 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 發明領域 本發明係有關半導體裝置與其製造方法，特別係有關形 成包含數個MOS之積體電路之半導體裝置與其製造方法。200306002 玖 玖, description of the invention (the description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the drawings). FIELD OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a formation inclusion Semiconductor device of integrated circuit of MOS and manufacturing method thereof.

此外，本發明係有關將具有植入氫離子之植入層之單晶 石夕薄膜貼合於基板，以其氫離子植入層分割而作成之s〇I 基板，進一步係有關使用其之顯示裝置及s〇I基板之製造方 法。 此外，本發明係有關主動矩陣驅動液晶顯示裝置等上使 用之改善積體化週邊驅動電路及控制電路之裝置之電路性 能的半導體裝置及其製造方法。 先前技術 先前於玻璃基板上形成a-矽（非晶質矽）及卜矽（多晶矽）之 薄膜電晶體（Thin Film Transistor，以下猶 「將1 Π )，進行液晶 面板及有機EL面板等驅動而進行所謂的主動矩陣驅動。並 使用移動率高之高速動作之p-矽而進行週邊驅動器之積= 化。或是為了要求更高性能之影像處理器及時間控制哭^ 糸統的積體化而研究形成更焉性能之硬裝置。 、 夕晶矽因結晶性不完 w w門局部位準 及釔晶粒場附近之缺陷及間隙内存在局部位準導致夕 降低及S係數（次臨限值係數）增加，於形成言 夕動率 人回I王月匕之硬梦晉 時，存在電晶體性能不足的問題。 1 因而’為求形成更高性能之矽裝置，哈 ^ 降每射晶化之外， 逛開發出如更進步之SLS(序列側面固仆、堂从 )寺、、'σ晶性改善用 200306002 (2) 發勞說明續頁 之技術及（如參照美國專利第6300175號說明書（公開曰期 2〇〇1年1〇月9日））、CLC(CW雷射側面晶化）（如參照a. Hara et. al.，丨’Ultra-high Performance Poly-Si TFTs on a Glass by a Stable Scanning CW Laser Lateral Crystallization”，2001In addition, the present invention relates to a soi substrate formed by bonding a monocrystalline silicon film having an implantation layer for implanting hydrogen ions to a substrate and dividing the hydrogen ion implantation layer, and further relates to a display using the same. Device and manufacturing method of SOI substrate. In addition, the present invention relates to a semiconductor device used in an active matrix driving liquid crystal display device or the like to improve the circuit performance of a device that integrates peripheral driving circuits and control circuits, and a method of manufacturing the same. In the prior art, thin-film transistors (a-Si (amorphous silicon) and poly-crystalline silicon) (Thin Film Transistor (hereinafter referred to as "1 Π") were formed on a glass substrate to drive liquid crystal panels and organic EL panels. Carry out the so-called active matrix drive. Use the p-silicon with high-speed movement and high speed to perform the product of the peripheral driver. Or, to require a higher-performance image processor and time control, the system is integrated. And research to form a harder device with higher performance., Xijing silicon due to incomplete crystallinity ww gate local level and defects near the yttrium grain field and the existence of local levels within the gap led to the reduction and S coefficient (secondary threshold (Coefficient) increases, and when the hard-won dream of Wang Yuejian ’s success is formed, there is a problem of insufficient performance of the transistor. 1 Therefore, in order to form a higher-performance silicon device, ^ We have developed more advanced SLS (Sequence Side Fixer, Tangcong) Temple, 'σ Crystallinity Improvement 200306002 (2) Techniques for the continuation of the labor instructions and (eg, refer to US Patent No. 6300175 Specification (publication date October 9, 2001)), CLC (CW Laser Side Crystallization) (e.g. refer to a. Hara et. CW Laser Lateral Crystallization ", 2001

International Workshop on Active matrix Liquid Crystal Displays--TFT Technologies and Related materials--(AM-LCD200 1 )5 Digest of Technical Papers, p.227-230,July 11-13,2001，Japan Society of Applied Physics(日本應用物 理學會））。此等係在玻璃基板上堆積a-矽膜，著眼於如何有 效控制其晶化或如何接近單晶。 但是’此等使用雷射之技術係在低溫地保持玻璃等耐熱 性低之纟巴緣基板的溫度，而僅將石夕膜加熱至高溫進行結晶 生長。因而矽膜上通常施加約l〇9Pa之強拉扯應力，因而產 生膜龜裂、TFT特性之重現性不佳及變動大等的問題。 另外，尚有於絕緣基板上貼合單晶矽，將其予以薄膜化 之技術（如參照曰本公開專利公報特開平弘2iU28號公報 (公開日期1993年8月20日公開））。採用該技術時，於單晶矽 基板上形成氧化膜，可於其上形成單晶矽薄膜。但是欲與 矽=外之絕緣基板，如玻璃基板或石英基板接合時，因與 石央基板等之絕緣基板的熱膨脹係數差異，而存在矽剝落 或破壞的問題。 ° 針對此，為求防止因與石英基板之熱膨脹係數差異而於 加祕合強度提高步驟中造成上述破壞，冑一種改變晶化 玻璃之組成的方法（如參照日本公開專利公報特=平 200306002 (3) 發明說朗_頁 1 1-1633 63號公報（公開日期1999年6月18日公開））。 此外，如上所述’先前之加工單晶矽基板，於基板上形 成約數億個電晶體之積體電路元件技術；及於玻璃基板等 非晶質材料上形成矽膜等之多晶半導體薄膜後，加工電晶 體’製造液晶顯示裝置之像素及驅動器之薄膜電晶體（ΤΜη Film Transistor: TFT)液晶顯示裝置技術，除達到使用電腦 及液晶顯示裝置之個人資訊終端的普及之外，並且獲得重 大發展。 & 其中，積體電路元件係將市售之厚度不足lmm，直徑為 15〇 mm至300 mm之單晶矽晶圓予以加工，並在其上形成多 數個電晶體而製成。此外’ TFT液晶顯示裝置係將非晶質 無驗玻璃絲上之非晶質石夕膜以雷射等之熱溶㉟、多晶化 ，將其予以加工而製成切換元件2M〇s型電晶體。 使用前述TFT之前述液晶顯示裝置及有機EL顯示裝置領 域，係在透明之玻璃基板上形成非晶質石夕膜及多晶石夕膜之 啊’而形成進行前述像素驅動之所謂主動矩陣驅動用的 矽裝置。再者，為求自其主動矩陣驅動達到週邊驅、 :間控制器等系統之積體化，而研究形成更高性能之；裝 此因，多晶石夕膜因結晶性不完全性引起之間隙内 = 場附近之缺陷或間隙内存在局部位準導致移 =低=限值係數(S係數)增加，於形成高性能之發 衣置呀，存在電晶體性能不足的問題。 7International Workshop on Active matrix Liquid Crystal Displays--TFT Technologies and Related materials-(AM-LCD200 1) 5 Digest of Technical Papers, p.227-230, July 11-13, 2001, Japan Society of Applied Physics Physics Society)). These are a-silicon films deposited on glass substrates, focusing on how to effectively control their crystallization or how to approach single crystals. However, these techniques using lasers keep the temperature of low-heat-resistant substrates such as glass at a low temperature, and only heat the stone film to a high temperature for crystal growth. Therefore, a strong tensile stress of about 109 Pa is usually applied to the silicon film, which causes problems such as film cracks, poor reproducibility of TFT characteristics, and large variations. In addition, there is a technology for attaching a single-crystal silicon to an insulating substrate and thinning it (for example, refer to Japanese Unexamined Patent Publication No. Hirahiro 2iU28 (published on August 20, 1993)). When this technology is used, an oxide film is formed on a single crystal silicon substrate, and a single crystal silicon film can be formed thereon. However, when bonding to an insulating substrate other than silicon, such as a glass substrate or a quartz substrate, there is a problem of peeling or destruction of silicon due to a difference in thermal expansion coefficient between the insulating substrate such as a stone central substrate and the like. ° In view of this, in order to prevent the above-mentioned damage in the step of increasing the combined strength due to the difference in thermal expansion coefficient with the quartz substrate, a method of changing the composition of crystallized glass (for example, refer to Japanese Laid-Open Patent Publication No. Hei 200306002 ( 3) Inventory of the Invention Long_Page 1 1-1633 63 (Publication date: June 18, 1999). In addition, as described above, 'previously processed monocrystalline silicon substrates, integrated circuit element technology of forming hundreds of millions of transistors on the substrate; and polycrystalline semiconductor films such as silicon films on amorphous materials such as glass substrates. Later, the processing of the transistor 'manufactured the pixel and driver of the liquid crystal display device (TFT film transistor: TFT) liquid crystal display device technology, in addition to the use of computers and liquid crystal display devices of personal information terminals, and gained significant development of. & Among them, the integrated circuit element is manufactured by processing a commercially available single crystal silicon wafer having a thickness of less than 1 mm and a diameter of 150 mm to 300 mm, and forming a plurality of transistors thereon. In addition, the TFT liquid crystal display device is made of an amorphous stone film on an amorphous glass fiber and melted and polycrystallized by heat such as laser, and processed into a switching element 2M0s type transistor. . In the field of the foregoing liquid crystal display device and organic EL display device using the TFT, an amorphous matrix film and a polycrystalline matrix film are formed on a transparent glass substrate to form a so-called active matrix drive for driving the aforementioned pixels. Silicon device. In addition, in order to achieve the integration of peripheral drive systems, controllers, and other systems from its active matrix drive, research has been conducted to form higher performance; for this reason, polycrystalline silicon membranes are caused by incomplete crystallinity. In-gap = Defects near the field or local level in the gap leads to shift = low = increase of the limit coefficient (S coefficient). In the formation of high-performance hair, there is a problem of insufficient transistor performance. 7

因而著眼於SOI技術。前βA I之S01係矽絕緣體（Silicon Qr|So focus on SOI technology. Former βA I S01 series silicon insulator (Silicon Qr |

Insulator)的簡稱，係在絕 ⑽ 丞极上^成早晶+導體膜的 (4) (4)200306002 發明說明續頁 技術(通常不使用於形成多晶石夕膜）。該技術之領域約自 1981年起積極進行研究。而於積體電路領域中使；之go! 基板的目的在於製作良好之電晶冑，使半導體元件之功能 大幅提曰兩，因此基板只須絕緣膜即可，其可為透明或不透 明或疋可為晶質或非晶質。該領域中，藉由s〇I基板作成 電晶體時，因元件完全分離，因此動作上的限制小，而顯 不良好之電晶體特性。 目前市售+之SIM0X(矽植入氧）基板為主要之s〇i基板。該 SOI基板係藉由於石夕晶圓内植入氧所形成之氧化石夕層，自基 板表體分離單晶矽薄膜。因&，為求將遠比氫重之氧元素 植入特疋深度，須以咼能量、高濃度植入，因而存在導致 :晶：傷大，I晶性質不足，或是因二氧化矽膜部分之化 學計量偏差以致絕緣性不完全等問題。 口而於上述特開平5-2 1112 8號公報中揭示有··於基板上 貼合單晶石夕，將其予以薄膜化之技術。該先前技術係稱之 為精靈切割法之於單晶矽基板上藉由離子植入法植入氫離 子，與補剛材料貼合後，藉由熱處理，於前述植入氫離子 層内產生微小氣泡，以前述植入層分割前述單晶矽基板而 形成單晶矽薄膜，來實現S〇I構造，藉此可製造元件特性高 之單晶電晶體之非常優異的技術。 但疋，採用該先前技術時，僅揭示於單晶石夕基板上形成 氧化膜，並在其上形成單晶矽薄膜，並未檢討與前述顯示 裝置用之玻璃基板等其他基板之適用性。因而，檢討與其 他基板之接合例係揭示於上述特開平丨^丨63363號公報。該 200306002 (5) 發日興明續頁 先前技術揭示有：為求防止因提高與前述石英基板之接合 強度而進行之加熱步驟對石英基板之破壞，係使用晶化玻 璃，改變其組成，熱膨脹率因應矽片來接合之方法。 但是，晶化玻璃通常含鹼原子，具有與獲得特性穩定之 電晶體相反的性質。此外，以上之技術，由於單晶矽基板 之形狀為6, 8, 12吋之圓板，因此接合之絕緣基板限定於6， 8, 12吋之圓板，因而無法製造比其更大型之液晶顯示面板 及有機EL面板，此外，即使小型，其製造成本亦高，不易 實用化。 再者，使用石英基板時，於接合單晶矽基板與絕緣基板 時’因熱膨脹係數差異致使接合強度降低。此外，於接合 之界面上施加應力時，因施加於界面上之應力的不均一及 變動，而導致形成之TFT特性的惡化。 此外，上述之先前技術，在將單晶矽基板貼合於基板上 時，考慮若不暴露於高溫下即無法獲得充分之接合強度， 因而進行熱處理之溫度高達800〜1200。(：。因而存在適合應 變點在750°C以上之高耐熱晶化玻璃，而無法使用於一般使 用之應變點在700°C以下之高應變點無鹼玻璃上的問題。 發明内容 本發明之目的在提供一種具有單晶矽薄膜之特性穩定之 大型且廉價之基板，且單晶矽薄膜之接合強度及施加於接 合界面之應力無不均一及變動之半導體裝置及其製造方法。 本發明之其他目的在提供一種具有單晶矽薄膜之特性穩 定之大型且廉價之基板的半導體裝置。 -10- (6) (6)200306002(4) (4) 200306002 Description of the Invention Continued technology (usually not used to form polycrystalline stone evening film). The field of this technology has been actively researched since about 1981. In the field of integrated circuits, the purpose of the go! Substrate is to make a good transistor, so that the function of the semiconductor element is greatly improved, so the substrate only needs an insulating film, which can be transparent or opaque or 疋It can be crystalline or amorphous. In this field, when a transistor is formed on a SiO substrate, the components are completely separated, so the operation limitation is small, and the transistor characteristics are not good. Currently, a commercially available + SIM0X (silicon implanted oxygen) substrate is the main soi substrate. The SOI substrate is a single crystal silicon thin film separated from the surface of the substrate by an oxide stone layer formed by implanting oxygen in the stone chip. Because &, in order to implant the oxygen element far heavier than hydrogen into the special radon depth, it must be implanted with radon energy and high concentration, so the existence of: crystal: large injury, insufficient crystal properties, or silicon dioxide The stoichiometry deviation of the film portion causes incomplete insulation. In the above-mentioned Japanese Patent Application Laid-Open No. 5-2 1112 8, there is disclosed a technique of laminating a single crystal on a substrate to form a thin film. The previous technology is called the sprite cutting method. Hydrogen ions are implanted on the single crystal silicon substrate by ion implantation. After bonding with the stiffening material, heat treatment generates microscopic particles in the implanted hydrogen ion layer. Bubbles, the aforementioned single crystal silicon substrate is divided by the aforementioned implantation layer to form a single crystal silicon thin film, so as to realize the SOI structure, thereby making it possible to produce a single crystal transistor with high element characteristics. However, when this prior art was adopted, it was only revealed that an oxide film was formed on the monocrystalline substrate and a monocrystalline silicon thin film was formed thereon. The applicability to other substrates such as glass substrates for display devices was not reviewed. Therefore, examples of the connection between the review and other substrates are disclosed in the aforementioned Japanese Patent Application Laid-Open No. 63363. The 200306002 (5) Fa Ri Xingming continuation page The previous technology revealed that in order to prevent the quartz substrate from being damaged by the heating step performed to increase the bonding strength with the aforementioned quartz substrate, crystallized glass was used to change its composition and thermal expansion rate The method of bonding according to the silicon wafer. However, crystallized glass usually contains an alkali atom, and has properties opposite to those of a transistor having stable characteristics. In addition, in the above technology, since the shape of the single crystal silicon substrate is a 6, 8, 12-inch circular plate, the bonded insulating substrate is limited to a 6, 8, 12-inch circular plate, so it is impossible to manufacture a larger-sized liquid crystal. In addition, the display panel and the organic EL panel have high manufacturing costs even if they are small, and are not easy to be put into practical use. Further, when a quartz substrate is used, when a single crystal silicon substrate and an insulating substrate are joined, the difference in thermal expansion coefficient causes the joint strength to decrease. In addition, when stress is applied to the bonded interface, the unevenness and variation of the stress applied to the interface deteriorates the characteristics of the formed TFT. In addition, in the above-mentioned prior art, when a single-crystal silicon substrate is bonded to a substrate, it is considered that sufficient bonding strength cannot be obtained without being exposed to high temperatures, and thus the heat treatment temperature is as high as 800 to 1200. (:. Therefore, there is a problem that it is suitable for high heat-resistant crystallized glass with a strain point of 750 ° C or more, and cannot be used on high-strain point alkali-free glass with a strain point of 700 ° C or less in general use. SUMMARY OF THE INVENTION The purpose is to provide a large-scale and inexpensive substrate with stable characteristics of a single-crystal silicon film, and a semiconductor device having no unevenness and variation in the bonding strength of the single-crystal silicon film and the stress applied to the bonding interface, and a method for manufacturing the same. Another object is to provide a semiconductor device having a large and inexpensive substrate with stable characteristics of a single crystal silicon film. -10- (6) (6) 200306002

發明說明I 璃及古 f々在如供一種不使用調節組成之晶化玻 =耐熱麵’可以低成本製造S0I基板之 用其之顯示裝置與S0I基板製造方法。 使 上，本發明之半導體裝置之特徵為：於 广、. /晶石夕薄膜與單晶石夕薄膜分別形成於不同之 區域。 藉由上述構造，於大型之玻璃基板等絕緣基板上 矽薄膜與單晶石夕薄膜分別形成於不同之區域。可藉 曰曰曰 石夕消除於形成高性能之裝置時成為障礙之因多晶^内特: 之結晶性不完全性引起之間隙内之局部位準、結晶粒場附 近之缺陷及間隙内存在局部位準導致移動率降低及3係數 (次限值係數)增加等問題。因此’可在單晶矽薄膜之形 成區j形成要求更高性能之裝置，如時間控制器，而在‘ 晶梦薄膜之形成區域形成其他的裝置。 亦即’即使單晶發薄膜之尺寸有限，只須為於形成要求 必要之高速性 '耗電及變動之高速邏輯、時間產生 器' 高速之DAC(電流緩衝器)等時之足夠尺寸即可。因此 可在基板上一體積體化僅以單晶矽即可實現之高性能、高 功能之電路系、统，因此與以單晶石夕形成全部裝置時比較了 可以非常低的成本製造積體化高性能系統之液晶面板或有 機;EL面板等顯不裝置用之半導體裝置。 此外，單晶矽之基板形狀雖限定於LSI製造裝置之晶圓尺 寸之6, 8, 12吋之圓板，但由於在基板上亦形成多晶矽薄膜 ，因此亦可製造如大型之液晶顯示面板及有機El面板。、 -11 - 200306002 ⑺ 發轉酬 此外’為求達成上述目的， 方法係在絕緣基板上形成有多曰：〆之半導體裝置之製造 特徵為包含：堆積步驟 二=與單晶石夕薄膜，其 化石夕膜及非晶”膜；乡^=緣基板表面依序堆積氧 非曰質石夕胺 日日夕薄膜形成步驟，其係將前述 薄膜·、勒多晶矽層生長而形成多晶矽 區域；切斷步驟，其係將預先多晶石夕層之特定 且具有在特定深度植人特定=化表面或堆積氧化石夕膜’ 之I特疋/辰度之氫離子之氫離子植入部 之早日日矽基板切割成覆蓋 分或大致全部區域㈣去之區域形狀之一部 述切斷之單晶石夕基板使植二雜：者貼合步驟，其係將前 鞋刻除去之區域；及單曰“：子侧之面密著貼合於前述 理，以前述氫離子植：:;:邊：成步驟’其係藉由熱處 藉由上述構造，萨由力轨形成單晶矽薄膜。 離子之單晶矽基板：广於特定深度植入特定濃度之氫 ^ ^ 土亦即具有預先植入有氫離子之部分< 虱離子植入部之單曰功丁<丨刀< 以氫離子植人，可提高接合強度，並且藉由 膜。因而心^=離單_基板可獲得單晶石夕薄 之因多曰矽內胜：’肖除於形成高性能之裝置時成為障礙 之結晶性不完全性引起之間隙内之局部 千、、、口日日粒％附近之姑々 動率降低及S係數增加等問題。；此，二 二二 薄膜，以後之步驟以共通之加工製程 其餘裝π:::求更高性能之裝置，而以多-夕形成 σ以低成本製造積體化高性能系統之液晶 -12- (8)200306002 發明說明續頁 面板或有機EL面板等顯示裝 _________Description of the invention I glass and glass f. In the case of providing a crystallized glass without adjusting the composition = heat-resistant surface ', a display device and a method for manufacturing a SOI substrate can be manufactured at low cost. Therefore, the semiconductor device of the present invention is characterized in that the y / y thin film and the single crystal y thin film are formed in different regions, respectively. With the above structure, a silicon thin film and a single crystal thin film are formed on different regions on an insulating substrate such as a large glass substrate. It can be said that Shi Xi can eliminate the polycrystalline ^ which is an obstacle when forming a high-performance device. Nate: Local levels in the gap caused by incomplete crystallinity, defects near the crystal grain field, and the existence of gaps The local level leads to problems such as a decrease in the mobility rate and an increase in the 3-factor (sub-limit coefficient). Therefore, a device requiring higher performance can be formed in the formation region j of the single crystal silicon thin film, such as a time controller, and other devices can be formed in the formation region of the single crystal silicon thin film. That is, even if the size of the single-crystal hair film is limited, it only needs to be a sufficient size for forming a high-speed DAC (current buffer), etc., which requires the required high-speed performance, high-speed logic and time generator that consume power and changes. . Therefore, a high-performance, high-functionality circuit system that can be realized only with single crystal silicon can be integrated on a single substrate. Therefore, it is possible to manufacture a product at a very low cost compared with when all devices are formed using single crystal silicon. High-performance system of liquid crystal panels or organic; EL panels and other semiconductor devices used in display devices. In addition, although the shape of the substrate of monocrystalline silicon is limited to 6, 8, 12-inch wafers of the wafer size of LSI manufacturing equipment, since polycrystalline silicon thin films are also formed on the substrate, it is also possible to manufacture large-scale liquid crystal display panels and Organic El panel. , -11-200306002 ⑺ In order to achieve the above purpose, the method is to form a semiconductor device on an insulating substrate. The manufacturing characteristics of the semiconductor device include: stacking step 2 = and monocrystalline silicon thin film, which Fossil evening film and amorphous "film; the step of sequentially forming an oxygen non-crystalline stone substrate on the edge of the substrate is to form a polycrystalline silicon region by growing the aforementioned thin film and polycrystalline silicon layer; , Which is an early silicon that implants a specific polycrystalline stone layer in advance and has a hydrogen ion implantation part of a specific ion / Chen degree of hydrogen ion implanted at a specific depth to a specific surface or deposited on a specific oxide layer. The substrate is cut into a part of the shape of the area covered by or substantially all of the area, and the cut monocrystalline substrate is described as a part of the planting process: the fitting step is an area where the front shoe is engraved; and : The sub-side surface is closely adhered to the aforementioned principle, and is implanted with the aforementioned hydrogen ions ::;: edge: forming step 'It is the formation of a single-crystal silicon film by a thermal process and the above-mentioned structure. Ion single-crystal silicon substrate: implanted with a specific concentration of hydrogen more widely than a specific depth ^ ^ The soil has a part implanted with hydrogen ions in advance < the single-cut function of the lice ion implantation part < 丨 knife < to Hydrogen ions are implanted into humans, which can improve the bonding strength, and through the membrane. Therefore, the reason ^ = away from the single _ substrate can obtain the monocrystalline stone, and the reason is that the silicon wins: 'Xiao except for the local incompleteness in the gap caused by the crystalline incompleteness that becomes an obstacle when forming a high-performance device. , The decrease in the rate of movement around the daily grain percentage and the increase in the S coefficient. ; This, two two two thin films, the subsequent steps to a common processing process to install the remaining π ::: for higher performance devices, and multi-phase formation σ to manufacture integrated high-performance liquid crystal system at low cost-12 -(8) 200306002 Description of the invention Continued display panel or organic EL panel display equipment _________

此外，由於係預先形成氧化層或氧化矽膜，並經由其在 玻璃基板等絕緣基板上接合單晶矽基板，因此可防止因施 加於接合之石夕界面之應力造成石夕結晶應變而引起之移動率 降低，或是界面之缺陷及隨伴其之界面固定電荷、界面之 局部位準造成之臨限值偏差、特性穩定性降低等。藉此， 然須為求防止因與石英基板之熱膨脹係數差異所實施之加 熱接合強度提高、剝離步驟造成的破壞，而使用調整組成 之晶化玻璃，而可使用高應變點玻璃。因而不存在晶化玻 璃之鹼性金屬造成污染的問題，可防止因熱膨脹係數差異 所實施之加熱接合強度提高、剝離步驟造成的破壞。^ 再者，如於大面積之高應變點玻璃基板上形成多晶矽膜 ’、以覆蓋須接合加工成適切尺寸之單晶石夕基板之區域的方 式，預先餘刻除去多晶梦薄膜。 —+後m域内接合單晶石夕基板，藉由剝離保留單晶石夕 =膜與氧切膜。並藉㈣離除去以外之單晶可消除 正個玻璃基板的應力偏差。 '、In addition, since an oxide layer or a silicon oxide film is formed in advance, and a single crystal silicon substrate is bonded to an insulating substrate such as a glass substrate through the same, it is possible to prevent the crystal strain caused by the stress caused by the stress applied to the bonded interface. Reduced mobility, or defects in the interface and accompanying fixed charges on the interface, threshold deviations due to local levels of the interface, and reduced characteristic stability. Therefore, it is necessary to use a crystallized glass with an adjusted composition in order to prevent damage caused by the increase in thermal bonding strength and the peeling step due to the difference in thermal expansion coefficient between the quartz substrate and the high strain point glass. Therefore, there is no problem of contamination caused by the alkali metal of crystallized glass, and it is possible to prevent the damage caused by the thermal bonding strength improvement and the peeling step performed due to the difference in thermal expansion coefficient. ^ Furthermore, if a polycrystalline silicon film is formed on a large-area high-strain-point glass substrate, the polycrystalline dream film is removed in advance so as to cover the area to be bonded to be processed into a single-crystal monolithic substrate of an appropriate size. The monocrystalline substrate is bonded to the ++ region after m, and the monocrystalline substrate is retained by peeling = the film and the oxygen cut film. By removing the single crystals by removing them, the stress deviation of a glass substrate can be eliminated. ',

該區域預先氧化表面或堆疊氧化㈣，且將接 接mr!4人部侧之面密著於前述钱刻除去區域，來 刻除去之區域形狀之一二：：：基板切斷成覆蓋編 單晶發基板，心施或大致全部區域之特定形狀的 剝離單晶石夕基板，而伴留=，：虱離子植入部為邊界來 離除去其他之單、早晶石夕缚膜與氧化石夕膜，藉由剝 早曰曰石夕’可消除整個玻璃基板之應力偏差。 -13- (9) 200306002 發明說明續頁 藉此，不產生石夕之剝落、龜裂及破壞，可獲得基板之一 部分區域包含單晶⑪薄膜，其餘區域部分包含多晶石夕薄膜 之基板。 此外早曰曰石夕基板之形狀雖限定於LSI製造裝置之晶圓尺 8, 12对的圓板’但是由於在絕緣基板上亦形成多晶 :=因此可製造如大型之液晶顯示面板及有機此面板 4 +導體裝置。This area is oxidized in advance or stacked with plutonium oxide, and the surface connecting to the mr! 4 human body side is closely adhered to the aforementioned money-cut area, one of the shapes of the area to be removed: 2: The substrate is cut into a cover sheet Crystal hair substrate, single-crystal stripped substrate with a specific shape in the heart or almost the entire area, and entrapment = ,: The lice ion implantation part is used as a boundary to remove other single, premature spar film and oxide stones Evening film, by peeling the stone early, it can eliminate the stress deviation of the whole glass substrate. -13- (9) 200306002 Description of the Invention Continued By this, without exfoliating, cracking, or damaging of Shi Xi, one of the substrates can be obtained with a single-crystal gadolinium thin film in a part of the substrate, and a polycrystalline stone Xi thin film in the remaining area. In addition, although the shape of the Shi Xi substrate was limited to the wafer scale of 8, 12 pairs of wafers of LSI manufacturing equipment, but because polycrystals are also formed on the insulating substrate: =, it is possible to manufacture large-scale liquid crystal display panels and organic This panel has 4+ conductor devices.

:::二為求達成上述目的，本發明之半導體裝置之製造 方法係在絕緣基板上形忐古夕s 成有夕日日矽溥膜與單晶矽薄膜，其 特欲為匕§ •堆積步驟，1 化石夕膜及非晶質舞./a、=緣基板表面料堆積氧 非曰所坊胺；、 夕日日矽溥膜形成步驟，其係將前述 薄膜刻除去步驟…：二：夕層生長而形成多晶石夕 石夕声，…二I 除去特定區域之前述多晶 一邱八· + ^止 飞之刚述乳化石夕膜在厚度方向之 口ρ刀，切斷步驟，其係將預先 门之 ，且具有在特定、、 或堆積氧化矽膜 巧牡付疋，木度植入特定黨 & 部之單晶石夕基板切巧成又11料之氫離子植入::: Second, in order to achieve the above-mentioned object, the method for manufacturing a semiconductor device of the present invention is to form an ancient silicon substrate and a single-crystal silicon film on an insulating substrate, which is specifically intended to be a stacking step. , 1 Fossil ray film and amorphous dance. / A, = accumulation of oxygen on the surface of the edge substrate, oxygen amines; xi day, silicon silicon film formation step, which is the step of removing the aforementioned thin film ... Growth and formation of polycrystalline stone Xixiansheng, ... two I remove the aforementioned polycrystalline in a specific area-Qiu Ba · + ^ Zhi Feizhi just described the mouth of the emulsified stone film in the thickness direction, cutting step, the system The monolithic substrate with a preliminarily gated, and silicon oxide film deposited on a specific, or stacked silicon substrate is cut into a hydrogen ion implantation of 11 materials

部八十山 成復盍則述蝕刻除去之區域形狀之一 ^^刀或大致全部區域的特定 前述切斷之單曰矽其## & 在耆貼合步驟，其係將 踯之早日日矽基板使植入氫離子側 述钱刻除去之區域；及單晶石夕薄膜山耆“於前 處理，以前述氫離子植人部為邊界㈣^驟，/日係藉由熱 藉由上述構造，除前述製造方法 ^成早曰曰矽薄膜。 刻除去特定區域之多晶石夕層，並且^點之外’且由於餘 崎厚度方向之-部分，因此可消=該區域之氧化 除早日日矽基板之貼附 -14- 200306002 (ίο) 發明說明續頁 面=氧切膜之厚度的影響，可獲得絕緣基板上之單晶 二==晶矽薄膜之區域高度大致相等的基板。因而可 ==狀银刻之以後大部分的步驟。此外，藉此形成 L::::晶體或電路。因而，如為液晶面板時，單元厂: 方在上述目的’本發明之半導體裝置之製造 特徵為包含:；=成！多晶㈣膜與單晶石夕薄膜，其 m /、係於絶緣基板表面堆積氧化矽 膜在步驟，其係㈣除去特定區域之前述 或堆積氧化膜，且呈^ ^步驟’其係將預先氧化表面 之氫離子植入部之單入特定濃度之氫離子 區域形狀之-部分板切剔成覆蓋前述㈣除去之 ㈣，其係將二狀; 密著貼合於前述敍刻除去：二夕基!?？植，氯離子侧之面 其係藉由熱處理，以^、^早00W膜形成步驟， 單晶石夕薄膜；堆積牛；：離子植入部為邊界剝離而形成 第二氧化石夕膜及非二V、係於前述絕緣基板上依序堆積 係將前述非晶質矽：：石膜’及多晶矽薄膜形成步驟，其 成多晶石夕薄膜夕搞予以加熱晶化’使多晶石夕層生長而形 π上得與前述各製造方法相同之優點。 貼合植入氯離子之單述曰:的片，本發明基㈣^ 述單晶石夕片，而开片，以雨述氯離子植入層分割前 早曰曰矽薄膜，其特徵為··將前述基板 -15- 2UU306002 (11) 發明說明續ί 作為非晶質無驗玻璃基板。 藉由上述構造，於藉由 離子植人法於前述單晶W内植法等，其係藉由 前述氫離子植入層上產生氣脆化風雄子’藉由熱處理於 宝，丨前、十、0 a '^ 化，以該氫離子之植入層分 口J刖述早日日矽片而形成單晶 貼人仏fy /寻膜，所獲得之單晶矽薄膜 、占。於基板上所作成之S0I基板 單曰坊ΰ ^ ^ 土販f本發明人著眼於使前述 早曰曰矽片貼合於基板上時，即 ^ % ^ m , 1使、、0 30〇 c仍可獲得足夠之接The part of the eighty mountains into a complex is described as one of the shapes of the area removed by etching ^^ The blade or almost all of the area is cut by the aforementioned single-silicon ## & In the bonding step, it is an early date of The silicon substrate allows the implanted hydrogen ions to be removed from the side, and the monocrystalline stone thin film mountain stream is "pre-processed, with the aforementioned hydrogen ion planting part as a boundary step, / Japanese system by heat through the above Structure, in addition to the aforementioned manufacturing method ^ into the early-stage silicon thin film. The polycrystalline stone layer in a specific area is etched, and ^ points are excluded, and because of the-part of the thickness direction of Yuzaki, it can be eliminated = oxidation in this area Attaching the silicon substrate as soon as possible-14- 200306002 (ίο) Description of the invention Continued page = Influence of the thickness of the oxygen cut film, a single crystal on an insulating substrate == crystalline silicon film can be obtained with approximately equal height. Can == the shape of silver, most of the steps after the engraving. In addition, L ::::: crystals or circuits are formed by this. Therefore, if it is a liquid crystal panel, the cell factory: In the above purpose, 'Semiconductor device manufacturing of the present invention' Features include:; = cheng! Polycrystalline osmium film and monocrystalline stone thin In the step, the silicon oxide film is deposited on the surface of the insulating substrate. In the step, it is to remove the aforementioned or stacked oxide film in a specific area, and it is in the step of ^^. The shape of the hydrogen ion region that is single-entered into a specific concentration-a part of the plate is cut to cover the above-mentioned ㈣ and removed, which is two-shaped; closely attached to the foregoing narrative and removed: Erxyl! ?? Plant, chloride ion side The surface is formed by a heat treatment with a film formation step of ^, ^ as early as 00W, a monocrystalline stone film; stacked cattle ;: the ion implantation part is peeled off as a boundary to form a second oxide film and a non-two V, is The aforementioned sequential deposition on the insulating substrate is a step of forming the aforementioned amorphous silicon: stone film and polycrystalline silicon thin film, which forms a polycrystalline silicon film and heats it to crystallize it so that the polycrystalline silicon layer grows to form π. It has the same advantages as the above-mentioned manufacturing methods. The single-layered sheet which is attached with chloride ion implantation, the present invention is based on the single crystal evening sheet, and the open sheet is separated by the first-class chloride-ion implantation layer. Earlier, it was said that the silicon film is characterized by the following substrate-15-2UU306002 ( 11) Description of the invention Continued As an amorphous glassless substrate. With the above structure, the above-mentioned single crystal W internal implantation method by the ion implantation method, etc., is generated by the aforementioned hydrogen ion implantation layer. The embrittlement wind male 'was heat-treated at Yubao, before, ten, and 0 a' ^, and the hydrogen ion implantation layer was used to describe the early silicon wafer to form a single crystal paste fy / seek film The obtained single-crystal silicon thin film is made up of a SOI substrate made on a substrate. ^ 土 贩 f The inventor focuses on making the aforementioned silicon wafer adhere to the substrate, that is, ^% ^ m, 1 so that 0, 30c can still get enough access

σ強度’因此可低於先前設定楹古 声，7m 疋徒呵接合強度用之熱處理溫 度可使用應變點在700°c以下之韭曰陆> 缺+ π 下之非日日^無鹼玻璃基板。 ^ ^ β马衣將早晶矽片切割成單晶 迭牛！？中而量遠比氧離子輕之氫離子時，於元件製 :二=熱處理溫度約為崎即可。籍由施加該程度之 :=!可自單晶石夕片内之氣離子植入層排出氯而 質恢復：：石"版’亚且亦可一併進行將單晶石夕薄膜之晶 =设成以離子植人前相等的水準，而抑制日aaf降低的 :。、因此’藉由進行該約_t之溫度的熱處理，可改善σ strength 'can therefore be lower than the previously set 楹 ancient sound. The heat treatment temperature for the joint strength of 7m can be used with a strain point below 700 ° c. Non-day ^ alkali free glass Substrate. ^ ^ β horse clothing cuts early-crystal silicon wafers into single crystals. ? When the amount of hydrogen ions is much lighter than the oxygen ions, in the device system: two = heat treatment temperature is about saki. By applying this degree: =! Can recover chlorine from the gas ion implantation layer in the monocrystalline stone film and recover it qualitatively:: stone " version 'Asia and also can perform monocrystalline crystal = Set to the same level as before implantation with ions, and suppress the decrease of the daily aaf :. ， Therefore, by performing the heat treatment at a temperature of about _t, it can be improved

^分離及晶m亦可提高對單_片之基板的 刀0 入二1以所謂之精靈切割法等所獲得之單晶矽薄膜貼 二於基板上而作成之S0I基板中，著眼於將前述單晶矽片貼 :於基板上時，以約赋即可獲得足夠之接合強度，其基 ί係t用非晶質無鹼玻璃基板，以最高溫度約6〇〇°C，進行 珂述單晶矽片與基板之貼合及與薄膜之分離。 口此，热須使用調整組成之晶化玻璃及高耐熱之玻璃， -16- 200306002 (12) 明續頁 使用藉由主動矩陣驅動之液晶顯示面板等一般所使用之 回應艾點無鹼玻璃’即可以低成本製造S0I基板。此外，因 熱處理溫度低，因此可防止鹼性金屬向半導體層擴散。藉 此，由於防止其鹼性金屬之擴散，因此可減少如形成於單 晶矽片侧之氧化膜及形成於基板側之二氧化矽膜等的膜厚 ，而可提高通量。^ Separation and crystal m can also improve the knife for single-piece substrates. 0 Into the S0I substrate made by attaching the single-crystal silicon thin film obtained by the so-called spirit cutting method to the substrate, focusing on the aforementioned Monocrystalline silicon wafer: When it is on the substrate, sufficient bonding strength can be obtained with the approximate thickness. The base is an amorphous alkali-free glass substrate. The maximum temperature is about 600 ° C. Lamination of crystalline silicon wafers to substrates and separation from thin films. For this reason, heat-adjusted crystallized glass and highly heat-resistant glass must be used. -16-200306002 (12) The following pages use the commonly used response Ai-point alkali-free glass such as liquid crystal display panels driven by active matrix. That is, the SOI substrate can be manufactured at low cost. In addition, since the heat treatment temperature is low, the diffusion of the alkali metal into the semiconductor layer can be prevented. As a result, the diffusion of the alkali metal can be prevented, so that the thickness of the oxide film formed on the single crystal silicon wafer side and the silicon dioxide film formed on the substrate side can be reduced, and the flux can be improved.

另外，本發明之前述S0I基板亦可為包含於大面積之玻璃 基板的一部分貼附有前述單晶矽片之SOI的基板。 • 2外，為求達成上述目的，本發明之顯示裝置之特徵為 •丽述非晶質無鹼玻璃基板係使用透過可視光之非晶質玻 璃材料之前述任何一種SOI基板。 一藉由上述構造’前述非晶質無鹼玻璃基板採用透過可視 先之非晶質玻璃材料，於前述單晶砍薄膜上形成另外形成 之多晶石夕薄膜等及電晶體，可構In addition, the SOI substrate of the present invention may be a substrate included in a large-area glass substrate with the SOI of the single crystal silicon wafer attached thereto. • In addition, in order to achieve the above-mentioned object, the display device of the present invention is characterized in that: • The Lisuo amorphous alkali-free glass substrate is any one of the aforementioned SOI substrates using an amorphous glass material that transmits visible light. According to the above-mentioned structure ', the aforementioned amorphous alkali-free glass substrate is made of a transparent amorphous glass material, and a separately formed polycrystalline silicon film and the like and an electric crystal are formed on the aforementioned single-crystal chopped film.

再风，夜日日頌不叙置及有機EL 顯不裝置之基板。 面積基板的部分形成高 因此，可於顯示裝置用之需要大 性能之電晶體。Then again, the day and night chanting the substrate and the organic EL display device. The area of the substrate is high. Therefore, it can be used in a display device that requires a large-performance transistor.

/此外，4求達成上述㈣，本發明之則基板之 係於基板上貼合植入氫離子單 ^ " / ^ ^ ^ _ 早日日矽片，猎由熱處理，以 刖述風•子植入層分割前述單晶石夕 ，苴特徵為·铪、+、盆化技m /取早日日石夕溥胰 二ϋ為1述基板使用非晶質無鹼玻璃基 丽述熱處理之單晶矽的分割步驟 、，於 之溫度進行熱處理。 係、以取->皿度約為赋 藉由上述構造，於基板上貼合 以則述精靈切割法等所獲 -17- (13) (13)200306002 發明說明續頁 :二單晶石夕薄膜而作成之S0I基板的製造方法中，本發明人 糸者眼於將前述單晶石夕片貼人於其 π從π 义早曰曰7片貼。於基板上時，即使約300°C仍 了 k侍足夠之接合強度，而將埶處 丁…处主炙取阿溫度設定在分 〇,則处單晶石夕片之約600°C的溫度，如㈣O〇c，30〜60分鐘 進行處理。 因此，無須使用調整組成之晶化玻璃及高耐熱之玻璃， =使用藉由主動矩陣驅動之液晶顯示面板等一般所使用之 回應、交點無鹼玻璃，即可以低成本製造§〇1基板。此外，因 熱處理溫度低，因此可防止鹼性金屬向半導體層擴散。藉 此，由於防止其鹼性金屬之擴散，因此可減少如形成於單 曰曰矽片側之氧化膜及形成於基板側之二氧化矽膜等的膜厚 ，而可提高通量。 此外’為求達成上述目的，本發明之3〇1基板之製造方法 係於基板上貼合植入氫離子之單晶矽片，藉由熱處理，以 $述氫離子植入層分割前述單晶矽片，而形成單晶矽薄膜 ’其特徵為：前述基板使用非晶質無鹼玻璃基板，並且於 别述熱處理之單晶石夕的分割步驟中，係以包含約8 5 〇。〇以上 之峰值溫度的燈退火進行熱處理。 藉由上述構造，於基板上貼合以前述精靈切割法等所獲 得之單晶矽薄膜而作成之SOI基板的製造方法中，本發明人 係著眼於將前述單晶石夕片貼合於基板上時，即使最高溫度 約600°C仍可獲得足夠之接合強度，而以包含約85〇°C以上 之峰值溫度的燈退火進行熱處理。 因此’無須使用調整組成之晶化玻璃及高对熱之玻璃， -18- 200306002 (14) 發明說明續頁 而使用藉由主動矩陣驅動之液晶顯示面板等一般所使用之 高應變點無驗玻璃，即可以低成本製造S ΟI基板。此外，因 熱處理溫度低，因此可防止鹼性金屬向半導體層擴散。藉 此，由於防止其鹼性金屬之擴散，因此可減少如形成於單 晶石夕片侧之氧化膜及形成於基板側之二氧化石夕膜等的膜厚 ，而可提高通量。 此外，以電爐加熱，將玻璃基板加熱至應變點以上之高/ In addition, 4 to achieve the above, the principle of the present invention is to attach a hydrogen ion implantation substrate on the substrate ^ " / ^ ^ ^ _ Early silicon wafers, hunted by heat treatment, to describe the wind • Zi Zhi The above-mentioned single crystal stone is divided into layers, and the characteristics are: · 铪, +, potting technology m / Take the early sun stone evening, pancreas, second crystal is a monocrystalline silicon substrate using amorphous alkali-free glass-based heat treatment. In the step of dividing, heat treatment is performed at the temperature. The system is based on the above-mentioned structure, which is obtained by applying the above-mentioned structure to the substrate by using the wizard cutting method, etc. -17- (13) (13) 200306002 Description of the invention Continued: two monocrystals In the method for manufacturing a SOI substrate made of a thin film, the present inventor's eyes are to attach the aforementioned single crystal evening piece to 7 pieces of π from π. When it is on the substrate, the bonding strength is sufficient even at about 300 ° C, and the temperature of the processing unit is set to minus 0, and the temperature of the single crystal evening wafer is about 600 ° C , Such as ㈣0〇c, 30 ~ 60 minutes for processing. Therefore, there is no need to use crystallized glass with adjusted composition and high heat-resistant glass. = Use of response and intersection alkali-free glass, such as liquid crystal display panels driven by active matrix, can produce §〇1 substrate at low cost. In addition, since the heat treatment temperature is low, the diffusion of the alkali metal into the semiconductor layer can be prevented. As a result, the diffusion of the alkali metal is prevented, and thus the thickness of the oxide film formed on the silicon wafer side and the silicon dioxide film formed on the substrate side can be reduced, and the flux can be increased. In addition, in order to achieve the above-mentioned object, the manufacturing method of the 301 substrate of the present invention is to attach a single crystal silicon wafer implanted with hydrogen ions on the substrate, and divide the foregoing single crystal with the hydrogen ion implantation layer by heat treatment It is characterized in that a monocrystalline silicon thin film is formed by a silicon wafer, wherein the aforementioned substrate is an amorphous alkali-free glass substrate, and in a separate step of the heat-treated monocrystalline stone, it contains about 85.0. The lamp is annealed at a peak temperature of 〇 or more to perform heat treatment. With the above-mentioned structure, in the manufacturing method of an SOI substrate made by laminating a single-crystal silicon film obtained by the aforementioned sprite cutting method on a substrate, the present inventors focused on bonding the single-crystal wafer to the substrate. At this time, sufficient joint strength can be obtained even at a maximum temperature of about 600 ° C, and heat treatment is performed by lamp annealing including a peak temperature of about 85 ° C or more. Therefore, 'there is no need to use crystallized glass and high heat-resistant glass with adjusted composition, -18-200306002 (14) Description of the Continuation Sheet and use of high-strain-point non-inspection glass such as liquid crystal display panel driven by active matrix That is, it is possible to manufacture the SOI substrate at low cost. In addition, since the heat treatment temperature is low, the diffusion of the alkali metal into the semiconductor layer can be prevented. As a result, the diffusion of the alkali metal can be prevented, so that the thickness of the oxide film formed on the single crystal chip side and the dioxide film formed on the substrate side can be reduced, and the flux can be increased. In addition, the glass substrate is heated to a height above the strain point by electric furnace heating.

溫時’基板產生收縮，但是藉由燈等瞬間熱退火（RapidAt temperature ’, the substrate shrinks, but is thermally annealed instantaneously by a lamp, etc. (Rapid

Thermal Anneal，以下稱RTA)及藉由雷射加熱（雷射退火） 時，則可防止整個基板收縮，且提高須退火位置之溫度， 可使結晶性或分離效率提高。再者，亦可提高製造s〇i基板 上的通量。 另外，燈退火之峰值溫度愈高愈可提高電晶體之特性 不過由於基板之翹曲及伸縮大，因此只須因應基板尺寸 形成之裝置的種類選擇適切之溫度及保持時間即可。 3〇〇〜400 mm等級之基板係在·。c下保持約$分鐘。Thermal Anneal (hereinafter referred to as RTA) and laser heating (laser annealing) can prevent the entire substrate from shrinking, and increase the temperature of the annealing position, which can improve the crystallinity or separation efficiency. Furthermore, it is possible to increase the flux on the substrate. In addition, the higher the peak temperature of the lamp annealing, the more the transistor characteristics can be improved. However, due to the large warpage and expansion of the substrate, it is only necessary to select an appropriate temperature and holding time according to the type of the device formed by the substrate size. 300 ~ 400 mm grade substrates are attached to ·. Hold under c for about $ minutes.

之達成上述目的，本發明之S〇1基板之製造方; ^ 、隹和一氧化矽膜及非晶質矽膜.多日# 1p 形成步驟，其係將前述非晶質石夕膜予 -層生長而形成多晶編;二=:晶：::吏多』 去預定區域之前述多 飾“驟’其係崎 述二氧切膜在厚度方向:一：=除去相同區域。 氧化前述單晶矽片 刀植入步驟，其係預$ 片之表面或堆疊二氧切膜，並植入前对 -19- (15) 200306002To achieve the above object, the manufacturer of the S01 substrate of the present invention; ^,, and a silicon oxide film and an amorphous silicon film. Multi-day # 1p formation step, which is the aforementioned amorphous stone film to- The layer grows to form a polycrystalline braid; two =: crystalline: :: clerk. Go to a predetermined area of the above-mentioned multi-decoration "suddenly" its system is described in the thickness direction: one: = remove the same area. Crystal silicon blade implantation procedure, which is the surface of a pre-slice or stacked oxygen cut film, and the implantation is -19- (15) 200306002

飞離子，切断步驟，Μ 切斷成覆蓋前述_ μ $ μ子之早晶石夕片 1伤蔣义.+、+ xj除去之區域的形狀；密著貼合步驟 其係將刖述切斷之單 /私， 貼合於前述钱刻除去：二V 植入氣離子側之面密著 俜實施$ ” D°或，及單晶矽薄膜形成步驟，复 你員％刖述熱處理，驻^_ 具 而艰忐即曰* 一 猎由别述虱脆化使前述單晶矽片分到 而形成早晶石夕薄獏。 /门刀剖 措由上述構造，^Γ ^_、 、， 作成於丽述所貼合之單晶矽薄 於以CVD等堆穑夕夕曰 干日日y尋膜，亚且Flying ions, cutting step, M is cut into a shape covering the area of the above-mentioned _ μ $ μ 子 的 早 晶石 夕 片 1 hurt Jiang Yi. +, + Xj removal; the close bonding step is to cut off the description Single / private, attached to the aforementioned money and removed: two V implanted gas ion side surfaces are tightly adhered to each other, and a single crystal silicon thin film formation step is performed. _ However, it is difficult, that is to say * a hunting is caused by the embrittlement of other lice and the aforementioned single crystal silicon wafer is divided to form a presparite slab. The single-crystal silicon bonded by Yu Lishu is thinner than CVD, such as CVD, etc.

A板時，传於二夕日日矽薄膜上亦一併形成電晶體之S0I 二「/…述貼合前，先蝕刻除去包含該貼合區域之 預定區域之多晶石々爲、， 匕9之 夕㈢，亚且蝕刻除去相同區域之前述_ #i 化矽膜在厚度方向之一部分。 迩一虱 口 b T獲柃貼合有單晶矽薄膜之區域與多晶矽薄膜 區域大致相等高度之S0I基板。因而可於前述單晶梦薄膜之 區域與多晶梦薄膜之七 /潯胰之區域同時處理包含島狀蝕刻之以 部分的步驟。此外，帘孑卩比& , & 交 曰 匕外形成階差小之電晶體及電路，如為液 晶面板時，單元厚度控制性佳。 此外為求達成上述目㈤，本發明之半導體裝置之特徵 為：係於絕緣基板上，多晶石夕薄膜與單晶石夕薄膜形成於各 不相同的區域’且上述絕緣基板與上述單晶石夕薄膜經規格 化之線膨脹差異’大致於室溫以上，咖。c以下之溫度範圍 内’約在250 ppm以下。 通常形成高性能之裝置時成為障礙之因多晶石夕内特有之 結晶性不完全性引起之間隙内之局部位準、結晶粒場附近 之缺陷及間隙内存在局部位準導致移動率降低及s係數（次 -20- (16)200306002 發明說明續頁 可藉由將用作活性層之半導體薄 臨限值係數）增加等問題 膜形成單晶矽來消除。 因此，藉由上述構造，在大型之玻璃基板等絕緣基板上 ’多晶矽薄膜與單晶矽薄膜係形成於各不相同之區域。因 此’可於單晶⑦薄膜之形成區域形成要求更高性能之裝置 ，如時間控制器及微處理器1，而於多晶矽薄膜之形成區 域形成其餘之裝置。In the case of the A-plate, the S0I of the transistor was also formed on the silicon film on the second day. Before the bonding, the polycrystalline stone containing the predetermined region including the bonding region is etched and removed. On the evening, the aforementioned _ #i part of the silicon film in the same direction is etched to remove a part of the thickness direction. A single hole is obtained, and the area where the monocrystalline silicon film is bonded and the polycrystalline silicon film area are approximately equal in height. The substrate. Therefore, it is possible to simultaneously process the steps including island-like etching in the region of the single crystal dream film and the region of the polycrystalline dream film 7 / pancreas. In addition, the curtain ratio is &, & In the case of a transistor and a circuit with a small step outside, the thickness of the cell is good when it is a liquid crystal panel. In addition, in order to achieve the above purpose, the semiconductor device of the present invention is characterized in that it is attached to an insulating substrate and polycrystalline silicon The thin film and the single crystal thin film are formed in different regions', and the normalized linear expansion difference between the above-mentioned insulating substrate and the single crystal thin film is approximately 'above room temperature, and within a temperature range below c.' At 250 ppm ．Usually it becomes a barrier when forming high-performance devices. Local levels in the gap, defects near the crystal grain field, and local levels in the gap caused by the incompleteness of the crystallinity specific to the polycrystalline stone, reduce the mobility. And s-coefficient (sub-20- (16) 200306002 Description of the Invention Continued pages can be eliminated by forming a single-crystal silicon film by increasing the thin film threshold factor of the semiconductor used as the active layer). Therefore, with the above structure, On large glass substrates such as 'polycrystalline silicon films and monocrystalline silicon films are formed in different areas. Therefore,' high-performance devices such as time controllers and The microprocessor 1 forms the remaining devices in the formation region of the polycrystalline silicon film.

亦即，即使單晶石夕薄膜之尺寸有限，只須為於形成要求 單晶矽必要之高速性、耗電及變動之高速邏輯、時間產生 器、高速之DAC(電流緩衝器）等時之足夠尺寸即可。因此 可在基板上一體積體化僅以單晶矽即可實現之高性能、高 功旎之電路系統，因此與以單晶矽形成全部裝置時比較， 可以非常低的成本製造積體化高性能系統之液晶面板或有 機EL面板等顯示裝置用之半導體裝置。That is, even if the size of the monocrystalline silicon film is limited, it is only necessary to form high-speed logic, time generator, high-speed DAC (current buffer), etc., which requires the high-speed, power consumption, and fluctuation required for single-crystal silicon. Enough size. Therefore, a high-performance, high-power circuit system that can be realized only with single crystal silicon can be integrated on a single substrate. Therefore, compared with the case where all devices are formed with single crystal silicon, the integrated circuit can be manufactured at a very low cost. Semiconductor devices for display systems such as liquid crystal panels or organic EL panels in performance systems.

此外，單晶矽之基板形狀雖限定於LSI製造裝置之晶圓尺 寸之6, 8, 12吋之圓板，但由於在基板上亦形成多晶矽薄膜 ’因此亦可製造如大型之液晶顯示面板及有機EL面板。 再者，無須為求防止因與石英基板之熱膨脹係數差異所 實施之加熱接合強度提高步驟造成的破壞，而使用調整組 成之晶化玻璃。因而不存在晶化玻璃產生之鹼性金屬造成 污染的問題，且可防止因熱膨脹係數差異所實施之加熱接 合強度提高步驟造成的破壞。 此外，藉由絕緣基板與單晶矽薄膜之經規格化之線膨脹 差異，在大致室溫以上，600°C以下之溫度範圍内約在250 ^ 21 - (17) (17)200306002 發明說明續j ppm以下，施加於絕緣基板與單晶矽薄膜之應力小。因此 於絕緣基板上形成單晶矽薄膜之步驟中，可確實防止因熱 膨脹係數差異所實施之自氫植入位置劈開剝離步驟造成的 破壞及接合界面剝離，或於結晶中產生缺陷，並可促使加 熱接合強度提高。另外，此時所謂熱膨脹係指因溫度變化 引起之長度變化。 此外’為求達成上述目的’本發明之半導體裝置之特徵 為：係於絕緣基板上，多晶石夕薄膜與單晶石夕薄膜形成於各 不相同的區域’且上述單晶矽薄膜之喇曼峰值之偏差量在 519.5 cm]以上，且在5215 cm]以下。 藉由上述構造，⑨薄膜與單^薄耗形成於各不 t ^之f域。因此，可於單晶㈣膜之形成區域形成要求 ::能之裝置，如時間控制器及微處理器等，而於多晶 矽薄膜之形成區域形成其餘之裝置。 ::使用雷射進行晶化及結晶生長時，於係薄膜上殘留 大的應力。 實可使施加於單晶發薄膜…面的應力 二貝:'、、、令’因而單晶矽薄膜之喇曼峰值之偏差量在 >19.5 cnT1以上，且在 〗 碹每肽μ > .5 以下。因此形成TFT時，可 =止她加㈣界面之應力不均—及變動造成料 面固定電冇、尺而戈陷及隨伴產生界 特性r:I 準造成臨限值偏差及變動、及 特性穩定性降低等。 亦即’可於單晶矽薄膜之形成區域形成要求更高性能之 -22- (18) 2UUJ06002In addition, although the shape of the single-crystal silicon substrate is limited to 6, 8, 12-inch wafers of the wafer size of the LSI manufacturing device, since a polycrystalline silicon film is also formed on the substrate, it is also possible to manufacture large-scale liquid crystal display panels and Organic EL panel. Furthermore, it is not necessary to use a crystallized glass composed of adjustments in order to prevent damage caused by the step of increasing the thermal bonding strength due to the difference in thermal expansion coefficient from the quartz substrate. Therefore, there is no problem of contamination caused by the alkali metal generated by crystallized glass, and damage caused by the step of increasing the heat bonding strength due to the difference in thermal expansion coefficient can be prevented. In addition, the normalized linear expansion difference between the insulating substrate and the single crystal silicon film is approximately 250 ^ 21-(17) (17) 200306002 in the temperature range above approximately room temperature and below 600 ° C. Below j ppm, the stress applied to the insulating substrate and the single crystal silicon film is small. Therefore, in the step of forming a single-crystal silicon film on an insulating substrate, it is possible to surely prevent the damage caused by the splitting and peeling step from the hydrogen implantation position and the peeling of the bonding interface due to the difference in thermal expansion coefficient, or cause defects in the crystal and promote Heat bonding strength is improved. In this case, the thermal expansion refers to a change in length due to a change in temperature. Further, in order to achieve the above-mentioned object, the semiconductor device of the present invention is characterized in that: the polycrystalline silicon thin film and the single crystal thin film are formed in different regions on an insulating substrate; The deviation of the Mann peak is 519.5 cm] or more and 5215 cm] or less. With the above structure, the ytterbium thin film and the single thin film are formed in the f domains of each t ^. Therefore, it is possible to form required devices such as time controllers and microprocessors in the formation region of the monocrystalline silicon film, and to form the remaining devices in the formation region of the polycrystalline silicon film. :: When crystallization and crystal growth are performed by laser, a large stress remains on the thin film. In fact, the stress applied to the surface of the single crystal thin film can be made: ',,,', so the deviation of the Raman peak of the single crystal silicon film is > 19.5 cnT1 or more, and〗 碹 per peptide μ > .5 or less. Therefore, when forming a TFT, it is possible to stop the uneven stress on the interface—and the change caused by the fixed surface of the material, the ruler and the trapezoid and the accompanying boundary characteristics r: I will cause the threshold deviation and variation, and characteristics Reduced stability, etc. That is, ’which requires higher performance can be formed in the formation region of the single crystal silicon thin film -22- (18) 2UUJ06002

裝置，如日卑卩卩+ 成r形成::::置一 方法係在上述目的’本發明之半導體裝置之製造 特徵為勺=、.土板上形成有多晶石夕薄膜與單晶石夕薄膜，其 化石夕膜=s Ϊ積步驟，其係於絕緣基板表面依序堆積氧 非薄膜形成步驟，其係將上述 ;钱刻除：=: 夕層生長而形成多晶石夕薄膜 域.切斷牛7，/、純刻除去上述多晶㈣膜之特定區 域，切❹驟，其係將預先氧 面形成氧切膜，且呈1隹積乳化艇，於表 子之氫離子植入部之單特定濃度之氫離 :::活化，·接合步驟，其係將上述切斷之表 在至溫下使植入氫離子側之面密著土 ，接合上述兩基板；及單晶矽;：刻除去之區域 處理，以上述氫離子植入部為邊 、系措由熱 基板上形成單晶⑦薄膜。 ” “ ’於上述絕緣 藉由上述方法，藉由加熱於特 離子之單晶石夕基板，可提高接合強戶又植入特定濃度之氫 植入部為邊界來剝離單晶石夕基二二：=藉由以氯離子 可以單晶石夕消除於形成高性能之裝置時成為障礙：二 二嶋之結晶性不完全性引起之間隙内之局 二： 曰曰粒场附近之缺陷及間隙内存在局部位準導致移動率降: -23 - 200306002 (9) 發明IP月續頁 1--------- 及s係數增加等問題。因此，可於絕緣基板上形成單晶矽薄 膜與多晶矽薄膜，以後之步驟以共通之加工製程，可以單 晶矽形成要求更高性能之裝置，而以多晶矽形成其餘裝置 。因而可以低成本製造積體化高性能系統之液晶面板或有 機EL面板等顯示裝置等的半導體裝置等。 此外，由於係預先形成氧化矽膜，並經由其在玻璃基板 專、、、巴緣基板上接合單晶石夕基板，因此可防止因施加於接合 之石夕界面之應力造成矽結晶應變而引起之移動率降低，或 是界面之缺陷及隨伴其之界面固定電荷、界面之局部位準 造成之臨限值偏差、特性穩定性降低等。藉此，無須為求 防止因與石英基板之熱膨脹係數差異所實施之加熱接合強 度提南、剝離步驟造成的破壞，而使用調整組成之晶化玻 璃，而可使用高應變點玻璃。因而不存在晶化玻璃之鹼性 金屬造成污染的問題，可防止因熱膨脹係數差異所實施之 加熱接合強度提高、剝離步驟造成的破壞。 再者’如於大面積之高應變點玻璃基板上形成多晶矽膜 ’以覆蓋須接合加工成適切尺寸之單晶矽基板之區域的方 式預先餘刻除去多晶石夕薄膜，於該區域内接合單晶石夕基 板藉由剝讀保留單晶石夕薄膜與氧化石夕膜，並藉由剝離除 去以外之單晶矽，可消除整個玻璃基板的應力偏差，可獲 传基板之一部分區域包含單晶矽薄膜，其餘區域部分包含 多晶石夕薄膜之基板。 此外’單晶矽基板之形狀雖限定於LSI製造裝置之晶圓尺 寸之6, 8, 12吋的圓板，但是由於在絕緣基板上亦形成多晶 -24- (20) 200306002 發明說明續頁 ㈣膜，因此可製造如大型之液晶顯示面板及有機肛面板 寻半導體裝置。 此外，由於單晶矽基板係經由氧化矽膜，在室溫下接合 於絕緣基板卜因此可使施加於接合之矽界面的應：實質二 幾乎為零。因此，可更確實防止施加於界面之應力不均一 及變動造成石夕結晶應變而引起之移動率降低及變動，或只 面缺陷及隨伴產生界面固定電荷、界面之局部位準造成臨 限值偏差及變動、及特性穩定性降低等。 此外’為求達成上述目的’本發明之半導體裝置之 方法係在、I巴緣基板上形成有多晶石夕薄膜與單晶石夕薄膜，其 t徵為包含：堆積步驟，其係於絕緣基板表面依序堆積氧 !:::晶質石夕膜；多晶彻形成步驟，其係將上述 非曰曰貝石夕狀予以加熱，使多晶石夕層生長而形成多晶 胺钱刻除去步驟，其係钱刻除去特定區域之上述多晶石夕薄 並且㈣除去相同區域之上述氧化石夕膜在厚度方向之 斷步驟’其係將預先氧化表面或堆積’ 於f面形成氧化石夕膜’且具有在特定深度植入特定濃度之 :::::::植入部之單晶梦基板切割成覆蓋上述_ 化巧盆部分或大致全部區域的特定形狀，·活 =面係洗淨上述絕緣基板與單_基板，將 =在室:;舌:植接合步驟’其係將上述切斷之單晶石夕 兩基板；及單晶石夕薄膜形成步驟，其俜 错由熱處理，以前述上述氯離子植入部為邊界劈開剝離 -25- (21) (21)200306002 發明說明_胃 於土述絕緣基板上形成單晶矽薄膜。 藉由上述方法，除 刻除去特定區域之多日:^方法的優點之外，且由於钱 化石夕膜在厚产方㈣層’並錄刻除去相同區域之氧 附面側之氧==;Γ，因此可消除單晶梦基板之貼 晶石夕薄膜及多的影響，可獲得絕緣基板上之單 可同時處理Μ區域高度大致相等的基板。因而 此形成階差小之==後大部分的步驟。此外，藉 單元厚度控制性佳。 目而’如為液晶面板時， 方半r為求達成上述目的，本發明之半導體裝置之製造 特货爲勺ί緣基板上形成有多晶石夕薄膜與單晶石夕薄膜，其 二切：：·堆積步驟，其係於絕緣基板表面堆積氧化矽 面幵/驟’其係將預先氧化表面或堆積氧化膜，於表 =成2切膜，且具有在特定深度植人特定濃度之氯離 :之：料植入部之單晶石夕基板切割成特定形狀；活化步 係洗淨t述絕緣基板與單㈣基板，將該兩基板表 /:化’饴著接合步驟，其係將上述切斷之單晶矽基 f "至溫下使植人氫離子側之面密著接合於上述絕緣基 石夕膜側表面之特定位置；單晶石夕薄膜形成步驟， 二=㉟處理’以上述氫離子植入部為邊界劈開剝離， :上迷絕緣基板上形成單晶石夕薄膜；堆積步驟，其係於上 緣基板上依序堆積絕緣膜及非晶”U多晶石夕薄 =成步·驟，其係將上述非晶”膜予以加熱，使多晶石夕 層生長而形成多晶矽薄膜。 -26- (22) 200306002The device, such as the Japanese 卩 卩 卩 卩 + into r formation :::: set a method based on the above purpose 'The manufacturing characteristics of the semiconductor device of the present invention is spoon =, ... polycrystalline stone film and single crystal are formed on the soil plate In the thin film, the fossil evening film = s deposition step, which is a step of sequentially forming an oxygen non-thin film on the surface of the insulating substrate, which is the above; the money is carved out: =: the evening layer is grown to form a polycrystalline evening film domain .Cut cattle 7 /, purely remove specific areas of the polycrystalline osmium film, and cut it. It will form an oxygen cutting film on the oxygen surface in advance, and form a 1-volume emulsification boat. A single concentration of hydrogen ion at the entrance ::: activation, bonding step, which is to close the cut table to the surface of the implanted hydrogen ion side to the soil at a temperature to join the two substrates; and a single crystal Silicon: treatment of the area to be etched away, using the hydrogen ion implantation part as a side, to form a single-crystal gadolinium thin film on a hot substrate. "" In the above-mentioned insulation, by using the above-mentioned method, by heating the monocrystalline stone substrate with special ions, the bonding strength can be improved and a specific concentration of hydrogen implanted portion can be implanted as a boundary to strip the monocrystalline stone. : = By using chloride ions, single crystals can be eliminated and become obstacles in the formation of high-performance devices: the incompleteness of the gap caused by the incompleteness of the crystallinity of the two or two particles. Local level leads to lower mobile rate: -23-200306002 (9) Invention of IP Continuation Page 1 --------- and increase of s coefficient. Therefore, a monocrystalline silicon film and a polycrystalline silicon film can be formed on an insulating substrate, and the subsequent steps can be formed by a common processing process, and the monocrystalline silicon can be used to form a device requiring higher performance, and the polycrystalline silicon can be used to form the remaining devices. Therefore, semiconductor devices such as display devices such as liquid crystal panels or organic EL panels, which are integrated high-performance systems, can be manufactured at low cost. In addition, since a silicon oxide film is formed in advance, and a monocrystalline stone substrate is bonded to the glass substrate, the edge substrate, and the glass substrate, the silicon crystal strain caused by the stress applied to the bonded stone interface can be prevented. Reduced mobility, or defects in the interface and accompanying fixed charges on the interface, threshold deviations due to local levels of the interface, and reduced characteristic stability. Therefore, in order to prevent the damage caused by the thermal bonding strength and the peeling step due to the difference in thermal expansion coefficient between the quartz substrate and the substrate, it is not necessary to use a crystallized glass with an adjusted composition, but a high strain point glass can be used. Therefore, there is no problem of contamination caused by the alkali metal of crystallized glass, and it is possible to prevent the damage caused by the heat bonding strength improvement and the peeling step performed due to the difference in thermal expansion coefficient. Furthermore, 'if a polycrystalline silicon film is formed on a large-area high-strain-point glass substrate', the polycrystalline silicon thin film is removed in advance so as to cover a region to be bonded to a single-crystal silicon substrate of a suitable size, and bonded in this region. Single crystal substrates retain the single crystal films and oxide stone films by stripping, and remove the single crystal silicon except by stripping, which can eliminate the stress deviation of the entire glass substrate, and it can be obtained that a part of the substrate contains a single region. The crystalline silicon thin film, and the remaining areas partially include the substrate of the polycrystalline silicon thin film. In addition, although the shape of a single crystal silicon substrate is limited to a 6, 8, 12-inch circular plate of a wafer size of an LSI manufacturing device, polycrystalline -24 is also formed on an insulating substrate. (20) 200306002 Description of the Invention Continued Because of the thin film, semiconductor devices such as large liquid crystal display panels and organic anal panels can be manufactured. In addition, since the single-crystal silicon substrate is bonded to the insulating substrate at room temperature through the silicon oxide film, the application of the silicon interface to the bonding can be made to be substantially zero. Therefore, it is possible to more surely prevent the decrease and change of the mobility caused by the unevenness of the stress applied to the interface and the change in the crystal strain caused by Shi Xi, or only the surface defects caused by the surface defects and the accompanying fixed charges on the interface, and the threshold of the interface. Variations and variations, and reduced stability of characteristics. In addition, in order to achieve the above-mentioned object, the method of the semiconductor device of the present invention is to form a polycrystalline silicon thin film and a monocrystalline silicon thin film on a I-border substrate, and its t-sign includes the following steps: a stacking step, which is based on insulation Oxygen is sequentially deposited on the surface of the substrate! ::: crystalline stone film; polycrystalline formation step, which is to heat the above-mentioned non-shell stone shape, so that the polycrystalline stone layer grows to form a polycrystalline amine. The removing step is a step of removing the polycrystalline stone thinner in a specific area and removing the above-mentioned oxide stone thin film in the same area in the thickness direction. The step is to oxidize the surface or deposit in advance on the f-side to form an oxide stone. Evening film 'and has a specific concentration of implanted at a specific depth ::::::: The single crystal dream substrate of the implanted part is cut into a specific shape covering a part or almost all of the above-mentioned chemistry bowl, · live = noodle system Wash the above-mentioned insulating substrate and single-substrate, and will = be in the room :; tongue: plant bonding step 'which is the two substrates of the monocrystalline stone cut above; and the step of forming the single-crystal thin film by heat treatment Cleave with the aforementioned chloride ion implantation part as a boundary Peeling -25- (21) (21) 200306002 Description of the Invention _ Stomach A single crystal silicon film is formed on the insulating substrate. By the above method, in addition to the removal of a specific area for many days: the advantages of the method ^, and because the money fossil evening film is in a thick production square layer, and the oxygen in the same area is recorded to remove the oxygen on the side of the surface ==; Γ, so the influence of the monocrystalline dream substrate and the mullite crystal film can be eliminated, and a single substrate on the insulating substrate can simultaneously process substrates with substantially equal heights in the M region. Therefore, this step forms a small step == most of the following steps. In addition, the controllability of the thickness of the borrow unit is good. In the case of a liquid crystal panel, in order to achieve the above-mentioned objective, the manufacturing special product of the semiconductor device of the present invention is a polycrystalline silicon film and a monocrystalline silicon film formed on the edge substrate. ：： · Stacking step, which is to deposit silicon oxide surface on the surface of the insulating substrate. It is to oxidize the surface or deposit the oxide film in advance, and form a two-cut film on the surface, and implant a specific concentration of chlorine at a specific depth. From :: Cut the monocrystalline substrate in the material implantation part into a specific shape; the activation step is to clean the insulating substrate and the single substrate, and then the two substrates are bonded to each other, and it is The above-mentioned cut single-crystal silicon substrate f " tightly joints the surface of the hydrogen ion-implanting side to a specific position on the side surface of the above-mentioned insulating substrate film at a temperature; the step of forming the single-crystal silicon film, and two = ㉟ treatment ' Using the above-mentioned hydrogen ion implantation part as a boundary to split and peel, a single crystal thin film is formed on the insulating substrate; and a stacking step is to sequentially deposit an insulating film and an amorphous "U polycrystalline thin film" on the upper substrate. = Step · Step, which is to heat the above-mentioned amorphous film The polycrystalline silicon layer is grown to form a polycrystalline silicon thin film. -26- (22) 200306002

上述方法可獲得與上述各製造方法相同之優點。 L為求達成上述目的，本發明之半導體裝置之製 特徵為勺'•巴緣基板上形成有多晶矽薄膜與單晶矽薄膜，其 膜·堆積步驟’其係於絕緣基板表面堆積氧化石夕 膜二 =去步驟，其係餘刻除去特定區域之上述 方向之一部分；切斷步驟，其係將預先氧化表面 於f面形成氧切膜，且具有在特定深: 成牵墓/辰又之虱雔子之風離子植入部之單晶矽基板切割 2=刻除去區域之-部分或大致全部區域之特定 將兮兩u r驟，其係洗淨上述絕緣基板與單晶矽基板’ 板表面予以活化；密著接合步驟，其係將上述切 =㈣基板之植人氫離子側之面，在室 ::述_除去區域；單晶㈣膜形成步驟，其係藉 =胺以上述氫離子植人部為邊界劈開剝離，而形成單晶、 = 步驟，其係於上述絕緣基板上依序堆積絕緣 膜；及多晶石夕薄膜形成步驟，其係將上述非 曰曰：：版予以加熱，使多晶石夕層生長而形成多晶石夕薄膜。 猎由上述方法可獲得與上述各製造方法相同之優點。 方t:;在成上述目的，本發明之半導體裝置之製造 特徵為包含:堆積步:成::::=晶伽，其 卜 〃’、、、、、巴緣基板表面依序堆積第 :氧切膜、非晶質”及第二氧㈣膜，·露出步驟，、其 糸蝕刻除去上述第二氧化發膜之特定 她一部分露出，·自旋塗敷步驟，其係少二二： -27- (23) 200306002 淹敷二Γ非晶質矽膜而形成氧化膜，於該氧化膜上自旋 液；多晶石夕薄膜形成步驟，其係將上述非 之:晶梦^加熱’使藉由金屬協助而促進結晶生長方向 去 ^長’而形成多晶矽薄膜；除去步.驟’其係除 这弟一氧化矽膜與上述氧化膜；蝕 :=::r 一區域，步=係= ==度植人特定濃度之氫離子之氫離子植人部之單 矽基板切割成覆蓋上述蝕刻除去區域之— 區域之特定形狀；活化步驟，1係刀2王部 晶-基板，將該兩基板表面予::活化基:與單 著於上溫下使植入氫離子侧之面密 耆於上述蝕刻除去區域’接合上述 形成步驟，其係藉由熱處理，以上述氯離子 劈開剝離，於上述絕緣基板上形成單晶矽薄膜。’丨 藉由上述方法可獲得與上述各製造方法相同之優點。 充ΐ::之其他㈣、特徵及優點，於以下所示内容即可 中：可:瞭此外’本發明之利益，於參照附圖之以下說明 實施方式 [第一種實施形態] 矩陣基板20，依據圖 由··絕緣基板1、氧化 就本發明一種實施例之TFT之主動 1 (h)說明如下。 半導體裝置之主動矩陣基板2〇係藉 -28- 200306002 (24) 發明說明續頁 矽（Si〇2)膜2及11、多晶矽薄膜4、單晶矽薄膜5、閘極氧化 膜6、閘極21、層間絕緣膜22、及金屬配線24構成。 I巴緣基板1係使用高應變點玻璃之c〇ning公司之# 1737 (鹼土六員-鋁硼矽酸玻璃），不過亦可為高應變點玻璃之鋇_ 鋁硼矽酸玻璃、鹼土類_鋁硼矽酸玻璃、硼矽酸玻璃、鹼土 類-鋅-鉛-鋁硼矽酸玻璃、鹼土類_鋅_鋁硼矽酸玻璃等。 於整個絕緣基板1之表面形成有膜厚約200 nm之氧化矽 膜2。 於/邑緣基板1表面上之氧化矽膜2上，膜厚約5〇11111之多晶 石夕薄膜4形成於島狀圖案區域内。並於與多晶石夕薄膜*區域 不同之區域中，於絕緣基板丨表面上之氧化矽膜2上，膜厚 約200 nm之氧化矽膜u以及於其上同形狀之膜厚約5〇、nm 之單晶矽薄膜5接合於島狀圖案之區域。多晶矽薄膜4之區 域與單晶矽薄膜5之區域至少分離〇·3微米，$宜分離〇·5微 米以上。藉此防止於後述之多晶矽薄膜4之製造步驟中使用 鎳鉑锡、絶等金屬原子擴散於單晶石夕區域，促進特 性穩定化。 “於整個氧化矽膜2、多晶矽薄膜4及單晶矽薄膜5上形成有 膜厚約60 nm之閘極氧化膜6。 多晶矽薄膜4及單晶矽薄膜5之各島狀圖案區域上面之閘 極氧化膜6上，形成有包含多晶矽、矽化物或聚化2 (polycide)等之閘極 21。The above method can obtain the same advantages as the above-mentioned respective manufacturing methods. In order to achieve the above-mentioned object, the semiconductor device of the present invention is characterized in that a polysilicon film and a single-crystal silicon film are formed on a rim substrate, and the film deposition step is a process of depositing an oxide oxide film on the surface of an insulating substrate. Two = go step, which removes a part of the above direction in a specific area in a short time; cutting step, which will oxidize the surface in advance to form an oxygen cutting film on the f surface, and have a certain depth: into a grave / Chenyou lice Single crystal silicon substrate cutting of the wind ion implantation part of the cripple 2 = partial or almost all of the specific area of the region to be removed is to be cleaned, which is to clean the surface of the above-mentioned insulating substrate and the single crystal silicon substrate. Activation; close bonding step, which cuts the surface of the hydrogen ion-implanted side of the substrate, in the chamber :: __ removed area; the step of forming a single-crystal europium film, which uses an amine to implant the hydrogen ion The human body is split and peeled for the boundary to form a single crystal, which is a step of sequentially depositing an insulating film on the above-mentioned insulating substrate; and a step of forming a polycrystalline silicon film, which is to heat the above-mentioned non- :: plate, Growing polycrystalline A polycrystalline stone thin film is formed. By the method described above, the same advantages as those of the respective manufacturing methods can be obtained. Square t :; In order to achieve the above-mentioned purpose, the manufacturing characteristics of the semiconductor device of the present invention include: a stacking step: a :::: == crystal, which is sequentially stacked on the surface of the edge substrate: Oxygen-cutting film, amorphous "and second oxygen film, exposure step, which exposes a part of the second oxide film by etching, and spin coating step, which is two or two less:- 27- (23) 200306002 Submerging the two Γ amorphous silicon film to form an oxide film, and spin solution on the oxide film; the step of forming a polycrystalline silicon thin film is to heat the above-mentioned non-: crystalline dream ^ heating With the help of metal, the crystal growth direction is promoted to grow to form a polycrystalline silicon thin film; the step of removing is the step of removing the silicon oxide film and the above oxide film; etching: = :: r a region, step = system = The single silicon substrate of the hydrogen ion implantation part implanted with a specific concentration of hydrogen ions is cut into a specific shape covering the above-mentioned etching-removed area; the activation step, 1 series of knives and 2 king section crystals-the substrate, the two The surface of the substrate :: Activating group: Closely contact the surface of the implanted hydrogen ion side with the above etching at the upper temperature The removed region is bonded to the above-mentioned formation step, which forms a single-crystal silicon thin film on the above-mentioned insulating substrate by heat treatment and splitting and peeling with the above-mentioned chloride ions. The above-mentioned method can obtain the same advantages as the above-mentioned manufacturing methods. ΐ :: Other features, advantages, and advantages can be included in the following: OK: In addition, the benefits of the present invention will be described below with reference to the drawings. [First Embodiment] Matrix substrate 20, The active substrate 1 (h) of the TFT according to an embodiment of the present invention is described below by the insulating substrate 1 and the oxide according to the figure. The active matrix substrate 20 of a semiconductor device is borrowed from -28- 200306002 (24) Description of the invention continued on silicon ( (SiO2) Films 2 and 11, polycrystalline silicon thin film 4, single crystal silicon thin film 5, gate oxide film 6, gate 21, interlayer insulating film 22, and metal wiring 24. I edge substrate 1 uses a high strain point Glass # 1737 (Alkaline Earth Six-Aluminum Borosilicate Glass), but it can also be barium for high strain point glass _ aluminoborosilicate glass, alkaline earth _ aluminoborosilicate glass, borosilicate Glass, alkaline earth-zinc-lead-aluminum-borosilicate Glass, alkaline earth_zinc_aluminum borosilicate glass, etc. A silicon oxide film 2 having a film thickness of about 200 nm is formed on the entire surface of the insulating substrate 1. On the silicon oxide film 2 on the surface of the substrate 1 The polycrystalline silicon thin film 4 having a thickness of about 5011111 is formed in an island-like pattern region. In a region different from the polycrystalline silicon thin film * region, the silicon oxide film 2 on the surface of the insulating substrate A silicon oxide film u of about 200 nm and a monocrystalline silicon thin film 5 with a film thickness of about 50 nm in the same shape are bonded to the area of the island pattern. The area of the polycrystalline silicon film 4 and the area of the single crystal silicon film 5 are at least Separation is 0.3 microns, and separation should be above 0.5 microns. This prevents the use of nickel, platinum, tin, or other metal atoms in the manufacturing process of the polycrystalline silicon thin film 4 described later to diffuse into the monocrystalline region, and promotes stabilization of characteristics. "A gate oxide film 6 having a thickness of about 60 nm is formed on the entire silicon oxide film 2, the polycrystalline silicon film 4, and the single crystal silicon film 5. The gates on the island-like pattern areas of the polycrystalline silicon film 4 and the single crystal silicon film 5 A gate electrode 21 made of polycrystalline silicon, silicide, polycide, or the like is formed on the electrode oxide film 6.

斤再者，於形成有閘極21之整個閘極氧化膜6上形成有包含 氧化矽之層間絕緣膜22。但是層間絕緣膜22具有作為開Z -29- 200306002 v ^ 發明說明續頁 之接觸孔23(參照圖1(g))，該開口内形成有包含矽化鋁等金 屬之金屬配線24。金屬配線24自多晶矽薄膜4及單晶石夕薄膜 5之各島狀區域上面形成。 再者，主動矩陣基板20進一步於液晶顯示用上形成有 SlNx(氮化矽）、樹脂平坦化膜、連通孔、及透明電極，於 多晶石夕薄膜區域形成有驅動器及顯示部用之TFT，於單晶 石夕薄膜區域形成有藉由驅動器驅動之控制各時間之時間抑 制器。 、曰工 先前之形成於多晶矽區域之TFT的移動率約為1〇〇 cm2/v· sec (N通道），而該液晶顯示用主動矩陣基板2〇中，形成於單晶 矽區域之TFT則可獲得約5〇〇 cm2/v · sec(N通道）的移動率。 藉由該液晶顯示用主動矩陣基板2〇，驅動器原本形成於 ^晶矽薄膜4區域之裝置需要7〜8 v之訊號與電源電壓，但 疋形成於單晶矽薄膜5區域之裝置之時間控制器只須3V 即可穩定地動作。 ’ 、 、，另外，使單晶矽薄膜5之膜厚增加時，為5〇麵〜1〇〇請時 並無大的變化，但是辦$,丨Q Λ A 广^ 疋曰加到300 nm〜600 ，因通道部無 法完全耗盡化，因此斷開雷、、ώ y —间冤极逐漸增加，且S值（次臨限值 係數）變大。因此通道部雜命 丨雖14摻雜岔度相關，但是考慮對變 動之餘净谷’早晶薄膜5夕η替后v右上 守联）之肤厚須在500 nm以下，並宜在100 nm以下。 此外’該液晶顯示用主無 動矩陣基板20中，藉由電晶體形 成於多晶矽薄膜4區域|罩a访—+ 、 ”早日日矽溥膜5區域内，形成於各個 區域之同一導電型之雷曰触 屯日日肢之移動率、次臨限值係數、臨 -30- (26) 200306002 發明說明續ί _：_一^ 可因應必要之特性 由積體電路形成於 ，形成於各個區域 、電源電壓及邏輯 可因應必要之構造 〇 由積體電路形成於 ，形成於各個區域 則。此因，特別於 TFT特性之變動幾 影響，變動急遽地 。因而可因應加工Furthermore, an interlayer insulating film 22 containing silicon oxide is formed on the entire gate oxide film 6 on which the gate electrode 21 is formed. However, the interlayer insulating film 22 has a contact hole 23 (see FIG. 1 (g)) as an opening Z -29-200306002 v ^ Description of the Invention, and a metal wiring 24 containing a metal such as aluminum silicide is formed in the opening. The metal wiring 24 is formed on each of the island-like regions of the polycrystalline silicon thin film 4 and the monocrystalline silicon thin film 5. In addition, the active matrix substrate 20 is further formed with SlNx (silicon nitride), a resin planarization film, a communication hole, and a transparent electrode on a liquid crystal display, and a driver and a display TFT are formed in a polycrystalline silicon film region. A time suppressor that controls each time by a driver is formed in the monocrystalline stone film area. The mobility of the TFT previously formed in the polycrystalline silicon region was about 100 cm2 / v · sec (N channels), while in the active matrix substrate 20 for the liquid crystal display, the TFT formed in the monocrystalline silicon region was A mobility of about 500 cm2 / v · sec (N channels) can be obtained. With the active matrix substrate 20 for liquid crystal display, the device originally formed in the 4 region of the crystalline silicon film requires a signal of 7 to 8 V and the power supply voltage, but the time control of the device formed in the 5 region of the monocrystalline silicon film It only needs 3V for stable operation. In addition, when the film thickness of the single-crystal silicon thin film 5 is increased, there is no major change from 50 to 100, but it is increased to 300 nm, and Q is added to 300 nm. ~ 600, because the channel can not be completely depleted, so the number of disconnected thunder, y, y, and y are gradually increased, and the S value (sub-threshold value coefficient) becomes larger. Therefore, although the mismatch of the channel part 丨 is related to the 14-doped bifurcation, it is necessary to consider the net thickness of the valley valley (early-crystal film early after 5th η replacement and v-upper right). The skin thickness must be less than 500 nm, and preferably 100 nm. the following. In addition, in the main passive matrix substrate 20 for liquid crystal display, a transistor is formed in the polycrystalline silicon thin film 4 area | cover | Lei Yue, the movement rate of the limbs, the sub-threshold value coefficient, Lin-30- (26) 200306002 Description of the invention continued _: _ 一 ^ Can be formed by integrated circuits according to necessary characteristics, formed in various areas The power supply voltage and logic can be constructed according to the necessary structure. It is formed by integrated circuits and is formed in various areas. This is particularly affected by changes in the characteristics of TFTs, which changes rapidly. Therefore, it can respond to processing.

限值中之至少一個於各區域 砜不冋。因而 而形成於適合電晶體的區域内。 该液晶顯示用主動矩陣基板2〇中，藉 多晶矽薄膜4區域與單晶矽薄膜5區域; 之積體電路之閘長、閘極氧化膜之膜厚 位準中之至少一個於各區域不同。因: 及特性而形成於適合積體電路的區域内 該液晶顯示用主動矩陣基板2〇中，藉 多晶矽薄膦4區域與單晶矽薄膜5區域; 之積體電路可適用各區域不同之加工原 短之通道長時，單晶部分無結晶粒場， 乎不增加，而多晶部分受到結晶粒場之 增加，因此各個部分需要改變加工原則 原則形成於適合積體電路的區域内。At least one of the limits is in each area. Therefore, it is formed in a region suitable for a transistor. In the active matrix substrate 20 for liquid crystal display, at least one of the gate length of the integrated circuit and the film thickness level of the gate oxide film of the integrated circuit is different from each region by using the polycrystalline silicon film 4 region and the single crystal silicon film 5 region. Due to: and characteristics, formed in the area suitable for integrated circuits in the active matrix substrate 20 for liquid crystal display, the polycrystalline silicon thin phosphine 4 area and the single crystal silicon thin film 5 area are used; the integrated circuit can be applied to different processing in each area When the original short channel is long, there is no crystal grain field in the single crystal part, and it does not increase, while the polycrystalline part is subject to the increase of the crystal grain field. Therefore, the processing principle of each part needs to be changed to form the area suitable for the integrated circuit.

壯另外本务明可獲得之單晶矽區域尺寸雖受限於LSI製造 裝置之晶圓尺寸，不過只須為於形成要求單晶矽必要之高 速性、耗電及變動之高速邏輯、時間產生器、高速之dac (電流緩衝器）等時之足夠尺寸即可。 就以上σ兒明之主動矩陣基板2 〇之製造方法，依據圖1 (&)〜 圖Uh)說明如下。 首先’絕緣基板1係使用高應變點玻璃之coning公司之 # 173 7(鹼土類-鋁硼矽酸玻璃），在其整個表面上，使用石夕 烧（S1H4)與一氧化二氮（Να)之混合氣體，藉由電漿化學汽 相生長（Chemical Vapor Deposition ’ 以下稱 CVD)，如圖 1 (a) -31 - (27) (27)200306002 _說明續頁 所示’堆積膜厚約200 nm之氧化矽膜2。進一步於其整個表 面上，使用矽烷氣體，藉由電漿CVD，如圖丨（a)所示，堆 積膜厚約50 nm之非晶質矽膜3。 於前述非晶質矽膜3上照射準分子雷射予以加熱晶化，使 多晶矽層生長’而形成多晶矽薄膜4。另外，對非晶質矽膜 3之加熱並不限定於藉由準分子雷射之照射加熱，如亦可藉 由其他雷射照射加熱，亦可為使用爐之加熱。此外，為^ 促進結晶生長，亦可於非晶質矽膜3内添加鎳、翻、錫’:鈀 中之至少一種。 如圖1⑻所示，蝕刻除去多晶矽薄膜4之特定區域。 其次，準備預先藉由氧化表面或堆疊氧化膜（氧化石夕 :形=膜丨約200 nm之氧化矽膜u ’具有以特定能量植入 10 /cm以上’此處為5xlQl6/em2劑量之氫離子之氣離子 植二區域12之摻雜有3xlQl5em.3之狀單晶石夕基板1〇。藉由 切剎等將该早晶矽基板1〇切斷成比蝕刻除去多晶矽薄膜4 之特疋區域之形狀至少小〇·3微米，尤宜為小0.5微 的 形狀。 j 成有多晶矽薄膜4之基板及單晶矽基板10之 :基板後，如圖1(c)所示’使切斷之單晶石夕基板10之接近 =氣離子植人區域12側之表面密著貼合於前述蚀刻除去 區域。所謂s。1洗淨，係-般稱為崎淨的一種洗淨法 ，並使用包含氨、過氧化氮與純水之洗淨液。 而後，以30(rc〜6〇。 理，藉由雷射照人 約5贼之溫度進行熱處 、〆匕έ約700 ς以上峰值溫度之燈退火， •32- (28) (28)200306002 發明說朋續頁 使單晶石夕基板1 〇之氫離 飞離子植入區域12的溫度昇溫至氫自矽 版離之度以上，以 <奇雜2 & ^ α 辽離子植入區域12為邊界剝離單晶矽 暴板1 0。 蝕二等：性電漿蝕刻或濕式蝕刻，此處為緩衝氟酸之濕式 J \猎由約lOiim輕微餘刻除去經剝離而殘留於絕緣基板 上之單晶矽基板表面之損傷層。 错此/如圖1⑷所示，於絕緣基板1上分別獲得膜厚約50 :之夕晶矽薄膜4與單晶石夕薄臈5。另外，在室溫下接合單 =基板U)後，以期〜35Gt，約3Q分鐘熱處理後，以約峨 熱處理而剝離時隨剝離之剝落減少。 以約80(TC進行i分鐘燈退火。其次，保留構成裝 置之活性區域的部分，《由钱刻除去不需要之石夕薄膜4, 5 ’如圖1(e)所示，獲得島狀圖案。 其次，使用TEOS(四乙氧基㈣，亦即Si(〇c2H山）盘氧 之混合氣體’藉由電漿CVD，堆積膜厚約350 nm之氧化石夕 \以異方性敍刻之RIE予以回鍅約.㈣後，使用石夕貌與 -乳化二氮之混合氣體，藉由電漿CVD，如圖i⑴所示，形 成膜厚約60 nm之第二氧㈣膜6,作為閘極氧化膜卜 此時’藉由使前述第一氧化石夕膜圖案與前述單晶矽薄膜 圖案間之空間大致等於前述第一氧化矽膜厚之兩倍，於前 述多晶梦薄膜與前述單晶碎薄膜圖案間之溝狀部内保留氧 化膜，整個基板予以平坦化。 而後，藉由一般熟知之p-石夕（多晶石夕）形TFT矩陣基板之形 成製程相同的製程形成即可。亦即，々口刚所示，形成 -33- 200306002 ㈣ 包含多晶矽、矽化物或聚化物等之閘極21後，植入p+&B + 離子，堆積氧化矽膜（層間絕緣膜）22，開設接觸孔23。而 後，如圖1(h)所示，於接觸孔23内形成金屬（矽化鋁）配線24。 另外，將形成於絕緣基板1之單晶矽薄膜5與多晶矽薄膜4 予以餘刻圖案化成島狀而形成M〇s電晶體，n型MOS電晶 體及P型MOS電晶體之源極及汲極區域之至少一部分内植 入約l〇15/cm2以上之P +離子。藉此，繼續藉由RTA、雷射、 爐等進行加熱處理，除多晶矽薄膜4區域外，單晶矽薄膜5 區域亦同％藉由除去金屬原子，可獲得特性變動小而特性 穩定之TFT。 於液晶顯示用上進一步依序形成SiNx(氮化矽）、樹脂平坦 =膜、連通孔、及透明電極，於多晶矽薄膜4區域形成驅動 裔及顯不部用之TFT，於單晶矽薄膜5區域形成時間控制器。 此外，本實施形態增加氫離子之植入能量，加深氫原子 =峰值位置，增加單晶矽薄膜5之膜厚時，為5〇nm〜i〇〇nm 日守並無大的變化，但是增加到300 nm〜600 nm時，丁打之s 值逐漸變大且斷開電流顯著增加。因此，即使單晶矽薄膜5 之膜厚亦與雜質之摻雜密度相關，仍須在約600 nm以下， 且且在約500 nm以下，更宜在1〇〇11111以下。 〔第二種實施形態〕 就本發明其他實施例之TFT之主動矩陣基板30，依據圖 ()況月如下。另外與第一種實施形態之主動矩陣基板2 〇 相同的構件省略說明。 半導體裝置之主動矩陣基板30係藉由：絕緣基板1、氧化 -34- (30) (30)200306002 發明說明續頁 矽（S:i〇2)膜32及11、第二氧化矽膜3S、多晶矽薄膜37、單晶 矽薄膜34、閘極氧化膜38、閘極21、層間絕緣膜22、及金 屬配線2 4構成。 絕緣基板1係使用高應變點玻璃之c〇NING公司之#丨737 (鹼土類-鋁硼矽酸玻璃）。 於整個絕緣基板1之表面形成有膜厚約35〇 nm2氧化矽 膜32。 於絕緣基板1表面上之氧化矽膜32上，膜厚約1〇〇11111之第 一氧化矽膜35與膜厚約5〇 nm之多晶矽薄膜37堆疊形成於 島狀圖案區域内。 再者與夕曰曰矽薄膜3 7不同之區域中，絕緣基板丨表面之 氧化矽膜32上形成有具有約15〇 nm深度之凹部33(參照圖 2(a))。該凹部33之底面上，膜厚約2〇〇 之氧化矽膜η以 及於其上同形狀之膜厚約50 nm之單晶矽薄膜34形成於島 狀圖案之區域。多晶矽薄膜37之區域與單晶矽薄膜34之區 域至少分離〇·3微米，尤宜分離〇·5微米以上。藉此防止鎳、 鉑、錫、鈀等金屬原子擴散於單晶矽區域，促進特性穩定 化。 〜 、於整個氧化矽膜32、多晶矽薄膜37及單晶矽薄膜W上形 成有膜厚約6〇 nm之閘極氧化膜36。 、夕曰曰矽薄膜37及單晶矽薄膜34之各島狀圖案區域上面形 成有包含多晶矽、矽化物或聚化物等之閘極2 i。 再者，與主動矩陣基板30同樣地，形成有層間絕緣膜U 、接觸孔23(參照圖2(g))、及金屬配線24。此外，亦同樣地 -35- (31) (31)200306002 發明說日描賣頁 ，主動矩陣基板30於液晶顯示用上形成有咖（氮化石夕）、 樹脂平坦化膜、連通孔、及透明電極，於多晶石夕薄膜區域 形成有驅動器及顯示部用之TFT，於單晶石夕薄膜 有時間控制器。 x 先前之形成於多晶石夕區域之TFT的移動率約為l〇〇cm2/v.sec ’而該液晶顯示用主動矩陣基板3G中，形成於單晶石夕區域 之N通道TFT則可獲得約5〇〇cm2/v· 的移動率。 藉由該液晶顯示用主動矩陣基板3G，驅動器原本形成於 多晶矽薄膜37區域之裝置需要7〜8V之訊號與電源電壓，作 是形成於單晶㈣膜34區域之裝置之時間控制器只須3.3 v 即可穩定地動作。 就以上說明之主動矩陣基板3〇之製造方法，依據圖2⑷〜 圖2(h)說明如下。 絕緣基板i係使用C0NING公司之# 1737(驗土類-銘石朋石夕 酸玻璃），在其整個表面上，使用石夕烧與―氧化二氮之混合 氣體，藉一由電槳CVD堆積膜厚約35〇 _之氧化石夕膜32。如 圖2(a)所不，蝕刻約15〇 nm之前述氧化矽膜”之特定區域 而形成凹部3 3。 / 其-人’準備預先藉由氧化表面或堆積氧化膜而形成膜厚 約2〇〇謂之氧化石夕，具有以特定能量植入有5χΐ〇ΐ6_2 劑量之氫離子之氫離子植人區域12之單㈣基板ι〇。切斷 成比形成前述凹部33之區域相同形狀至少小〇5微米的形 狀。 SC-1洗淨形成前述凹部33之絕緣基板丨及切斷之單晶矽 -36- 200306002 { } 發明說明續頁 基板ίο之兩基板後，如圖2(b)所示，使前述氫離子植入侧 表面密著貼合於前述蝕刻除去區域。 而後，以30(TC〜600t;，此處以約55(Γ(：2溫度進行熱處 理，藉由雷射照射或包含約70(rc以上峰值溫度之燈退火， 使單晶矽基板10之氫離子植入區域12的溫度昇溫至氫自矽 脫離之溫度以上’以氯離子植入區域12為邊界剝離 基板10。 此處為緩衝氟酸之濕式 以等方性電漿蝕刻或濕式蝕刻 蝕刻，f由約10 nm輕微蝕刻除去經剝離而殘留於絕緣基板 1上之單晶矽基板表面之損傷層。藉此，如圖2(c)所示，於 絕緣基板1上獲得膜厚約5〇 nm之單晶矽薄膜34。 而後，於整個絕緣基板丨上，使用矽烷與一氧化二氮之混 合氣體，藉*電漿CVD，如圖2⑷所* ,堆積膜厚約ι〇〇謹 之f二氧切膜35。進-步於其整個表面上使㈣烧氣體 藉由電漿CVD，如圖2⑷所示，堆積膜厚約5〇 nm之非晶 質矽膜3 6。 非晶質矽膜36上照射準分子雷射予以加熱晶化，使多晶 石夕層生長二而形成多晶㈣膜37,並且促近接和強度提高。 人藉由钱刻除去多晶石夕薄膜3 7之不需要部分與第二 乳切膜35之至少單晶％薄膜34上之部分。其次，保留構 成裝置之活性區域的部分，#由蝕刻除去不需要之矽膜， 如圖2(e)所示，獲得島狀圖案。 人，使用TEOS與氧之混合氣體，藉由電漿CVD，堆積 膜厚約350 nm之氧化矽膜，以異方性蝕刻之rie予以回蝕約 •37- (33) (33)200306002 發明說明續頁 4〇〇 nm後，使用矽烷與一氧化二氮之混合氣體，藉由電嚷 CVD，如圖2⑴所示，形成膜厚約6〇 nm之氧化石夕膜 為閘極氧化膜38。此時，藉由使前述第一氧化矽薄膜圖案 與前述單晶矽薄膜圖案間之空間大致等於前述第一氧彳σ匕矽 膜厚之兩倍，於前述多晶矽薄膜與前述島狀蝕刻前之單晶 矽薄膜圖案間之溝狀部内保留氧化膜，整個基板予以平= 以後，與第一種實施形態相同，因此省略。 〔弟二種實施形態〕 就本發明其他實施例之TFT之主動矩陣基板說明時，因剖 面構造與第一種實施形態之主動矩陣基板2〇相同，因此僅 說明差異處。 本實施形態之多晶矽薄膜43(參照圖3(d))係藉由結晶生 長方向一致之多晶矽之所謂連續結晶粒場矽（C〇ntlnuous Grain Silicon)形成。 先鈾之形成於連續結晶粒場石夕區域之N通道τ f τ的移動 率約為200 cm2/V · sec，而該液晶顯示用主動矩陣基板中 ’形成於單晶矽區域之N通道TFT則可獲得約5〇〇 cm2/v· sec 的移動率。 藉由該液晶顯示用主動矩陣基板，驅動器原本形成於多 晶石夕薄膜43區域之裝置需要7〜8 v之訊號與電源電壓，但是 形成於單晶矽薄膜5區域之裝置之時間控制器只須3 · 3 V即 可穩定地動作。 就以上說明之主動矩陣基板之製造方法，依據圖3(a)〜圖 -38 - (34) (34)200306002 發明說明續頁 3(d)說明如下。 本發明第三種實施例與第一種實施例同樣地，首先，絕 緣基板1係使用c〇NING公司之# 1737(鹼土類_鋁硼矽酸玻 璃）’在其整個表面上，使用矽烷與一氧化二氮之混合氣體 ，藉由電漿CVD堆積膜厚約200 nm之氧化矽膜2。在且整個 表面上使用石夕院氣體’藉由電漿CVD，堆積約5〇麵之非晶 質石夕膜3。進—步如圖3⑷所示，在其整個表面上使用石夕烧 與：氧化二氮混合氣體’藉由電漿CVD堆積約麵之第 -一氧化梦膜4 1。 口邱笮層Γ" 4第一乳：矽膜4 1之特定區域内藉由蝕刻形成開 二，為求控制前述開口部之非晶質石夕膜3表面的親水性 ’ ：：3广)所不’於非晶質石夕膜3表面形成薄的氧化石夕膜42 ’在其上自旋塗敷醋酸鎳水溶液。 曰Γΐ方ΓΤ溫度進行約12小時固態生長，使促進結 日日生長方向一致之結晶哇具 進-步除去多晶彻43上)之生第長二W晶彻43。 钱刻除去多晶石夕薄膜43之特定區=化石夕膜41及42。而後 其-人’準備預先藉由氧化田 約2〇〇nm之氧切mi，星有氧化膜而形成膜厚 劑量之氯離子之氯離子植入有之能量日植入有叫 單晶石夕基板1〇切斷成比餘刻除去夕曰早3曰石夕基板10。將該 的形狀至少小0.3微米，尤宜:;、〇;^ 似洗淨形成有前述多一薄膜形狀。 、、 之基板及單晶矽基板 -39- 200306002 1 ~ 發明說明續頁 兩基板後，如圖3(c)所示，使接近於單晶矽基板丨〇之 虱離子植入區域12之侧的表面密著貼合於前述蝕刻除去區 域。此時多晶矽薄膜43與單晶矽基板10之間至少分離〇·3微 =，尤宜分離0.5微米以上。藉此防止後述之多晶矽薄膜4 ‘ ie ν ‘中使用之錄、鈾、錫、把等金屬原子擴散至單晶 石夕區域，促進特性之穩定化。 而，以300 C〜600 C，此處以約55〇°C之溫度進行熱處 理，藉由雷射照射或包含約7〇〇。〇以上峰值溫度之燈退火， 使單晶石夕基板1〇之氮離子植入部12的溫度昇溫至氫自矽脫 離之服度以上，以氫離子植入部12為邊界剝離單晶矽基板 10。 以等4方性電漿姓刻或濕式姓刻，此處為緩衝氣酸之濕式 餘刻’口猎由約10 nm輕微餘刻除去經剝離而殘留於絕緣基板 1上之單晶矽基板10表面之損傷層。藉此，如圖3⑷所示， 於絕緣基板1上分別獲得膜厚約5G nm之多晶石夕薄膜43 晶矽薄膜5。 一 其次’藉由蝕刻除去多晶矽薄膜43之不需要部分與第二 乳化石夕膜之至少單晶石夕薄膜5上之部分。進一步因應特定之 裝置形狀，島狀地巍玄丨丨]^ 土夕a ^ Λ 蝕刻除去多晶矽溥膜43與單晶矽薄膜5 不需要的部分。其次’保留構成裝置之活性區域的部分、， 蝕刻除去不需要之矽膜，而獲得島狀圖案。 其次，使用TE0S舆氧之混合氣體，藉由電浆CVD，堆产 膜厚約350麵之氧切膜，以異方性㈣之RIE予以回 後，使用石夕院與一氧化二氮之混合氣體，藉由電雙 -40- (36) 200306002 發明說明續頁 =二成::約6，m之!化:夕膜(圖上未顯示)，作為閘 單晶矽薄膜圖宰稭：使刚述第一氧化矽薄膜圖案與前述 兩倍，於前^之空間大致等於前述第-氧切膜厚之 部内保留氧介日从日日夕溥膜圖案間之溝狀 成側壁以減少坡度。 —化或疋於階差部形 ，t:二t裝置之活性區域近旁的氧切膜上形成開口部 求除去將氧切膜作為掩模促進結晶生長而添加之錄 二入，度之p+離子(15 keV，5xl〇15/cm2) ’ 以 rta，在約 之咖度下進行丨分鐘之熱處理。其係以避免單晶矽中 鎳原子擴散之方式，物理性納人空間，*過極微量之錄原 子仍可能混入製程中，因此單晶矽之活性區域宜進行前述 除去步驟，但是優先空間時，亦可依設計上考慮省略除去 步驟。 以後之步驟，與第一種實施形態相同，因此省略。 〔第四種實施形態〕 本發明其他實施例之TFT之主動矩陣基板50與第一種實 施形態之主動矩陣基板20大致相同，因此僅說明差異處。 主動矩陣基板20之氧化石夕膜2之膜厚約為200 nm，而本實 施形態之主動矩陣基板50之氧化矽膜52之膜厚則約為35〇 nm ，並進一步形成有深度約150 nm之凹部55(參照圖4(b))。 此外，主動矩陣基板20之氧化矽膜11之膜厚約為2〇〇 nm ，而本實施形態之主動矩陣基板5〇之氧化矽膜6 1之膜厚則 約為400 nm。 -41- 200306002 κ } 發明說明續頁 ，刖之形成於多晶矽區域之Ν通道TFT的移動率約為1〇〇 cm /V · sec，而該液晶顯示用主動矩陣基板中，形成於 單晶矽區域之N通道TFT則可獲得約5〇〇 cm2/v· sec的移動 率 0 夕藉由該液晶顯示用主動矩陣基板5〇,驅動器原本形成於 =曰曰矽薄膜54區域之裝置需要7〜8 V之訊號與電源電壓，但 是形成於單晶矽薄膜55區域之裝置之時間控制器只須3·3 V 即可穩定地動作。 此外，本實施例係使用形成有約400 nm之氧化矽膜61的 單晶矽基板60，所獲得之TFT之臨限值的變動，與使用形 成有約200 nm之氧化矽膜n之單晶矽基板1〇之第一種實施 形恶4的0.3 V(土 〇)比較，為約1/2之〇15 v( ±(J )，特別是 於低電C k之動作穩定性提高。此因接合之單晶石夕基板與 玻璃基板界面之污染’或是晶格應變及不完全性引起之固 定電荷的影響減輕。前述氧切膜61之膜壓，於膜厚愈厚 ，臨限值之變動愈少，不過藉由氧化矽膜之形成步驟的效 率（氧化所需時間）與階差的折衷，適切值大致為2〇〇 nm〜400 nm。重視變動時，適切值大致為4〇〇 nm，重視階 差及效率時，適切值大致為2〇〇11111。 當然，階差不構成問題時，須大致在4〇〇 nm以上。 就以上說明之主動矩陣基板5〇之製造方法，依據圖4(幻〜 圖4(h)說明如下。 絕緣基板1係使用C0NING公司之# 1737(鹼土類_鋁硼矽 酉欠玻埚）在其整個表面上，使用石夕烧與一氧化二氮之混合 -42- 200306002 (3δ) 發明說明續頁 —-—-_ 氣體，藉由電漿CVD堆積膜厚約350 nm之氧化矽膜52。進 一步如圖4(a)所示’在其整個表面上使用矽烷氣體，藉由 電漿CVD堆積膜厚約50 nm之非晶質石夕膜53。 非日日貝石夕膜5 3上fl?、射準分子雷射予以加熱晶化，使多晶 矽層生長，而形成多晶矽薄膜54。 藉由約150 nm蝕刻除去特定區域之多晶矽薄膜54與氧化 矽膜52之一部分，如圖4(b)所示，形成深度約2〇〇 之 部55。 其次’準備預先藉由氧化表面或堆疊氧化膜而形成膜厚 約400 nm之氧化矽膜6丨，具有以特定能量植入有5 χ丨〇1 劑量之氫離子之氫離子植入部62之單晶矽基板6〇。 將單晶妙基板60分斷成比凹部55的形狀小〇.5微米的形 狀。 7 SC-1洗淨形成有多晶矽薄膜54之基板}及單晶矽基板⑼ 之兩基板後，如圖4(c)所示，使接近於單晶矽基板6〇之氫 離子植入部62之侧的表面密著貼合於凹部55之底面。 而後，以30CTC〜65CTC，此處以約55〇。(：之溫度進行熱處 理’藉由雷射照射或包含約70(rc以上峰值溫度之燈退火， 使單晶矽基板60之氫離子植入部62的溫度昇溫至氫自石夕脫 離之溫度以上，以氫離子植入部62為邊界剝離單晶矽基板 60 ° 以等方性電漿蝕刻或濕式蝕刻，此處為緩衝氟酸之濕式 蝕刻，藉由約10 nm輕微蝕刻除去經剝離而殘留於絕緣基板 1上之單晶石夕基板1 〇表面之損傷層。 -43- 200306002 (39) 發明訴明續頁 藉此，如圖4(d)所示，於絕緣基板丨上分別可獲得膜厚約 5 0 nm之多晶石夕薄膜5 4與單晶石夕薄膜5 5。 而後，在溫度約800°C下，進行}分鐘之燈退火。其次， 保留構成裝置之活性區域的部分，蝕刻除去不需要之矽薄 膜54，55’如圖4(e)所示’獲得島狀圖案。 其次，使用TEOS與氧之混合氣體，藉由電漿CVD，堆積 膜厚約350 nm之第一氧化矽膜，以異方性蝕刻之rie予以回 蝕約400 ，使用矽烷與一氧化二氮之混合氣體，藉由 電漿CVD，如圖4(f)所示，形成膜厚約6〇 nm之氧化矽膜％ ，作為閘極氧化膜。 以後之步驟，藉由與第一種實施形態相同之步驟形成tft。 〔第五種實施形態〕 、就本發明其他實施例之TFT之主動矩陣基板說明時，其構 造與第四種實施形態之主動矩陣基板相同，僅製造方法之 一部分不同，因此僅說明差異處。 第四種實施形態中係準備以特定能量植入有5x丨〇, Vcm2 劑量之:气離子的單晶石夕基板60。而本實施形態中係準備以 特，能量植人有3x l〇16W劑量之氫離子的單晶砍基板。 第四種κ施形態中’於以氫離子植入部62為邊界剝離單 晶矽’可獲得單晶矽薄膜55之前’係在約55〇。〇的溫度下進 行熱處理。而本實施形態則係以多晶矽層形成時之大致 6〇〜80%之能量照射準分子雷射之脈衝，與多晶矽 同樣地，藉由照射全面進行加熱。 长 先前之形成於多晶石夕區域之N通道T F τ的移動率約為工⑻ -44- 200306002 發明說明續頁 2 cm /V · sec，而該液晶顯示用主動矩陣基板中，形成於單 晶石夕區域之N通道TFT則可獲得約6〇〇 cm2/V · sec的移動率 另外，第四種實施形態之液晶顯示用主動矩陣基板中， 先前之形成於多晶矽區域之TFT的移動率約為5〇〇 em2/v· sec。其差異係因本實施形態所獲得之單晶矽薄膜減少氫離 子植入量，而可減少因植入氫離子造成單晶矽之損傷，以 改善TFT特性。 、此外，藉由該液晶顯示用主動矩陣基板，驅動器原本形 成於多晶矽薄膜區域之裝置需要7〜8 V之訊號與電源電壓 ’但是形成於單晶矽薄膜區域之裝置之時間控制器只須3 · 3 v 即可穩定地動作。 〔第六種實施形態〕 發明其他實施例之TFT之主動矩陣基板說明時，因構 '種貫施形態之主動矩陣基板相同，因此省略說明。 、貝苑例中，形成於多晶矽區域與單晶矽區域内之TFT 、、蜀長刀別為5微米、〇.8微米，閘極氧化膜厚分別為8〇 另夕111、屯源電壓分別以8 V、3 V來動作時可穩定地動作。 動外士’於多晶石夕區域内形成閘長為〇·8微米之TFT，並以3 v 、 T之特性k動，源極〜；;及極間之耐壓不足，往 住不能使用。 此*夕卜，於炙 a r-，、、In addition, although the size of the single crystal silicon region that can be obtained by this matter is limited by the wafer size of the LSI manufacturing device, it only needs to be generated for the high-speed logic and time required for the high-speed, power consumption, and changes required for the single-crystal silicon. Size, high-speed dac (current buffer), etc. The manufacturing method of the above active matrix substrate 20 is described below with reference to FIGS. 1 (&) to (Uh). First of all, the insulating substrate 1 is # 173 7 (alkaline earth-aluminum borosilicate glass) from Coning Co., Ltd., which uses high strain point glass. On its entire surface, Shibaiya (S1H4) and nitrous oxide (Nα) are used. The mixed gas is grown by plasma chemical vapor deposition (hereinafter referred to as CVD), as shown in Figure 1 (a) -31-(27) (27) 200306002 nm of silicon oxide film 2. Further, an amorphous silicon film 3 with a film thickness of about 50 nm is deposited on the entire surface by using silane gas and plasma CVD as shown in FIG. 丨 (a). The aforementioned amorphous silicon film 3 is irradiated with an excimer laser to be crystallized by heating to grow a polycrystalline silicon layer 'to form a polycrystalline silicon thin film 4. In addition, the heating of the amorphous silicon film 3 is not limited to heating by irradiation with an excimer laser. If it is heated by other laser irradiation, it may also be heating using a furnace. In addition, in order to promote crystal growth, at least one of nickel, flip, tin ': palladium may be added to the amorphous silicon film 3. As shown in FIG. 1A, a specific region of the polycrystalline silicon thin film 4 is removed by etching. Secondly, prepare a silicon oxide film by oxidizing the surface or stacking the oxide film (stone oxide: shape = film 丨 approximately 200 nm u 'with a specific energy implanted above 10 / cm' here. Here is a 5xlQl6 / em2 dose of hydrogen The ionic gas ion implanted in the second region 12 is doped with a 3xlQl5em.3 single crystal substrate 10. The early-crystal silicon substrate 10 is cut by cutting or the like to remove polycrystalline silicon film 4 by etching. The shape of the area is at least 0.3 micrometers, and preferably 0.5 micrometers. J Form the substrate with the polycrystalline silicon thin film 4 and the single crystal silicon substrate 10: After the substrate, as shown in FIG. 1 (c), make the cut The approach of the single crystal evening substrate 10 = the surface on the side of the gas ion implantation region 12 is closely adhered to the aforementioned etching-removed region. The so-called s.1 cleaning is a cleaning method generally called saki cleaning, and Use a washing solution containing ammonia, nitrogen peroxide, and pure water. Then, heat at a temperature of 30 (rc ~ 60. Temperature lamp annealing, • 32- (28) (28) 200306002 The invention says that the continuation page makes the monocrystalline substrate 100 hydrogen away from the ion implantation area. The temperature of the domain 12 rises above the degree of hydrogen separation from the silicon plate, and the single-crystal silicon storm plate 10 is peeled off with the < odd 2 & ^ α Liao ion implantation region 12 as a boundary. Second class etching: plasma etching Or wet etching, here is the wet type of buffered fluoric acid. The damage layer on the surface of the single crystal silicon substrate that is left on the insulating substrate after peeling off is slightly removed by about lOiim. It is wrong / as shown in Figure 1⑷ A film thickness of about 50 was obtained on the insulating substrate 1: Zhixi crystal silicon film 4 and monocrystalline silicon thin film 5. In addition, after bonding at room temperature to single = substrate U), heat treatment is expected to ~ 35Gt, about 3Q minutes After that, the peeling with peeling decreases with heat treatment at about 650 ° C. I-minute lamp annealing is performed at about 80 ° C. Secondly, the portion constituting the active area of the device is retained. 5 'As shown in Figure 1 (e), obtain an island-like pattern. Next, use TEOS (tetraethoxyfluorene, which is a mixed gas of Si (0c2H) disk oxygen' to deposit film thickness by plasma CVD Approximately 350 nm of oxidized stone xi \ The anisotropic RIE will be used to make an appointment. Later, using the xi xi appearance and the emulsified dinitrogen The gaseous gas is formed by plasma CVD, as shown in FIG. 5 (a), to form a second oxide film 6 having a film thickness of about 60 nm as a gate oxide film. The space between the single crystal silicon thin film patterns is approximately equal to twice the thickness of the first silicon oxide film. An oxide film is retained in the groove-shaped portion between the polycrystalline dream film and the single crystal broken film pattern, and the entire substrate is planarized. Then, it can be formed by the same process as the formation process of the generally known p-stone (polycrystalline stone) TFT matrix substrate. That is, as shown in the mouth, just formed -33- 200306002 ㈣ Contains polycrystalline silicon, silicidation After the gate electrode 21 such as a substance or polymer is implanted, p + & B + ions are implanted, a silicon oxide film (interlayer insulating film) 22 is deposited, and a contact hole 23 is opened. Then, as shown in FIG. 1 (h), a metal (aluminum silicide) wiring 24 is formed in the contact hole 23. In addition, the monocrystalline silicon thin film 5 and the polycrystalline silicon thin film 4 formed on the insulating substrate 1 are patterned into an island shape to form a MOS transistor, a source and a drain of an n-type MOS transistor and a p-type MOS transistor. At least a portion of the area is implanted with P + ions above about 1015 / cm2. With this, the heating treatment by RTA, laser, furnace, etc. is continued. In addition to the polycrystalline silicon thin film 4 region, the single crystal silicon thin film 5 region is also the same%. By removing metal atoms, a TFT with small variation in characteristics and stable characteristics can be obtained. On the liquid crystal display, SiNx (silicon nitride), resin flat film, communication hole, and transparent electrode are formed in order. TFTs for driving and display parts are formed on the polycrystalline silicon thin film 4 area, and on the single crystal silicon thin film 5 Zones form time controllers. In addition, in this embodiment, the implantation energy of hydrogen ions is increased, the hydrogen atom = peak position is deepened, and when the film thickness of the single crystal silicon thin film 5 is increased, it is 50 nm to 100 nm. From 300 nm to 600 nm, the s value of Ding Da gradually increases and the off current increases significantly. Therefore, even if the film thickness of the single crystal silicon thin film 5 is related to the doping density of impurities, it must still be below 600 nm, and below 500 nm, more preferably below 10011111. [Second Embodiment] The active matrix substrate 30 of a TFT according to another embodiment of the present invention is as follows according to the figure (). In addition, the same components as those of the active matrix substrate 20 of the first embodiment will not be described. The active matrix substrate 30 of a semiconductor device is composed of: an insulating substrate 1, an oxide -34- (30) (30) 200306002 description of the invention continued on the silicon (S: io2) films 32 and 11, the second silicon oxide film 3S, The polycrystalline silicon thin film 37, the single crystal silicon thin film 34, the gate oxide film 38, the gate 21, the interlayer insulating film 22, and the metal wiring 24 are configured. The insulating substrate 1 is made of high-strain point glass Cooning's # 丨 737 (alkaline earth-aluminum borosilicate glass). A silicon oxide film 32 having a film thickness of about 35 nm is formed on the entire surface of the insulating substrate 1. On the silicon oxide film 32 on the surface of the insulating substrate 1, a first silicon oxide film 35 having a film thickness of about 10011111 and a polycrystalline silicon thin film 37 having a film thickness of about 50 nm are stacked in an island-like pattern region. Furthermore, in a region different from the silicon thin film 37, a concave portion 33 having a depth of about 150 nm is formed on the silicon oxide film 32 on the surface of the insulating substrate (see FIG. 2 (a)). On the bottom surface of the recess 33, a silicon oxide film η having a film thickness of about 200 and a single-crystal silicon thin film 34 having a film thickness of about 50 nm having the same shape thereon are formed in the region of the island pattern. The area of the polycrystalline silicon thin film 37 is separated from the area of the single-crystalline silicon thin film 34 by at least 0.3 micrometers, and more preferably 0.5 micrometers or more. This prevents metal atoms such as nickel, platinum, tin, and palladium from diffusing into the single crystal silicon region, and promotes stabilization of characteristics. A gate oxide film 36 having a thickness of about 60 nm is formed on the entire silicon oxide film 32, the polycrystalline silicon film 37, and the single crystal silicon film W. On each of the island-like pattern regions of the silicon thin film 37 and the single-crystal silicon thin film 34, a gate 2i containing polycrystalline silicon, silicide, or a polymer is formed. In addition, like the active matrix substrate 30, an interlayer insulating film U, a contact hole 23 (see FIG. 2 (g)), and a metal wiring 24 are formed. In addition, the same -35- (31) (31) 200306002 invention description page, the active matrix substrate 30 is formed on the liquid crystal display with a coffee (nitride stone), a resin flattening film, a communication hole, and transparent The electrode is formed with a TFT for a driver and a display part in a polycrystalline silicon film region, and a time controller for the monocrystalline silicon film. x The mobility of the previous TFT formed in the polycrystalline region is about 100 cm2 / v.sec '. In this active matrix substrate for liquid crystal display 3G, the N-channel TFT formed in the monocrystalline region can be A mobility of about 500 cm2 / v · was obtained. With the active matrix substrate 3G for liquid crystal display, the device originally formed in the 37 region of the polycrystalline silicon film requires a signal of 7 to 8V and the power supply voltage. As a time controller of the device formed in the 34 region of the monocrystalline silicon film, only 3.3 is required. v for stable operation. The manufacturing method of the active matrix substrate 30 described above will be described below with reference to FIGS. 2 (a) to 2 (h). The insulating substrate i is # 1737 (Soil Inspection-Mingshi Pengshiyu acid glass) from C0NING Company. On its entire surface, a gas mixture of Shiyaki and Nitrogen Oxide is used to deposit it by electric paddle CVD. Oxide stone film 32 with a film thickness of about 35 mm. As shown in FIG. 2 (a), a specific area of the aforementioned silicon oxide film of about 150 nm is etched to form a recessed portion 33. / Its-person 'is ready to form a film thickness of about 2 by oxidizing the surface or depositing an oxide film in advance The oxidized stone is a monolithic substrate having a hydrogen ion implantation region 12 implanted with a dose of 5 χΐ〇ΐ6_2 hydrogen ions at a specific energy. It is cut at least smaller than the same shape as the region forming the recess 33 〇5um shape. SC-1 cleans the insulating substrate forming the aforementioned recessed portion 33 and the cut single-crystal silicon-36- 200306002 {} Description of the invention The two substrates on the continuation of the substrate are shown in Figure 2 (b). It is shown that the hydrogen ion implantation side surface is closely adhered to the etching-removed area. Then, heat treatment is performed at 30 (TC ~ 600t ;, here, about 55 (Γ (: 2 temperature), by laser irradiation or containing The lamp is annealed at a peak temperature of about 70 ° C or higher to raise the temperature of the hydrogen ion implantation region 12 of the single crystal silicon substrate 10 to a temperature above the temperature at which hydrogen is released from the silicon. The substrate 10 is peeled off using the chloride ion implantation region 12 as a boundary. Wet buffered hydrofluoric acid with isotropic plasma etching or wet etching Etching, f removes the damaged layer on the surface of the single-crystal silicon substrate left on the insulating substrate 1 by peeling off at about 10 nm. As a result, as shown in FIG. 2 (c), a film thickness of about 1 on the insulating substrate 1 is obtained. 50nm single crystal silicon thin film 34. Then, on the entire insulating substrate, a mixed gas of silane and nitrous oxide was used, and plasma plasma CVD was used, as shown in Figure 2 *. F dioxygen-cut film 35. Further, the sintered gas was subjected to plasma CVD on the entire surface thereof, as shown in FIG. 2 (a), and an amorphous silicon film 36 having a thickness of about 50 nm was deposited. Amorphous The silicon film 36 is irradiated with excimer laser to be heated and crystallized, so that the polycrystalline silicon layer grows to form a polycrystalline silicon film 37, and the proximity and the strength are improved. The person removes the polycrystalline silicon film by money carving 3 The unnecessary part of 7 and the part on the at least single crystal% thin film 34 of the second dicing film 35. Secondly, the part constituting the active area of the device is left, and the unnecessary silicon film is removed by etching, as shown in FIG. 2 (e) An island pattern was obtained as shown in the figure. Using a mixed gas of TEOS and oxygen, plasma CVD was used to deposit oxygen with a film thickness of about 350 nm. The silicon film is etched back with anisotropic etching. • 37- (33) (33) 200306002 Description of the Invention Continued after 400nm, a mixed gas of silane and nitrous oxide is used, and CVD, as shown in FIG. 2 (a), a oxide film having a thickness of about 60 nm is formed as the gate oxide film 38. At this time, the space between the first silicon oxide thin film pattern and the single crystal silicon thin film pattern is formed. It is approximately equal to twice the thickness of the first silicon oxide film. The oxide film remains in the groove between the polycrystalline silicon film and the single-crystal silicon film pattern before the island-like etching. The entire substrate is flattened. One embodiment is the same, so it is omitted. [Second Embodiment] In the description of the active matrix substrate of the TFT of the other embodiment of the present invention, the cross-sectional structure is the same as that of the active matrix substrate 20 of the first embodiment, so only the differences will be described. The polycrystalline silicon thin film 43 of this embodiment (refer to FIG. 3 (d)) is formed of so-called continuous grain grain silicon (polycrystalline silicon) having polycrystalline silicon with uniform crystal growth directions. The uranium N-channel τ f τ formed in the continuous crystal grain field stone evening region has a mobility of about 200 cm 2 / V · sec, and the N-channel TFT formed in the monocrystalline silicon region in the active matrix substrate for the liquid crystal display A mobility of about 500 cm2 / v · sec can be obtained. With the active matrix substrate for liquid crystal display, the device originally formed in the 43 region of the polycrystalline silicon film requires a signal of 7 to 8 V and the power supply voltage, but the time controller of the device formed in the 5 region of the monocrystalline silicon film only 3 · 3 V is required for stable operation. The manufacturing method of the active matrix substrate described above is described below with reference to Figs. 3 (a) to -38-(34) (34) 200306002 Description of Invention Continued 3 (d). The third embodiment of the present invention is the same as the first embodiment. First, the insulating substrate 1 uses # 1737 (alkaline earth_aluminum borosilicate glass) of Cooning Company 'on its entire surface, using silane and A mixed gas of nitrous oxide is deposited on the silicon oxide film 2 with a thickness of about 200 nm by plasma CVD. On the entire surface, an amorphous stone film 3 with an area of about 50 faces was deposited by using a plasma gas CVD using a plasma gas CVD. Further, as shown in FIG. 3 (a), the whole surface is made of Shibuya and: Nitrogen oxide mixed gas' to deposit the first-first oxide film 41 on the surface by plasma CVD.口 丘 笮 层 Γ " 4 First breast: Silicon film 41 is formed by etching in a specific area of Kai 2 to control the hydrophilicity of the surface of the amorphous stone film 3 on the opening portion of the silicon film ′ :: 3) Therefore, a thin oxide stone film 42 is formed on the surface of the amorphous stone film 3, and a nickel acetate aqueous solution is spin-coated thereon. Said Γΐ square ΓΤ temperature for about 12 hours solid state growth, so as to promote the growth direction of the crystal growth direction of the same crystal wow further-removed polycrystalline Te 43). The specific area where the polycrystalline silicon thin film 43 is removed by the engravings = fossil evening films 41 and 42. Then the man-in-person was prepared to cut the thickness of the chloride ion by oxidizing the field with about 200 nm of oxygen, and the chlorine ion was implanted with an energy film called monocrystalline stone. The substrate 10 is cut to remove the Shixi substrate 10 earlier than the remaining time. The shape is at least 0.3 micrometers smaller, and it is particularly suitable that:;, 〇; Substrate and Monocrystalline Silicon Substrate-39- 200306002 1 ~ Description of the Invention After the two substrates are continued, as shown in Fig. 3 (c), the side of the lice ion implantation region 12 close to the monocrystalline silicon substrate 丨 〇 The surface is closely adhered to the etching-removed area. At this time, the polycrystalline silicon thin film 43 is separated from the single crystal silicon substrate 10 by at least 0.3 micron, and it is particularly preferable to separate more than 0.5 micron. This prevents metal atoms such as uranium, tin, and uranium used in the polycrystalline silicon thin film 4 ‘ie ν ′ described later from diffusing into monocrystalline regions, and promotes the stabilization of characteristics. In addition, heat treatment is performed at 300 C to 600 C, here at a temperature of about 55 ° C, and it is irradiated with laser light or contains about 700. The lamp annealed at a peak temperature above the temperature, the temperature of the nitrogen ion implantation portion 12 of the single crystal substrate 10 was raised to a level higher than the degree of hydrogen release from silicon, and the single crystal silicon substrate was peeled off with the hydrogen ion implantation portion 12 as a boundary. 10. Either a four-dimensional plasma plasma or wet-type engraving, here is a wet-type engraving of buffered gas acid. The poaching removes the monocrystalline silicon remaining on the insulating substrate 1 after peeling off with a slight etch of about 10 nm. A damaged layer on the surface of the substrate 10. As a result, as shown in FIG. 3 (a), a polycrystalline silicon thin film 43 and a silicon thin film 5 each having a film thickness of about 5 G nm are obtained on the insulating substrate 1. First, the unnecessary portion of the polycrystalline silicon film 43 and at least a portion of the single crystal stone film 5 of the second emulsified stone film are removed by etching. Further in accordance with the specific device shape, the island-like grounds are cut off. ^ Tu Xi a ^ Λ removes unnecessary parts of the polycrystalline silicon film 43 and the single-crystalline silicon film 5 by etching. Secondly, the portion constituting the active area of the device is left, and an unnecessary silicon film is removed by etching to obtain an island-like pattern. Secondly, a mixed gas of TEOS and oxygen was used to produce an oxygen-cut film with a thickness of about 350 sides by plasma CVD, and then returned by anisotropic RIE, and then a mixture of Shixiyuan and nitrous oxide was used. Gas, by electric double -40- (36) 200306002 Description of the invention Continued = 20% :: about 6, m! Chemical: evening film (not shown in the figure), as a gate single crystal silicon thin film Just mentioned the first silicon oxide film pattern and the aforementioned double, the space in the front is approximately equal to the aforementioned-oxygen-cut film thickness portion to retain the oxygen medium from the groove-shaped sidewall between the day and night film pattern to reduce the slope. -Change or shape in the stepped part, t: two openings are formed on the oxygen cutting film near the active area of the t-device. The removal of the oxygen cutting film is used as a mask to promote crystal growth. (15 keV, 5 × 10 15 / cm2) ′ The heat treatment was performed at rta for about 1 minute. It is a way to avoid the diffusion of nickel atoms in single crystal silicon. It physically accommodates space. * A very small amount of recorded atoms may still be mixed into the process. Therefore, the active region of single crystal silicon should be subjected to the aforementioned removal step. It is also possible to omit the removal step according to design considerations. The subsequent steps are the same as those of the first embodiment, and are therefore omitted. [Fourth Embodiment] The active matrix substrate 50 of the TFT in other embodiments of the present invention is substantially the same as the active matrix substrate 20 of the first embodiment, so only the differences will be described. The film thickness of the oxidized oxide film 2 of the active matrix substrate 20 is about 200 nm, while the film thickness of the silicon oxide film 52 of the active matrix substrate 50 of this embodiment is about 35 nm, and a depth of about 150 nm is further formed. Recessed portion 55 (see FIG. 4 (b)). In addition, the film thickness of the silicon oxide film 11 of the active matrix substrate 20 is about 200 nm, and the film thickness of the silicon oxide film 61 of the active matrix substrate 50 of this embodiment is about 400 nm. -41- 200306002 κ} Continued description of the invention, the mobility of the N-channel TFT formed in the polycrystalline silicon region is about 100 cm / V · sec, and this active matrix substrate for liquid crystal display is formed in monocrystalline silicon The N-channel TFT in the area can obtain a movement rate of about 500 cm2 / v · sec. With this active matrix substrate for liquid crystal display 50, the driver was originally formed in the area of the silicon film 54 area. The signal and power supply voltage of 8 V, but the time controller of the device formed in the 55 area of the monocrystalline silicon film only needs 3 · 3 V to operate stably. In addition, in this embodiment, a single-crystal silicon substrate 60 having a silicon oxide film 61 having a thickness of about 400 nm is used. The variation in the threshold value of the obtained TFT is different from a single crystal having a silicon oxide film n having a thickness of about 200 nm. The 0.3 V (soil) comparison of the first implementation of the silicon substrate 10 is about 1/20 15 V (± (J)), and especially the operation stability at low current C k is improved. The influence of the contamination of the interface between the bonded monocrystalline substrate and the glass substrate or the fixed charge caused by the lattice strain and incompleteness is reduced. The film pressure of the aforementioned oxygen-cut film 61 is thicker as the film thickness becomes larger, and the threshold value The less variation there is, but due to the trade-off between the efficiency (time required for oxidation) and the step of the formation step of the silicon oxide film, the appropriate value is approximately 200 nm to 400 nm. When attention is paid to the variation, the appropriate value is approximately 40. 〇nm, when the step and efficiency are valued, the appropriate value is approximately 200011111. Of course, when the step does not pose a problem, it must be approximately 400nm or more. For the manufacturing method of the active matrix substrate 50 described above, The following description is based on FIG. 4 (magic to FIG. 4 (h). The insulating substrate 1 is made of # 1737 (alkali from CONING). Class _ aluminum borosilicate glass under glass pot) on its entire surface, the use of a mixture of stone yaki and nitrous oxide -42- 200306002 (3δ) Description of the Invention Continued — — — — Gas, by plasma CVD A silicon oxide film 52 having a film thickness of about 350 nm is deposited. As shown in FIG. 4 (a), further, an amorphous stone film 53 having a film thickness of about 50 nm is deposited by plasma CVD using a silane gas on the entire surface. The polycrystalline silicon thin film 54 is formed by heating the fl? And the excimer laser on the non-Japanese silicon stone film 5 3 to grow the polycrystalline silicon layer to form a polycrystalline silicon thin film 54. The polycrystalline silicon thin film 54 and the oxidation in a specific region are removed by etching at about 150 nm. As shown in FIG. 4 (b), a part of the silicon film 52 is formed into a portion 55 having a depth of about 200. Next, a silicon oxide film having a thickness of about 400 nm is prepared in advance by oxidizing the surface or stacking the oxide film 6 丨, A single crystal silicon substrate 60 having a hydrogen ion implantation portion 62 implanted with a dose of 5 χ 〇 〇1 hydrogen ions at a specific energy. The single crystal substrate 60 is cut to a shape smaller than the shape of the concave portion 55 by 0.5. Micron shape. 7 SC-1 After washing the two substrates with the polycrystalline silicon film 54 and the single crystal silicon substrate ⑼, As shown in Fig. 4 (c), the surface of the side close to the hydrogen ion implantation portion 62 of the single crystal silicon substrate 60 is closely adhered to the bottom surface of the recessed portion 55. Then, the temperature is 30CTC to 65CTC, and here is approximately 55. (: The heat treatment is performed at a temperature of 'The temperature of the hydrogen ion implantation portion 62 of the single crystal silicon substrate 60 is raised to a temperature at which hydrogen is released from Shi Xi by laser irradiation or lamp annealing including a peak temperature above about 70 (rc). Above, the single-crystal silicon substrate was peeled off at 60 ° with the hydrogen ion implantation portion 62 as the isotropic plasma etching or wet etching. Here, the wet etching with buffered fluoric acid was performed. The damaged layer remaining on the surface of the single crystal substrate 10 on the insulating substrate 1 after being peeled off. -43- 200306002 (39) Announcement of Continuation of the Invention According to this, as shown in FIG. 4 (d), a polycrystalline silicon thin film 5 4 and a single crystal with a film thickness of about 50 nm can be obtained on an insulating substrate 丨 respectively. Evening film 5 5. Then, lamp annealing was performed at a temperature of about 800 ° C for} minutes. Next, the portion constituting the active area of the device is left, and unnecessary silicon thin films 54, 55 'are removed by etching to obtain an island pattern as shown in FIG. 4 (e). Secondly, a mixed gas of TEOS and oxygen was used to deposit a first silicon oxide film with a thickness of about 350 nm by plasma CVD, and then etched back by anisotropic etching to about 400 Å, using silane and nitrous oxide. The mixed gas is subjected to plasma CVD as shown in FIG. 4 (f) to form a silicon oxide film% having a film thickness of about 60 nm as a gate oxide film. In the subsequent steps, tft is formed by the same steps as in the first embodiment. [Fifth Embodiment] When the active matrix substrate of a TFT according to another embodiment of the present invention is described, its structure is the same as that of the active matrix substrate of the fourth embodiment, and only a part of the manufacturing method is different, so only the differences will be described. In the fourth embodiment, a single crystal substrate 60 with a dose of 5 × 10, Vcm2: gas ions is prepared to be implanted with a specific energy. In this embodiment, a single-crystal slicing substrate with hydrogen ions at a dose of 3 × 10 16 W is prepared. In the fourth κ application mode, 'Before the single-crystal silicon is peeled off by using the hydrogen ion implantation portion 62 as a boundary', a single-crystal silicon film 55 is obtained, which is about 55 °. The heat treatment was performed at a temperature of 0 ° C. In this embodiment, the pulse of the excimer laser is irradiated with approximately 60 to 80% of the energy when the polycrystalline silicon layer is formed, and like polycrystalline silicon, the entire surface is heated by irradiation. The mobility of the N-channel TF τ previously formed in the polycrystalline region is about ⑻ -44- 200306002 Description of the invention continued on 2 cm / V · sec, and this active matrix substrate for liquid crystal display is formed on a single substrate. The N-channel TFT in the spar area can obtain a mobility of about 600 cm2 / V · sec. In addition, in the fourth embodiment of the active matrix substrate for liquid crystal display, the mobility of the TFT previously formed in the polycrystalline silicon region About 500em2 / v · sec. The difference is that the single crystal silicon thin film obtained in this embodiment mode reduces the amount of implanted hydrogen ions, and can reduce the damage to the single crystal silicon caused by the implantation of hydrogen ions to improve the TFT characteristics. In addition, with the active matrix substrate for liquid crystal display, the device that the driver originally formed in the polycrystalline silicon thin film area requires a signal of 7 ~ 8 V and the power supply voltage. However, the time controller of the device formed in the monocrystalline silicon thin film area only needs 3 · 3 v for stable operation. [Sixth Embodiment] When the active matrix substrate of a TFT according to another embodiment of the invention is described, the active matrix substrate of the same embodiment is the same, so the description is omitted. In the case of Beiyuan, the TFTs and shovels formed in the polycrystalline silicon region and the single crystal silicon region are 5 micrometers and 0.8 micrometers, and the gate oxide film thicknesses are 80 and 111. 8 V, 3 V can operate stably. "Dongwaishi" formed a TFT with a gate length of 0.8 micron in the area of polycrystalline stone, and acted with the characteristics of 3 v and T, the source is ~; and the voltage between the electrodes is insufficient, so it cannot be used . This * Xi Bu, Yu Zhi a r-,,,

. 、日日夕區域内形成閘長為1.5微米之TFT，並以3 V 時，臨限值電壓及其變動大，實用上有問題。 利=外’一本=明m定於上述各種實施形態，在申請專 、厂、勺範圍内可作各種變更，適切組合不同實施形態 -45- 200306002 (41) [mmmm 之實施形態亦包含於本發 中分別揭示之技術性手段所獲得 明之技術範圍内。 此外，本發明之實施形態並不限定於本内容 矽形成法或層間絕緣膜之材料、膜厚等，其他該領域 術者即使藉由獲知之手段當然亦可實現。此外，%尤材料 -般而言只要係相同目的上使用I，即使為不同材：二 然亦可獲得同樣之效果。 田 〔第七種實施形態〕 就本發明另外實施形態，依據圖5〜圖8說明如下。 圖5#、本實施形態之s〇I基板2〇1之剖面圖。該基板 係以前述精靈切割法所作成者，於非晶質無鹼玻璃基板之 高應變點無鹼玻璃基板202之表面堆疊有二氧化矽膜2〇3， 其上貼合有被二氧化矽膜204所覆蓋之單晶矽薄膜2〇5。 。亥圊5巾|曰曰石夕薄膜2〇5描緣成小於高應變點無驗玻璃 基板202 匕係依目岫市售之高應變點無鹼玻璃基板與矽晶 圓之一般大小關係者，單晶矽薄膜2〇5亦可為與高應變點無 鹼玻璃基板202相同大小者。此外，該圖5中因係模式圖， 因此厚度之大小關係並非事實。一般而言，高應變點無鹼 玻璃基板202之厚度約為〇·7 mm，二氧化矽膜2〇3, 2〇4之厚 度約為50〜300 ηηι。 此外’單晶矽薄膜2〇5之厚度為40〜2〇〇 nm。單晶矽薄膜 205之厚度，亦即氫離子之植入深度若低於2〇〇 nm，可獲得 7U全耗盡化之電晶體，可大幅提高特性，並且加工亦容易 。另外’比4〇 nm薄時，膜厚變動增加，導致製造上之安全 -46- (42)200306002 發罪譲：日月續頁 可保持安全係數，且 係數降低。因此如上述地作選擇時 獲得南的元件特性。 ' 圖6顯示將單晶石夕片2 日μ_ 、έ 5於高應變點無鹼玻璃基板 202前的狀態。單晶矽片 伋 之一虱化矽膜204係藉由化學汽相 生長法（C V D法）成膜而獲得兮勝 X侍忒犋日守，如该圖6所示，僅 於單晶矽片206之表面。以下、+、々批ρ 7丄 下述之熱氧化法形成時，則形成. In the day and night area, a TFT with a gate length of 1.5 microns is formed, and at 3 V, the threshold voltage and its variation are large, which is problematic in practical use. Benefit = Outer's book = Ming m is determined in the above various implementation forms, and various changes can be made within the scope of the application, factory, and spoon, and different implementation forms can be appropriately combined. Within the technical scope obtained by the technical means disclosed in this publication respectively. In addition, the embodiments of the present invention are not limited to the content of the silicon forming method, the material of the interlayer insulating film, the film thickness, and the like, and those skilled in the art can of course realize it even by means of knowing. In addition, %% materials-In general, as long as I is used for the same purpose, even if it is different materials: Er, the same effect can be obtained. [Seventh Embodiment] Another embodiment of the present invention will be described with reference to Figs. 5 to 8 as follows. FIG. 5 # is a cross-sectional view of a soI substrate 201 of this embodiment. The substrate is made by the aforementioned sprite cutting method. A silicon dioxide film 203 is stacked on the surface of the high strain point alkali-free glass substrate 202 of the amorphous alkali-free glass substrate, and a silicon dioxide film is bonded thereon. The single crystal silicon thin film 205 covered by the film 204. . Haiyi 5 towels | Said that the stone xi film 2 05 is drawn to be smaller than the high strain point non-inspection glass substrate 202. It is the general size relationship between the high strain point alkali-free glass substrate and silicon wafers sold by Imeya, The single crystal silicon thin film 205 may also be the same size as the high strain point alkali-free glass substrate 202. In addition, since FIG. 5 is a schematic diagram, the thickness relationship is not a fact. Generally speaking, the thickness of the high strain point alkali-free glass substrate 202 is about 0.7 mm, and the thickness of the silicon dioxide films 203, 204 is about 50 to 300 ηη. In addition, the thickness of the 'single-crystal silicon thin film 200 is 40 to 200 nm. The thickness of the single crystal silicon film 205, that is, if the implantation depth of hydrogen ions is less than 200 nm, a 7U fully depleted transistor can be obtained, which can greatly improve the characteristics and be easy to process. In addition, when it is thinner than 40 nm, the variation in film thickness increases, resulting in manufacturing safety. -46- (42) 200306002 Guilt 譲: Sun and Moon Continuation Page The safety factor can be maintained and the factor is reduced. Therefore, when the selection is made as described above, the characteristics of the device are obtained. FIG. 6 shows a state before the monocrystalline slab of μ_ and Z_5 are placed on the alkali-free glass substrate 202 at a high strain point. The single crystal silicon wafer 204 is obtained by chemical vapor phase growth (CVD) film formation, and it is obtained by Xisheng X Shiji Rishou, as shown in FIG. 6, only for single crystal silicon wafers. 206 surface. When the following, +, 々 batch ρ 7 丄 is formed by the following thermal oxidation method, then

於單晶石夕片206之表面與背面^ Β tH U ”月囱兩者。而早晶矽片206以前述 精靈切割法分割時，矣& Μ ^ 才表面側之二氧化矽膜亦被除去，而如 前述圖5所示，成為單晶矽薄膜2〇5。 圖7(a)至®] 7(g)係顯示上述之s〇I基板2〇1的製作程序圖 。由於前述高應變點無鹼玻璃基板2〇2原本親水性不足，為 求增加親水性，如圖7(a)至圖7(b)所示，二氧化矽（MO〗）膜 203形成前述約50〜30〇 nm。其成膜如藉由電漿化學汽相生 長法（電漿CVD法），於真空處理室中流入丁E〇s(Tetra 〇rth〇 Silicate)氣體與氧氣，可藉由實施電漿放電來進行。前述電 漿CVD法由於係藉由電漿放電活化材料氣體而成膜，因此 適於在無法提高至600。〇以上高溫之該高應變點無鹼玻璃 基板202上成膜。具體之成膜法概要如下。 雨述真空處理室内流入材料氣體之TE〇S氣體與氧氣，將 真空度调整為133〜1330 Pa。基板溫度形成約2〇〇〜400T：。 放置該基板之載台亦形成高頻電源之一方電極，另一方電 極與載台間施加RADIO FREQUENCY帶（RF帶）之頻率為 13 · 5 6 MHz的高頻，使產生電漿放電。其高頻功率密度約為 0· 1 W/cm2。藉由該電漿放電，經過約1分鐘時間，可形成 >47- 200306002 (43)On both the front and back sides of the single crystal slab 206 ^ Β tH U ”moon chimney. When the early-crystal silicon wafer 206 is divided by the aforementioned sprite cutting method, the silicon dioxide film on the surface side of 矣 & M ^ is also It is removed and becomes a single-crystal silicon thin film 20 as shown in FIG. 5 described above. FIGS. 7 (a) to 7] (g) show the manufacturing process diagram of the above-mentioned soI substrate 201. Because of the aforementioned high The strain point alkali-free glass substrate 200 was originally not sufficiently hydrophilic. In order to increase the hydrophilicity, as shown in FIGS. 7 (a) to 7 (b), a silicon dioxide (MO) film 203 forms about 50 to 30. 〇nm. The film is formed by plasma chemical vapor phase growth method (plasma CVD method), but EO (Tetra 〇thth Silicate) gas and oxygen flow into the vacuum processing chamber, plasma can be implemented by Discharge is performed. The aforementioned plasma CVD method is suitable for film formation on the alkali-free glass substrate 202 at a high strain point that cannot be raised to a temperature of 600 ° C or higher because the plasma is formed by activating the material gas with a plasma discharge. The outline of the film-forming method is as follows: The rain and the TEOS gas and oxygen flowing into the material gas in the vacuum processing chamber are adjusted to a vacuum of 133 to 1330 Pa. The temperature of the substrate is about 2000 ~ 400T: The stage on which the substrate is placed also forms one of the electrodes of the high-frequency power source, and the frequency of applying a RADIO FREQUENCY band (RF band) between the other electrode and the stage is 13 · 5 6 MHz The high frequency causes plasma discharge. Its high frequency power density is about 0.1 W / cm2. With this plasma discharge, after about 1 minute, it can be formed> 47- 200306002 (43)

¥明說日iS 前述約5〇〜300 nm之二氧化矽膜2们。 此時，電漿頻率亦可祐北乂、^ d^¥ Tomorrow iS The aforementioned silicon dioxide film 2 of about 50 ~ 300 nm. At this time, the plasma frequency can also be used by Beibei, ^ d ^

卫非則述RF γ，亦可為微波帶（約 2.456 GHz)。此外，高施銳机…… V …交點《驗玻璃基板2〇2親水性不〇 的原因在於其化學組成。—汽 一乳化矽（Si〇2)為親水性佳的材料 ’但是其在該基板上僅含約50%，此即顯示親水性不足的 原口^上所述’冑由僅以上述厚度塗敷二氧化石夕膜203 ’可獲得足夠之親水性。 另外，-般而言單晶石夕片2〇6係形成6,8, 12忖的圓板形狀 。此外’ -般而t，摻雜有某種濃度之石朋及碟等雜質，並 電阻率低達1〇 Qcm。纟士曰古认曰> / ^ 、、'口日日方位，於具有（100)面者最容易 獲得。為求避免雜質自表面擴散，而以熱氧化法等，首先 如^⑷至圖7⑷所示，形成約5〇〜·咖之二氧切膜咖 。剛述熱氧化法亦可為乾氧氧化法，不過由於該方法的氧 化速度k，因此欲形成前述300 nm之氧化臈時將耗費大量 時間。因此亦可使用熱氧化及蒸汽氧化法等氧化速度快的 方法。 而後，如圖7⑷所示，植入氫離子。其_種植入條件為·· ，速電壓為12〜36 kV，植入量約為4〜6x 1〇16cm_2。藉由該氫 離子植入，如參照符號21〇所示，於單晶矽片206中之特^ 深度（前述40〜200 nm)之面上形成有氫離子植入面。 如此所準備之高應變點無鹼玻璃基板2〇2及單晶矽片2〇6 為求除去表面之微粒子予以活化，係以純水稀釋氨水及過 氧化氫水之所謂SC-丨溶液洗淨。前述溶液，如將市售 之28%氨水、w。/。之過氧化氫水、與電阻率為i〇 MQem二 -48- (44) (44)200306002 發1說明續頁 上之純水，以容積比丨：2 : 12等的比率混合作成。使前述 高應變點無鹼玻璃基板202及單晶矽片2〇6浸潰於該％」溶 液中約1〜10分鐘，除去表面的微粒子。而後，在純水流水 下洗甲約10分鐘，自各表面除去藥劑，再以自旋乾燥機等 使其乾燥。 如此洗淨之高應變點無鹼玻璃基板202與單晶矽片206彼 此靠近表面時，藉由van der貿心13力而接著。其態樣如圖 7(f)所不。此時將單晶矽片2〇6顛倒，將前述氫離子植入面 密著於高應變點無鹼玻璃基板2〇2。密著時之力，於經過良 好洗淨表面之微粒子被除去，表面充分活化時，僅須少 卉力即可（如約數百g)。所謂藉由前述van 力之引 力，係與原子間距離之6次方成反比而變化者。因而表面各 原子接近於可與固體之原子間距離比較的距離時形成接著 狀態。&接著狀態於高應變點無鹼玻璃基板202為透明基板時 ’自背面以目視觀察可確認干擾色消失。 匕使單曰曰石夕片206接著之高應變點無驗玻璃基板2〇2， 如，所述地藉由彼此靠近而接著（vanderWaals結合）後，藉 由貫施熱處理，而成為化學性結合鍵。亦# ,表面之氫藉 由熱而消散，各個基體上之各原子空鍵結合而接著力強化 、二本件务明人確認即使並非如前述特開平1 3 Μ號 之800 1200 C之兩溫，只須約3〇〇。〇以上之溫度即可。另外 ，基板之南應變點無鹼玻璃之應變點在7⑻。c以下，提高至 2以上溫度時即變形，因此如本發明之基板使用高應變點 無驗玻璃時，士 σ μ &、+、>L ^ , „ 令上所述之接者力強化之熱處理的最高溫度 -49- (45) (45)200306002 發明說明續寅 限制在約65(TC，經本件發明人證者 b 一Wei Fei stated that RF γ can also be a microwave band (about 2.456 GHz). In addition, the reason why Gao Shirui machine ... V… Intersection point “The glass substrate 200 is not hydrophilic because of its chemical composition. —Steam-emulsified silicon (SiO2) is a material with good hydrophilicity, but it only contains about 50% on the substrate, which means that the original mouth showing insufficient hydrophilicity is described above. The coating is only coated with the above thickness. The dioxide dioxide film 203 'can obtain sufficient hydrophilicity. In addition, in general, the monocrystalline stone sheet 206 is formed into a circular plate shape of 6, 8, 12 忖. In addition, '-t is generally doped with impurities such as stone and dish, and the resistivity is as low as 10 Qcm. The ancient ancestors of the princes said that / /, ^, 口, 日, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 日, 口, 口, 方位, 方位, 口, 方位, 方位, 口, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, 方位, and 日, were most easily obtained by those with (100) faces. In order to avoid the diffusion of impurities from the surface, thermal oxidation method and the like are firstly formed as shown in FIG. 7 to FIG. The thermal oxidation method just described may also be a dry oxygen oxidation method, but because of the oxidation rate k of this method, it takes a lot of time to form the aforementioned osmium oxide at 300 nm. Therefore, methods such as thermal oxidation and steam oxidation can be used. Then, as shown in FIG. 7 (a), hydrogen ions are implanted. Its _ implantation conditions are ..., the speed voltage is 12 to 36 kV, and the implantation amount is about 4 to 6 x 1016 cm_2. As a result of the hydrogen ion implantation, as shown by reference numeral 21, a hydrogen ion implantation surface is formed on a surface having a specific depth (the aforementioned 40 to 200 nm) in the single crystal silicon wafer 206. The high-strain-point alkali-free glass substrate 20 and single crystal silicon wafer 20 prepared in this way are cleaned by a so-called SC- 丨 solution, which is diluted with pure water to dilute ammonia and hydrogen peroxide in order to remove the surface particles and activate them. . The aforementioned solution is, for example, commercially available 28% ammonia water, w. /. Hydrogen peroxide water is mixed with pure water on the basis of the resistivity i0 MQem II -48- (44) (44) 200306002 1 Description Continued on the basis of volume ratio 丨: 2: 12 and so on. The high-strain-point alkali-free glass substrate 202 and the single crystal silicon wafer 206 were immersed in this% "solution for about 1 to 10 minutes, and fine particles on the surface were removed. Then, the nails were washed under running water for about 10 minutes, the chemicals were removed from each surface, and then dried with a spin dryer or the like. When the high-strain-point alkali-free glass substrate 202 and the single crystal silicon wafer 206 thus cleaned are close to each other, they are adhered by a van der trade force. Its appearance is shown in Figure 7 (f). At this time, the single crystal silicon wafer 206 was turned upside down, and the aforementioned hydrogen ion implanted surface was closely adhered to the high strain point alkali-free glass substrate 202. The force at the time of adhesion is removed by fine particles that have been well cleaned on the surface. When the surface is fully activated, only a small amount of force is required (such as about several hundred g). The so-called gravitational force of the van force is changed in inverse proportion to the sixth power of the distance between the atoms. Therefore, when the surface atoms are close to a distance comparable to the interatomic distance of a solid, a bonding state is formed. & When the state is that the alkali-free glass substrate 202 is a transparent substrate at a high strain point ', it can be confirmed by visual observation from the back surface that the interference color disappears. The high-strain point of the glass substrate 20, which is followed by the stone slab 206, is as follows, as described above, by being close to each other and then bonding (vanderWaals bonding), then through chemical heat treatment, it becomes a chemical bond key. Also #, the surface hydrogen is dissipated by heat, each atom on each substrate is bonded with a vacant bond and then strengthened. The two people confirmed that even if it is not the two temperatures of 800 1200 C as described in JP 1 3 M, Only about 300. 〇 Above temperature is sufficient. In addition, the south strain point of the substrate is 7⑻. c, it will be deformed when the temperature is increased to 2 or more. Therefore, when the substrate of the present invention uses a high strain point non-inspection glass, σ μ &, +, > L ^, The maximum temperature of heat treatment -49- (45) (45) 200306002 Description of the invention continued Yin is limited to about 65 (TC, after this inventor witness b a

仍可獲得充分之接合強度。Λ卩使最高溫度約為60(TC 如此接著之高應變點無鹼玻墙 界面具有約之接 走、早日日矽片206在 等所巧之薄膜之接著力比較裝置 广者之單晶砍薄膜2〇5自端部 進:估 性理論」（Ed · de · Randaun = Ye · % 以進仃。、 三譯，東京圖書）中，薄層（厚产h) 1 c ltZ*，佐藤常 „ ,, c (予度）於分離面上藉由與表 =:反而作用之外力自物體剝除時，每單位長度=Still obtain sufficient bonding strength. Λ 卩 makes the maximum temperature of about 60 (TC, so the high-strain point alkali-free glass wall interface has about the pick-up, the silicon wafer 206 is waiting for the adhesion of the film as soon as possible, compared with the single crystal cutting film of the device 2005 Advancement from the End: Estimation Theory "(Ed · de · Randaun = Ye ·% Yi Jin., Third Translation, Tokyo Books), thin layer (thick yield h) 1 c ltZ *, Sato Chang„ ,, c (予 度) On the separation surface by peeling off the object with an external force instead of the table =: per unit length =

Eh3 a = ^^y(^2r/ax2)2 來表示。此時’ e為薄膜之楊氏率，σ為薄膜之泊松比，h !薄膜之厚度，x為薄膜密著之平面之橫方向的軸，"薄 膜在法線方向剝除之膜之變位。該接著力a可藉由求（之 法線方向之變位對於χ軸之2階偏微分係數而獲得。 此外，進行接著力強化用之熱處理時，玻璃基板之熱膨 脹率大於單晶矽片206之熱膨脹率，係進行穩定之接著的要 素。矽之熱膨脹率於室溫附近約為SjxlO^deg-1，於約500°C 的溫度下約為4.1xl〇_6deg-1。另外，本發明使用之前述高應 受點無鹼玻璃基板自室溫至約7 0 0 °C的溫度範圍内，可獲得 熱膨脹率與單晶矽相等或大於的基板，因此，如由鹼土類_ 銘硼矽酸玻璃、鋇-鋁硼矽酸玻璃、鹼土類_鋅_鉛_鋁硼$夕酸 玻璃或驗土類-鋅-鋁矽酸玻璃構成，於50〜300。(：之溫度 範圍内，熱膨脹率約為4.7/10_6和8_1。因此，於前述50〜3001： -50- (46) 200306002 發明說明續頁 之Μ度範圍内，兩應變點無鹼玻璃基板2〇2之熱膨脹率較大 i另外，本發明前述所謂非晶質無驗玻璃基板，係指驗含 里為1 /〇以下之彳政I物，具體之製品如CONING公司之 CONING# 1737 玻璃等。 圖8模式顯示為求進行前述熱處理，而將接著之高應變點 無驗f璃基板202及單晶石夕片206放入爐中，於高溫時麵曲 勺狀心口上述之熱膨脹率的關係，於暴露在進行熱處理Eh3 a = ^^ y (^ 2r / ax2) 2. At this time, 'e is the Young's rate of the film, σ is the Poisson's ratio of the film, h! The thickness of the film, and x is the axis in the transverse direction of the plane where the film is close, " Variable Bit. The adhesion force a can be obtained by obtaining the second-order partial differential coefficient of the displacement of the normal direction to the x-axis. In addition, when the heat treatment for the adhesion strengthening is performed, the thermal expansion coefficient of the glass substrate is greater than that of the single crystal silicon wafer 206 The thermal expansion coefficient is a continuation factor for stability. The thermal expansion coefficient of silicon is about SjxlO ^ deg-1 near room temperature, and about 4.1xl0_6deg-1 at a temperature of about 500 ° C. In addition, the present invention The above-mentioned high-stress-resistance alkali-free glass substrate is used in a temperature range from room temperature to about 700 ° C, and a substrate having a thermal expansion coefficient equal to or greater than that of single crystal silicon can be obtained. Therefore, for example, from alkaline earth _ borosilicate Glass, barium-aluminum borosilicate glass, alkaline earth _zinc_lead_aluminum boron acid glass or earth test-zinc-aluminum silicate glass, in the temperature range of 50 ~ 300. (: Thermal expansion coefficient It is about 4.7 / 10_6 and 8_1. Therefore, within the range of 50 degrees from the aforementioned 50 ~ 3001: -50- (46) 200306002 Invention Description, the thermal expansion coefficient of the alkali-free glass substrate 2 at two strain points is larger. In the present invention, the so-called amorphous glass substrate without inspection refers to the government policy that the inspection content is 1/0 or less. I, concrete products such as CONING # 1737 glass of the CONING company, etc. Figure 8 mode shows that in order to perform the aforementioned heat treatment, the subsequent high strain point non-inspection glass substrate 202 and the single crystal chip 206 are placed in the furnace. The relationship between the above-mentioned thermal expansion coefficient of the curved spoon-shaped mouth at high temperature is exposed to heat treatment.

用之回/孤下日守，尚應變點無鹼玻璃基板2〇2向下翹曲於凸方 =。此時’藉由^述㈣der Waals力而接著之兩者中，單 夕片206之在回應變點無鹼玻璃基板2〇2附近的部分橫方 向拉扯’不過如前所述，藉由高應變點無驗玻璃基板202 向下輕曲於凸方向，自單晶石夕片206之端剝離之力血趣曲方 向:致，^抵銷單^片咖自接著㈣離力，不引起剝離 成為形成結合鍵的要素。 但是，雨述氫離子之植人面21G因氫脆化之分離，如溫户 1約_c以上時不產生，因此設定約6⑽。c之溫度 同日π有效地進行Γ、+、+立—丄> & #With the use of back / solder, the Strain-free alkali-free glass substrate 200 warped downward to the convex square =. At this time, 'by the ㈣der Waals force followed by the two, the part of the single-sheet piece 206 is pulled horizontally in the vicinity of the alkali-free glass substrate 2 in response to the change point', but as described above, with high strain The pointless inspection glass substrate 202 bends downward in the convex direction, and the force of peeling off from the end of the single crystal chip 206 is in the direction of blood funky: ^, offsetting the single ^ sheet of coffee from the subsequent separation force, without causing peeling Elements that form a bond. However, the hydrogen-embedded human face 21G is separated by hydrogen embrittlement. It does not occur when the temperature is above about _c, so it is set to about 6⑽. The temperature of c effectively performs Γ, +, + stand-up on the same day π > &#

仃強化刚述接者力之熱處理與該單晶矽 ，^用的熱處王里。如進行600°c，30〜60分鐘之熱處理日士 2:广:斤述Λ ’接著之面的接著力被強化，並且單晶矽片 以刖述虱離子植入面21〇分離。顯示該 述圖5及圖7(g)。 狀心者為則 时處理中〜TDS(溫度吸收光譜學）評估時，觀 C之4起，氫排出的狀態。該氮排出時，氣自單晶 -51 - (47) (47)200306002 發明說明續頁 206之氫離子植入面210的位置急遽消散，該單晶矽片2〇6 分離成單晶石夕薄膜2〇5與單晶石夕片裏a，於高應變點無驗玻 璃基板逝上可獲得單晶砍薄膜2()5。藉由如上的處理，形 成具有前述膜厚為40〜200 nm之單晶矽薄膜2〇5的s〇i基板 2〇卜在該膜厚範圍内，元件形成之電晶體的通道部須完全 耗盡化。 另外，上述說明係說明以丨個階段進行熱處理，不過多階 &進仃％’可進一步強化接著力。尤其是，亦可將強化接 著力用之熱處理（約3〇〇〜55(rC之溫度）與分離用之熱處理 區分成不同階段來進行。此時，由於接著力強化如以上所 ^係以約300 C以上的溫度進行，其係300〜550°c之單晶 夕片206未被植入面2 i 〇分離的溫度，經過約工$分鐘以下短 時間的處理，進行該接Im 丁 /接者力強化用之第一階段的熱處理， 而後，以600〜700。(？之、、西痒、社—、w ^ 之μ度進仃分離用之第二階段的熱處理 ’膜自接合面剝落，可、、成，卜结 ^ Γ减ν早日日矽片206之膜於熱處理後剝 落之瑕疲品的數量。 、卜—上述之°兒明係顯示於前述熱處理中使用電爐，不 、亦可藉由田射等光（燈）退火之包含大致以上之峰 :溫度的瞬間熱退火來進行。藉由前述電爐之加熱，當高 應變點無驗玻璃基板2G2達到應變點以上之高溫時，產生基 ，的1½ ’而以燈等之瞬間熱退火及雷射加熱（雷射退火） 、】可防止正個基板收縮，且可提高須退火之位置的溫 吏、:日日f生或刀離效率提高。並可提高製造基板i 上的通量。 -52- 200306002 (48) I褎明說明續ί 以上作成之SOI基板201，如在前述高應變點無鹼玻璃基 板202内使用透過可視光的材料時，於前述單晶矽薄膜 之層上形成薄膜電晶體，加工成TFT液晶顯示（lcd ·· Uquid Crystal Display)裝置、TFT有機電致發光（〇led ·· 〇 Llght Emitting Diode)顯示裝置等。於此種主動矩陣驅動之 顯示面板上導入本發明之s〇I基板2〇1時，可促進電晶體之 特性均一化、穩定化及高性能化，亦可自前述主動矩陣之 驅動器積體化週邊驅動器、時間控制器等系統。此外，亦 可於必要之部分貼附單晶矽片2〇6，亦可對應於大面積之基 板。 如以上所述，本發明之s〇I基板2〇1係將以精靈切割法等 所獲得之單晶矽薄膜205貼合於基板上而作成之s〇l基板， 並著眼於於貼合時即使約為3〇〇它仍可獲得足夠之接合強 度，該基板上使用非晶質無鹼玻璃基板之高應變點無鹼玻 璃基板202。 因此，無須使用調整組成之晶化玻璃及高耐熱玻璃，而 使用藉由主動矩陣驅動之液晶顯示面板等上一般所使用之 高應變點無驗玻璃，可以低成本製造S〇i基板。此外，因前 逃熱處理之溫度低，因此與以800〜1200°C進行熱處理之先 月比較’可減少鹼性金屬對半導體層之擴散達數位數。藉 此’可使為防止前述擴散而形成之二氧化矽膜2〇3, 2〇4等的 膜厚比先前薄，可提高通量。 、 此外’係使用自室溫至約7〇〇。(：之溫度範圍内，熱膨脹率 與單晶石夕相等或大於之高應變點無鹼玻璃基板2〇2，於進行 -53- 200306002 ㈣ [5明說明續頁 提高自最高溫度約600。(：之i曰& u 1 又jL您早日日矽片2〇6與前述單晶矽薄膜 205之分離及單晶矽片2〇6盥該含 — ”遠π應變點無鹼玻璃基板202 之接著力的熱處理時，可扣卩剎I 4rz ^ & 』$卩制基板破裂及單晶矽薄膜205 的剝離。 上述說明原係說明單晶石夕片206最容易獲得之表面為 (_面’不過("〇)面及(100)面等其他方位者亦全部同樣 地自形成時’ T製造具有無須表面研磨而平坦之石夕膜面的 S ΟI基板。 而與（100)方位者比較，（110)方位者，由於最接近之各原 子絕大部分排列於該（110)面上，因此分離該單晶矽片2〇6 時，分離面極為平坦，可減少作成於本s〇I基板2〇1上之矽 電晶體的不良率。 此外，採用（111)方位時，分離之面與單晶矽塊之劈開面 一致，且於同平面内，最接近之各原子存在於自該（111)面 稍微偏差的角度，因此分離該單晶矽片206時，分離面極為 平坦，可進一步降低作成於本S0I基板2〇1上之矽電晶體的 不良率。 〔第八種實施形態〕 依據圖9(a)及圖10說明本發明另外實施形態如下。 圖9(a)至圖9(h)係顯示本實施形態之s〇i基板211的作成 程序圖。該SOI基板211與前述之SOI基板201類似，對應之 部分註記相同之參照符號，而省略其說明。須注意的是， 如圖9(h)所示’该SΟI基板211係於同一個高應變點無鹼玻 璃基板202上作成多晶石夕薄膜212與前述單晶石夕薄膜2〇5。 -54- (50) (50)200306002 發明說明續頁 首先，如圖9(a)至圖9(b)所示，於高應變點無鹼坡璃基板 202上藉由電漿化學汽相生長法（PECVD法）形成厚度約3〇〇 nm之構成内塗層膜之絕緣膜2 1 3。該内塗層之最上層形成 親水性良好之前述二氧化矽膜。其次，如圖9(c)所示，以 前述PECVD法形成30〜200 nm之非晶石夕膜214，並在 4〇0〜500°C下進行脫氫退火，排除非晶矽膜214中之氯。而 後’如圖9(d)至圖9(e)所示，以準分子雷射熔融、晶化（雷 射晶化）以非晶矽膜214形成TFT之區域214a，而形成多晶石夕 薄膜212。此時之多晶矽薄膜212的膜厚須與爾後形成之單 晶矽薄膜205的膜厚，如前述4〇〜200 nm因應。 雷射晶化後，如圖9(e)至圖9(f)所示，蝕刻除去貼合有單 晶矽薄膜205之區域214b的矽膜。此時，擔心多晶矽薄膜212 f面與光阻密著而污染時，只須於光阻塗敷前，在多晶矽 薄膜212之表面預先形成厚度約30〜1〇〇 nm之二氧化矽膜即 可此外自夕晶矽薄膜2 12之膜厚，依需要以亦與前述絕 緣膜213之厚度方向之—部分因應’單晶㈣膜2Q5之膜厚 與多晶矽薄膜212之膜厚一致的方式蝕刻除去。 繼續’植入有前述氫離子之單晶矽片2〇6切斷成覆蓋前述 虫：除去之區域214b的形狀’與前述圖7⑴至圖7⑷同樣地 π 119(g)至圖9(h)所將單晶石夕片㈣貼合於經前述蝕 :1 區域Μ内’繼續藉由經過前述約喊之熱步驟 膜205早日日㊉片2G6自氫離子植人面21G分離而獲得單晶石夕薄 同才具有此等薄膜205, 212，或如前述之s〇i基板 -55- 200306002 (51) 明巍明續頁 ，僅有單晶矽薄膜205時，TFT之形成程序均如以下之圖10 所不。圖10係自丽述SOI基板211作成之一種薄膜電晶體221 的剖面圖。詳細說明該薄膜電晶體221之作成程序如下，首 先將前述薄膜205, 212因應形成之電晶體尺寸予以圖案化 。其次，形成閘極絕緣膜222。該閘極絕緣膜222最宜為以 二氧化矽為主要成分之膜，如厚度為3〇〜2〇〇nm。由於閘極 絕緣膜222在200〜40(TC溫度下成膜時形成緻密性差之膜， 口此於成膜後係以約6〇〇°C之溫度實施緻密化退火。該退火 亦兼將植入氫離子之單晶矽膜之晶質恢復成植入前之晶質 的處理。 而後，形成約300 nm之閘極膜223，並圖案化成適切之形 狀。進一步將前述閘極膜223作為掩模，於前述薄膜2〇5, 212 内植入離子，而形成^或〆區域224。此時，本發明如前述 也係將單曰曰石夕薄膜2〇 5之厚度形成在約2 〇 〇 nm以下，因此 可將通道區域2 2 5完全耗盡化。 繼續，形成約400 nm之層間絕緣膜226後，於與源極、汲 極取付接觸之位置開孔。而後，形成約4〇〇 nm之源極、汲 極金屬膜227，並予以圖案化。依需要，打型m〇stft於前 述植入離子時，形成LDD構造以獲得高可靠性。 如此作成之薄膜電晶體22 1藉由貼合、分離，獲得單晶矽 溥膜205之位置，因構成通道部之矽膜為單晶，因此並無可 自多晶矽薄膜212觀察出之粒場的電導，可獲得高的特性， 且相同單晶矽薄膜2〇5上之全部電晶體的特性均一。因而如 使用於LCD顯示裝置時，係使用於源極驅動器部及週邊電 -56- 200306002 ^ ; 發明說明續頁 路反之’自多晶矽薄膜2 12作成前述薄膜電晶體22 1的位 置則用於特性較差之像素部及閘極驅動器部。 依據本件I明人之作成結果，單晶矽薄膜電晶體，於 NMOSTFT時，電效移動率為5〇〇 cm2/v·咖，臨限值電壓 為1,0 V ’斷開電流為lxl〇-12A，於PMOSTFT時，電效移動 率為2=0 cm /v · sec，臨限值電壓為〇 v，斷開電流為 1X10 A，均可獲得均一性佳之薄膜電晶體。 藉由如此構成，可獲得貼合有單晶矽薄膜2〇5之區域21仆 與多晶矽薄膜212之區域214a大致相等高度之s〇I基板211 。因而包含島狀蝕刻，對於前述區域214a，2Ub可同時處理 以後大部分的步驟。此外，形成階差小之電晶體及電路， 如液晶面板時，單元厚度控制性佳。 〔第九種實施形態〕 依據圖11(a)至圖11(h)及圖16說明本發明另外一種實施 形態如下。 圖11(a)至圖11(h)顯示本實施形態之主動矩陣基板32〇(半 $體衣置）的一種製造步驟。如圖11(h)所示，本主動矩陣基 板320具備：絕緣基板3〇1、氧化矽（Si02)膜302, 31 1、多晶 石夕薄膜304、單晶矽薄膜305、閘極氧化膜306、閘極321、 層間絕緣膜322、及金屬配線324。此外，主動矩陣基板320 具備切換元件之薄膜電晶體（TFT : thin film transist〇r)。主 動矩陣基板320如使用於液晶顯示裝置等。 絕緣基板3 0 1包含高應變點玻璃。此處之絕緣基板3 〇 i係 使用包含鹼土類-鋁硼矽酸玻璃之c〇del737(c〇NING公司 -51 - (53) (53)200306002仃 Enhance the heat treatment of the power just described and the single crystal silicon, and use the heat of the king. For example, the heat treatment is performed at 600 ° C for 30 to 60 minutes. The adhesion force of the second surface is strengthened, and the single crystal silicon wafer is separated by the implantation surface of the lice ions. 5 and 7 (g) are shown. The person in the center of the heart is in the state of the current processing ~ TDS (temperature absorption spectroscopy) evaluation, the state of hydrogen emission from 4 to C. When the nitrogen is exhausted, the gas is rapidly dissipated from the position of the hydrogen ion implantation surface 210 of the single crystal -51-(47) (47) 200306002. Continued on page 206. The single crystal silicon wafer 20 is separated into single crystals. The thin film 2 05 and the single crystal chip a can be obtained on a high strain point non-examination glass substrate. Through the above processing, a soi substrate 20 having a single-crystal silicon thin film 205 having a thickness of 40 to 200 nm is formed. Within this film thickness, the channel portion of the transistor formed by the element must be completely consumed. Exhausted. In addition, the above description is that the heat treatment is performed in one stage, but the multistage & advance% 'can further strengthen the adhesion. In particular, the heat treatment (approximately 300-55 (rC temperature) for strengthening and bonding) and the heat treatment for separation can be divided into different stages. At this time, because the bonding strength is strengthened as above The temperature is higher than 300 C, which is the temperature at which the single crystal chip 206 of 300 ~ 550 ° c is not separated on the implanted surface 2 〇. After a short time treatment of about $ minutes or less, the connection is performed. The first step of the heat treatment used to strengthen the force, and then, 600 ~ 700. (? ,, Western itching, company-, w ^ into the second stage of the heat treatment for separation, the film peeled from the joint surface ， 可 ， 成 ， 卜 结 ^ Γ minus ν The number of defective products that peeled off the film of silicon wafer 206 after heat treatment in the early days. Bu—The above-mentioned ° Erming shows the use of an electric furnace in the aforementioned heat treatment, no, nor It can be performed by instant thermal annealing including light (lamp) annealing including the above peaks: temperature, etc. by the above-mentioned electric furnace. When the high strain point non-examination glass substrate 2G2 reaches a high temperature above the strain point, it is generated. Base, 1½ 'and instantaneous thermal annealing with lamps etc. Radiation heating (laser annealing), [] can prevent the substrate from shrinking, and can improve the temperature of the position to be annealed: the daily life or the knife separation efficiency is improved. And the flux on the manufacturing substrate i can be improved. 52- 200306002 (48) I clarify the continuation of the above-mentioned SOI substrate 201. For example, when a material that transmits visible light is used in the aforementioned high-strain-point alkali-free glass substrate 202, a thin film is formed on the aforementioned single-crystal silicon film. Transistors, processed into TFT liquid crystal display (lcquid crystal display) devices, TFT organic electroluminescence (olid · · lght Emitting Diode) display devices, etc. The invention is introduced into such active matrix-driven display panels When the SOC substrate 021 is used, it can promote the uniformity, stabilization, and high performance of the transistor, and can also integrate peripheral drives, time controllers, and other systems from the aforementioned active matrix driver. In addition, it can also A single crystal silicon wafer 206 is attached to the necessary part, which can also correspond to a large-area substrate. As described above, the soi substrate 201 of the present invention is a single crystal obtained by the wizard cutting method and the like. Silicon film 205 bonding A sol substrate made on a substrate and focused on achieving sufficient bonding strength even at about 3,000 at the time of bonding. The substrate uses an alkali-free glass with a high strain point of an amorphous alkali-free glass substrate. Substrate 202. Therefore, it is not necessary to use crystallized glass and high heat-resistant glass whose composition is adjusted, and high-strain-point non-examination glass generally used on active matrix driven liquid crystal display panels, etc., can be manufactured at low cost. In addition, because the temperature of the heat treatment is low, it can reduce the diffusion of alkali metals to the semiconductor layer by several digits compared with the previous month of heat treatment at 800 ~ 1200 ° C. By this, the thickness of the silicon dioxide film 203, 204, etc. formed to prevent the aforementioned diffusion can be made thinner than before, and the throughput can be improved. In addition, it is used from room temperature to about 700. (: In the temperature range, the thermal expansion coefficient is equal to or greater than that of single crystal slab, alkali-free glass substrate 002, which is performed in -53- 200306002 ㈣ [5 indicates that the continuation page is increased from the maximum temperature of about 600. ( : I i & u 1 and jL your early separation of the silicon wafer 206 from the aforementioned single crystal silicon film 205 and the single crystal silicon wafer 206 containing — ”far π strain point alkali-free glass substrate 202 When the subsequent heat treatment is performed, the substrate I 4rz can be broken and the single crystal silicon film 205 can be peeled off. The above description originally explained that the most easily obtained surface of the single crystal wafer 206 is (_ surface). 'However, when the (" 〇) plane and the (100) plane are all formed in the same way as other self-formed ones', T Manufactures an S OO substrate having a flat stone surface without the need for surface polishing. In comparison, in the (110) orientation, since most of the closest atoms are arranged on the (110) plane, when the single crystal silicon wafer 20 is separated, the separation plane is extremely flat, which can reduce the production in this s. Defective rate of silicon transistor on I substrate 201. In addition, when the (111) orientation is used, the separated surface is The split surface of the silicon block is the same, and in the same plane, the closest atoms exist at an angle slightly deviated from the (111) plane. Therefore, when the single crystal silicon wafer 206 is separated, the separation plane is extremely flat, which can further reduce the production. Defective rate of silicon transistor on the S0I substrate 201. [Eighth Embodiment] Another embodiment of the present invention will be described with reference to Figs. 9 (a) and 10. Figs. 9 (a) to 9 (h) ) Is a flowchart showing the creation of the SOI substrate 211 of this embodiment. The SOI substrate 211 is similar to the aforementioned SOI substrate 201, and the corresponding parts are marked with the same reference symbols, and descriptions thereof are omitted. It should be noted that, as shown in FIG. As shown in 9 (h), the SIO substrate 211 is formed on the same high strain point alkali-free glass substrate 202 as a polycrystalline silicon film 212 and the aforementioned monocrystalline silicon film 205. -54- (50) (50 200306002 Description of the Invention Continued First, as shown in FIGS. 9 (a) to 9 (b), a thickness of about 100% is formed on the high strain point alkali-free sloped glass substrate 202 by a plasma chemical vapor phase growth method (PECVD method). 300nm insulating film constituting the undercoating film 2 1 3. The uppermost layer of the undercoating layer has good hydrophilicity The aforementioned silicon dioxide film. Next, as shown in FIG. 9 (c), an amorphous stone film 214 having a thickness of 30 to 200 nm is formed by the aforementioned PECVD method, and is dehydrogenated and annealed at 400 to 500 ° C to exclude Chlorine in the amorphous silicon film 214. Then, as shown in FIG. 9 (d) to FIG. 9 (e), the TFT is formed by using the amorphous silicon film 214 with an excimer laser melting and crystallization (laser crystallization). The polycrystalline silicon thin film 212 is formed in the region 214a. The thickness of the polycrystalline silicon thin film 212 at this time must correspond to the thickness of the single-crystalline silicon thin film 205 formed later, as described above in the range of 40 to 200 nm. After the laser crystallization, as shown in FIGS. 9 (e) to 9 (f), the silicon film of the region 214b to which the single crystal silicon thin film 205 is bonded is removed by etching. At this time, if you are worried that the f-side of the polycrystalline silicon thin film 212 is contaminated with the photoresist and contamination, you only need to form a silicon dioxide film with a thickness of about 30 to 100 nm on the surface of the polycrystalline silicon thin film 212 before photoresist coating. In addition, the film thickness of the silicon crystal thin film 2 12 is etched and removed in a manner consistent with the thickness direction of the aforementioned insulating film 213 in part according to the thickness of the 'single-crystal silicon film 2Q5 and the film thickness of the polycrystalline silicon thin film 212 as needed. Continue "Single-crystal silicon wafer 2 implanted with the aforementioned hydrogen ions cut to cover the aforementioned insects: shape of the removed region 214b" is the same as in Fig. 7 (a) to Fig. 7 (p) 119 (g) to Fig. 9 (h) The monocrystalline stone slabs were bonded to the above-mentioned etch: 1 area M. Continue to obtain the single crystals by separating the slab 2G6 from the hydrogen ion implantation surface 21G as soon as possible through the thermal step of film 205 described above. Xi Botong only has these films 205, 212, or the above-mentioned soi substrate-55- 200306002 (51) Ming Weiming Continued. When there is only single-crystal silicon film 205, the TFT formation process is as shown in Figure 10 below. No. FIG. 10 is a cross-sectional view of a thin film transistor 221 made from the SOI substrate 211. The procedure for making the thin film transistor 221 is described in detail as follows. First, the thin films 205 and 212 are patterned according to the size of the formed transistor. Next, a gate insulating film 222 is formed. The gate insulating film 222 is most preferably a film containing silicon dioxide as a main component, such as a thickness of 30 to 200 nm. Since the gate insulating film 222 forms a poorly dense film during film formation at a temperature of 200 to 40 ° C., the densification annealing is performed at a temperature of about 600 ° C. after the film formation. The crystallinity of the single crystal silicon film into which hydrogen ions are implanted is restored to the crystallinity before implantation. Then, a gate film 223 of about 300 nm is formed and patterned into a suitable shape. The gate film 223 is further used as a mask. Mold, implanting ions in the above-mentioned film 205, 212 to form the ^ or 〆 region 224. At this time, the present invention also forms the thickness of the single-layered Shixi film 205 at about 200 as described above. Below nm, the channel region 2 2 5 can be completely depleted. Continuing, after forming an interlayer insulating film 226 of about 400 nm, a hole is opened at a position in contact with the source and drain electrodes. Then, about 400 nm is formed. The source and drain metal film 227 of nm are patterned. According to need, the mostft is patterned to form an LDD structure when the ions are implanted to obtain high reliability. The thin-film transistor 22 1 thus produced is obtained by The position of the single-crystal silicon film 205 is obtained by bonding and separating. The film is single crystal, so there is no grain field conductivity that can be observed from the polycrystalline silicon thin film 212, and high characteristics can be obtained, and the characteristics of all transistors on the same single crystal silicon thin film 205 are uniform. Therefore, if used in LCD In the display device, it is used in the source driver section and the peripheral circuit. -56- 200306002 ^; Description of the invention continued on the contrary, the position where the thin film transistor 22 1 is made from the polycrystalline silicon thin film 2 12 is used for the pixel portion with poor characteristics and Gate driver section. According to the results of this article, when a single-crystal silicon thin film transistor is used in an NMOS TFT, the electrical efficiency shift is 500 cm2 / v · ca, and the threshold voltage is 1,0 V. The open current is lxl0-12A. When the PMOSTFT is used, the electrical efficiency shift is 2 = 0 cm / v · sec, the threshold voltage is 0v, and the cut-off current is 1X10 A. Both thin film transistors with good uniformity can be obtained. With such a structure, a SiO substrate 211 having a region 21 bonded to the monocrystalline silicon film 205 and a region 214a of the polycrystalline silicon film 212 approximately equal in height can be obtained. Therefore, island-like etching is included. For the aforementioned region 214a, 2Ub can handle most of the subsequent steps simultaneously In addition, when a transistor and a circuit with a small step difference are formed, such as a liquid crystal panel, the thickness of the cell is excellent. [Ninth Embodiment] Another embodiment of the present invention will be described with reference to Figs. 11 (a) to 11 (h) and Fig. 16. The implementation mode is as follows. Fig. 11 (a) to Fig. 11 (h) show a manufacturing step of the active matrix substrate 32 (half-body clothing) of this embodiment. As shown in Fig. 11 (h), the active matrix substrate 320 includes: insulating substrate 301, silicon oxide (Si02) film 302, 31 1. polycrystalline silicon film 304, single crystal silicon film 305, gate oxide film 306, gate 321, interlayer insulating film 322, and metal Wiring 324. In addition, the active matrix substrate 320 is provided with a thin film transistor (TFT) of a switching element. The active matrix substrate 320 is used in, for example, a liquid crystal display device. The insulating substrate 3 0 1 contains high strain point glass. Here, the insulating substrate 3 〇 i is based on co-del737 (co-company -51-(53) (53) 200306002) containing alkaline earth-aluminum borosilicate glass.

發明剩續頁 另外，絕緣基板301之材料並無特別限定，亦可為言 點玻璃之鋇-鋁硼矽酸玻璃、硼矽酸玻璃、鹼土類“广 鋁硼矽酸玻璃、鹼土類-辞-鋁硼矽酸玻璃等。' ^絕緣基板3G1之表面上，大致全面地形成有包含氧化石夕 虱化矽膜3〇2。氧化矽膜302之膜厚約為1〇〇nm。 於氧切膜302上形成有多晶㈣膜3G4及氧切膜3ιι 。多晶石夕 '薄膜304形成島狀圖案，其膜厚約為5〇⑽ 石夕膜3⑽以在氧切膜3G2上，與多⑼薄膜3Q4不同之區 域形成島狀圖案的方式形成，其膜厚約為2〇〇議。於氧化 石夕膜叫上進-步以島狀圖案之方式形成有同形狀之單晶 矽薄膜305。單晶矽薄膜3〇5之膜厚約為5〇 。 士鄰接之多晶矽薄膜3〇4區域與單晶矽薄膜3〇5區域至少分 離〇·3 μηι，更宜分離〇 5 μηι以上。 藉此可防止於後述之多晶矽薄膜304製造步驟中使用之 錄、銘、錫、把等金屬原子擴散於單晶石夕區域，而促進特 性的穩定化。 於整個氧化矽膜302、多晶矽薄膜3〇4及單晶矽薄膜3〇5上 形成有包含氧化矽之閘極氧化膜306。閘極氧化膜3〇6之膜 厚約為60 nm。 多晶矽薄膜304及單晶矽薄膜3〇5之各島狀圖案之區域上 面的閘極氧化膜306上形成有閉極321。閉極321包含多晶矽 ，石夕化鶴。另外，閘極321之材料並無特別限定，如亦可為 多晶矽、其他矽化物或聚化物及高熔點金屬等。 -58- 200306002 v ; f月說明續頁 形成有該閘極321之整個閘極氧化膜306上形成有包含氧 化石夕之層間絕緣膜322。但是層間絕緣膜322具有開口之接 觸孔323(參照圖i1(g))，該接觸孔323内形成有包含石夕化紹 等金屬之金屬配線324。金屬配線324自多晶矽薄獏3〇4及單 晶石夕薄膜305之各島狀圖案區域的上面形成。 再者，主動矩陣基板320於液晶顯示用而形成有圖上未顯 不之氮化矽（SiNx)、樹脂平坦化膜、連通孔、透明電極等 。此外，於多晶矽薄膜區域内形成有驅動器及顯示部用之 TFT ’而於單晶矽薄膜區域内形成有控制藉由驅動器驅動 之各時間的時間控制器及微處理器等。當然，驅動器亦可 以單晶矽形成。此時性能進一步提高，裝置面積更小，均 一性佳，可以更低電壓動作，不過由於成本增加，因此須 依用途來選擇。 、 以下’依據圖11( a)〜圖11 (h)說明主動矩陣基板320之製造 方法。 ~ ° 首先’於上述之包含code 1737(CONING公司製）之絕緣基 板301的整個表面上，使用TE〇s(四乙氧基矽烷，亦即 SU〇C2H5)4)與氧之混合氣體，藉由電漿化學汽相生長法Continued pages of the invention In addition, the material of the insulating substrate 301 is not particularly limited, and may be barium-aluminum-borosilicate glass, borosilicate glass, alkaline earth type "wide aluminum borosilicate glass, alkaline earth type" -Aluminum borosilicate glass, etc. ^ On the surface of the insulating substrate 3G1, a silicon oxide film containing silicon oxide and silicon oxide 302 is formed on the entire surface. The thickness of the silicon oxide film 302 is about 100 nm. A polycrystalline silicon film 3G4 and an oxygen cutting film 3 ι are formed on the cutting film 302. The polycrystalline stone film '304 forms an island-like pattern with a film thickness of about 50 ⑽ The stone cutting film 3 ⑽ is on the oxygen cutting film 3G2, and The multi-layer thin film 3Q4 is formed by forming island-like patterns in different regions, and its film thickness is about 200 μm. On the stone oxide film, it is called ascending-step, and a single-crystal silicon film of the same shape is formed in an island-like pattern. 305. The thickness of the single crystal silicon thin film 305 is about 50. The area between the adjacent polycrystalline silicon thin film 304 and the single crystal silicon thin film 305 is separated by at least 0.3 μm, and more preferably separated by more than 0.05 μm. This can prevent the metal atoms such as recording, inscription, tin, and metal used in the manufacturing steps of the polycrystalline silicon thin film 304 described later from expanding. In the monocrystalline region, the stability of characteristics is promoted. A gate oxide film 306 containing silicon oxide is formed on the entire silicon oxide film 302, polycrystalline silicon film 300, and single crystal silicon film 305. Gate oxidation The film thickness of the film 306 is about 60 nm. A closed electrode 321 is formed on the gate oxide film 306 on each island-shaped pattern region of the polycrystalline silicon film 304 and the single crystal silicon film 305. The closed electrode 321 includes polycrystalline silicon, Shi Xihua Crane. In addition, the material of the gate 321 is not particularly limited, such as polycrystalline silicon, other silicides or polymers, and high melting point metals. -58- 200306002 v; f An interlayer insulating film 322 containing oxidized stone is formed on the entire gate oxide film 306 of the electrode 321. However, the interlayer insulating film 322 has an opening contact hole 323 (refer to FIG. I1 (g)). Shi Xihua and other metal wirings 324. The metal wirings 324 are formed on the island-like pattern regions of the polycrystalline silicon thin film 304 and the monocrystalline silicon thin film 305. Furthermore, the active matrix substrate 320 is used for liquid crystal display. Silicon nitride (SiNx) not shown on the figure is formed ), Resin flattening film, communication hole, transparent electrode, etc. In addition, a driver and a display TFT ′ are formed in the polycrystalline silicon thin film region, and a single crystal silicon thin film region is formed with a controllable time for controlling each time driven by the driver. Time controller, microprocessor, etc. Of course, the driver can also be formed of single crystal silicon. At this time, the performance is further improved, the device area is smaller, the uniformity is better, and it can operate at lower voltage, but due to the increase in cost, it must be used according to the purpose. The selection is as follows: 'The manufacturing method of the active matrix substrate 320 will be described in accordance with FIG. 11 (a) to FIG. 11 (h). ~ ° First' on the entire surface of the above-mentioned insulating substrate 301 including code 1737 (made by CONING), Using TE〇s (tetraethoxysilane, ie SU〇C2H5) 4) and oxygen mixed gas, by plasma chemical vapor phase growth method

(P-CVD · piasma chemical Vapor Deposition，以下稱p-CVD 法）堆積膜厚約100 nm之氧化矽膜302。 繼續，於氧化矽膜302上，藉由使用矽烷氣體之p_cVD法 堆積膜厚約50 nm之非晶質矽膜303(圖ll(a))。 而後於非晶質矽膜303上照射準分子雷射予以加熱，將非 晶質矽予以晶化，藉由使多晶矽層生長而形成多晶矽薄膜 -59- (55) (55)200306002 304 射照射加熱，亦可：：；:，，如亦可藉由其他雷 ，亦可…：爐加熱。此外，為求促進結晶生長 種。於非…膜3 03内添加鎳、-、錫、把中之至少— 心藉由㈣除去多…㈣中之特定區域(圖 化2或nt晶！基板31G。單晶石夕基板训藉由預先氧 之^ :宜乳化膜（氧化石夕膜）’而形成有膜厚約200 nm 處L/k:311。料’單晶矽基板310具有以特定能量(此 處：24keV)植入有1〇1、2以上，此處為5χΐ〇ΐ6/_^ 辽子的虱離子植人部312，__3xiq1W3 «度之雜質，N通道TFT之臨限值設定成適切之值猎“ ^ X比藉由蝕刻除去多晶矽薄膜304之特定區域之形 狀至少小〇 · 3 &gt; | Λ《 、 小.5 μπι以上的形狀，藉由切割或 刪，異方性_等，切斷單㈣基板31卜 ^ 、、鏖項將形成有多晶矽薄膜304之基板與單晶矽基板3 1() 之兩基板以除去微粒子與表面活化用之SC-〗洗淨予以活 化後，在室溫下使靠近切斷之單晶矽基板31〇之氫離子植入 邛3 12側之表面密著接合於蝕刻除去（圖ii(b))之區域（圖 ())此蚪所明SC-1洗淨，係一種一般稱為RCA洗淨的洗 淨法並使用包含氨、過氧化氫與純水的洗淨液進行洗淨。 而後，以30(TC〜60(rc，此處以約55〇。〇之溫度熱處理， -60- (56)200306002 發明說明顏 將單as矽基板3 1 〇之氫離子植入部3〗2溫度昇溫至氫自係脫 離的溫度以上。藉此，將氫離子植入部312作為邊界劈開剝 離單晶石夕基板3 1 0。 另外，該熱處理並無特別限定，如亦可藉由使用雷射照 射或包含約700°C以上之峰值溫度之燈退火，將單晶矽基板 310之氫離子植入部312溫度昇溫至氫自係脫離的溫度以上。(P-CVD · piasma chemical Vapor Deposition (hereinafter referred to as p-CVD method)) A silicon oxide film 302 having a thickness of about 100 nm is deposited. Continuing, on the silicon oxide film 302, an amorphous silicon film 303 having a film thickness of about 50 nm was deposited by the p_cVD method using a silane gas (FIG. 11 (a)). Then, an amorphous silicon film 303 is irradiated with an excimer laser to heat it, the amorphous silicon is crystallized, and a polycrystalline silicon film is formed by growing a polycrystalline silicon layer. -59- (55) (55) 200306002 304 You can also ::;: ,, if you can also use other mines, you can also :: Furnace heating. In addition, in order to promote crystal growth. Add nickel,-, tin, non -... at least-in the film 303 to remove a specific area in the ... (picture 2 or nt crystal! Substrate 31G. Single crystal substrate training by Pre-oxygenation ^: Emulsification film (stone oxide film) should be used to form L / k: 311 at a film thickness of about 200 nm. The single crystal silicon substrate 310 is implanted with a specific energy (here: 24keV) Above 〇1,2, here is 5χΐ〇ΐ6 / _ ^ Liaozi's lice ion implantation part 312, __3xiq1W3 «degree of impurities, the threshold value of the N-channel TFT is set to a suitable value for hunting" ^ The shape of a specific region of the polycrystalline silicon thin film 304 removed by etching is at least smaller than 0.3 | Λ <, smaller than 5 μm, and the single-sided substrate 31 is cut by cutting or deleting, anisotropy, etc. ^ The first and second substrates are formed with a polycrystalline silicon thin film 304 and a single crystal silicon substrate 3 1 () to remove fine particles and surface activation. After cleaning and activation, close to the cut at room temperature. The hydrogen ion implantation of the single crystal silicon substrate 31 ° 3 and the surface on the 12 side are closely bonded to the area (FIG. Ii (b)) removed by etching (FIG. Ii). Is a washing method generally called RCA washing, and is washed with a washing solution containing ammonia, hydrogen peroxide, and pure water. Then, 30 (TC ~ 60 (rc, here about 55.0). Temperature heat treatment, -60- (56) 200306002 Description of the invention The temperature of the hydrogen ion implantation section 3 of the single as silicon substrate 3 1 0 is raised to a temperature higher than the temperature at which hydrogen is detached from the system. As a result, hydrogen ions are implanted. The portion 312 serves as a boundary cleave and peels off the single crystal substrate 3 1 0. In addition, the heat treatment is not particularly limited, and the single crystal may be annealed by using a laser irradiation or a lamp including a peak temperature of about 700 ° C or more. The temperature of the hydrogen ion implantation portion 312 of the silicon substrate 310 is raised to a temperature above the temperature at which hydrogen is released from the system.

2後，以等方性電漿蝕刻或濕式蝕刻，此處為緩衝氟酸 之濕式蝕刻，藉由約20 nm輕微蝕刻除去經剝離而殘留於絕 緣基板3〇1上之單晶矽基板表面之損傷層。藉此，於絕緣基 板301上分別獲得膜厚約5〇 nm之多晶矽薄膜3〇4與單晶矽 薄膜 305。（圖 11(d))。 另外，於上數接合步驟（參照圖11(〇)中，在室溫下接合 單晶矽基板31〇後，以300〜35(rc，約3〇分鐘熱處理後，進 一步以約550X：熱處理而剝離時，隨剝離之剝落減少。After that, the isotropic plasma etching or wet etching is used. Here is the wet etching of buffered fluoric acid. The single crystal silicon substrate remaining on the insulating substrate 301 after peeling is removed by light etching at about 20 nm. Damage layer on the surface. Thereby, a polycrystalline silicon thin film 304 and a single-crystalline silicon thin film 305 with a film thickness of about 50 nm were obtained on the insulating substrate 301, respectively. (Figure 11 (d)). In addition, in the first bonding step (refer to FIG. 11 (0), the single crystal silicon substrate 31 is bonded at room temperature, and then heat-treated at 300 to 35 (rc, about 30 minutes), and further processed at about 550X: When peeling, peeling with peeling decreases.

此外，此時已可獲得足夠之石夕與基板的接合強度，不過 為求進一步提高接合強度，如而後以約8〇〇。〇進行丨分鐘燈 退火即可。此亦可與源極沒極之植人雜質的活化合併。 其次’保留構成裝置之活性區域的部分，藉由蝕刻除去 不需要之矽薄膜304, 305，而獲得島狀圖案（圖n(e))。 繼續，使用TEOS與氧（〇2)之混合氣體，藉由p_cvD法， 堆積膜厚約350 nm之氧化矽膜（回蝕用氧化矽膜），以異 性I虫刻之RIE(反應性離子姓刻）予以則虫約4〇〇麵。而後 使用矽烷與-氧化二氮之混合氣體，肖由^㈣法，形 膜厚約60 nm之閘極氧化膜306(氧化矽膜）（圖^⑴）。 -61 - 200306002 (57) 發明說明續頁 —；—____ 此日守，形成之多晶矽薄膜304與單晶矽薄膜3〇5之圖案間 的空間小時，階差被埋入，大時則形成側壁。 而後，藉由一般熟知之p-矽（多晶矽）形TFT矩陣基板之形 成製程相同的製程形成即可。亦即，形成包含多晶矽、矽 化物或聚化物等之閘極321後，植入p +及B +離子，堆積層間 絕緣膜（氧化矽膜）322，開設接觸孔323(圖11(§))。而後， 於接觸孔323内形成金屬（矽化鋁）配線324(圖u(h))。 另外，將形成於絕緣基板301之單晶矽薄膜3〇5與多晶矽 薄膜304予以蝕刻圖案化成島狀而形成M〇s電晶體，^^型 MOS電晶體及1&gt;型％03電晶體之源極及汲極區域之至少一 部分内植入約l〇15/cm2以上之P +離子。藉此，繼續藉由瞬間 熱退火（Rapid Thermal Annea卜以下稱RTA)、雷射、爐等 進行加熱處理，除多晶矽薄膜304區域外，單晶矽薄膜3〇5 區域亦同時藉由除去金屬原子，可獲得特性變動小而特性 穩定之TFT。 繼績，於液晶顯示用上進一步依序形成SiNx(氮化矽）、樹 脂平坦化膜、連通孔、及透明電極，於多晶矽薄膜3〇4區域 形成驅動器及顯示部用之T F T，於單晶矽薄膜3 〇 5區域形成 時間控制器及微處理器等。 再者’上述之使單晶矽基板3 1 〇密著接合於絕緣基板3 〇工 後，藉由熱處理自絕緣基板301劈開剝離單晶矽基板31〇時 (參照圖11(c)、圖11(d))，接合、劈開剝離是否良好係依絕 緣基板3 01之材料而定。 以下’係依據圖1 6，說明單晶矽基板3 1 〇之材料（Si . -62- 200306002 (58) 發明說明續頁In addition, at this time, sufficient bonding strength between Shixi and the substrate has been obtained, but in order to further increase the bonding strength, it is about 800. 〇 Perform 丨 minute lamp annealing. This can also be combined with the activation of implanted impurities at the source. Secondly, the portion constituting the active area of the device is retained, and unnecessary silicon thin films 304 and 305 are removed by etching to obtain an island pattern (Fig. N (e)). Continuing, using a mixed gas of TEOS and oxygen (〇2), p_cvD method was used to deposit a silicon oxide film (silicon oxide film for etch back) with a film thickness of about 350 nm, and a RIE (reactive ion surname) etched by the opposite sex (Engrave) was given about 400 faces. Then, a mixed gas of silane and -nitrogen oxide was used to form a gate oxide film 306 (silicon oxide film) with a film thickness of about 60 nm (Fig. ^ ⑴). -61-200306002 (57) Description of the Invention Continued —; — ____ On this date, when the space between the pattern of the polycrystalline silicon film 304 and the single crystal silicon film 305 is small, the step difference is buried, and when it is large, the sidewall is formed . Then, it can be formed by the same process as the formation process of a generally known p-silicon (polycrystalline silicon) TFT matrix substrate. That is, after forming the gate 321 including polycrystalline silicon, silicide or polymer, p + and B + ions are implanted, an interlayer insulating film (silicon oxide film) 322 is deposited, and a contact hole 323 is opened (FIG. 11 (§)). . Then, a metal (aluminum silicide) wiring 324 is formed in the contact hole 323 (FIG. U (h)). In addition, the monocrystalline silicon thin film 305 and polycrystalline silicon thin film 304 formed on the insulating substrate 301 were patterned into an island shape by etching to form a Mos transistor, a source of a ^ type MOS transistor, and a 1 &gt; type% 03 transistor. P + ions of about 1015 / cm2 or more are implanted in at least a part of the pole and drain regions. In this way, heat treatment is continued by rapid thermal annealing (hereinafter referred to as RTA), laser, furnace, etc. In addition to the polycrystalline silicon film 304 region, the single crystal silicon film 305 region is also removed by removing metal atoms at the same time. , TFTs with small variation in characteristics and stable characteristics can be obtained. Following the achievements, SiNx (silicon nitride), resin planarization film, communication holes, and transparent electrodes were sequentially formed on the liquid crystal display. The driver and display TFTs were formed on the polycrystalline silicon thin film 304 area. The silicon film 305 area forms a time controller and a microprocessor. Furthermore, when the single-crystal silicon substrate 3 1 0 is tightly bonded to the insulating substrate 3 as described above, the single-crystal silicon substrate 31 is cleaved and peeled from the insulating substrate 301 by heat treatment (see FIG. 11 (c), FIG. 11). (d)) Whether the bonding, cleaving and peeling are good depends on the material of the insulating substrate 301. The following ′ explains the material of the single crystal silicon substrate 3 1 〇 according to FIG. 16 (Si. -62- 200306002 (58) Invention Description Continued

Silicon)、上述絕緣基板301之材料（codel737(c〇NING公司 製））、及包含鋇-硼矽酸剝離之c〇de7059(CONING公司製） 經規格化的線膨脹（△L/L)。另外，所謂規格化之線膨脹（以 下稱線膨脹），係指因溫度變化引起之長度變化（ppm)。亦 即’ L為原長度，△ l為延伸後（變化後）之長度。 因而’〇〇心1737之線膨脹係數（。〇-1)於約600^：以下大致 一定’ code 1 73 7與矽之線膨脹幾乎無差異，在室溫（約2yc (圖16中顯示約100。〇以上》至約600°c之範圍内，線膨脹差 異約在250 ppm以内。 另外，code7059於約6〇(TC時，線膨脹係數急遽增加， code705 9與石夕之線膨脹差於約6〇〇°c時變大至約8〇〇 ppm。 因而於絕緣基板3 01上使用c〇de7059時，即使可與使用 c〇del737同樣地接合，劈開剝離的成功率極低。亦即，劈 開剝離時，引起單晶矽基板31〇的破壞、接合界面的剝離或 於結晶中發生缺陷。 口而，'纟巴緣基板3 01之材料，係使用大致在室溫以上，且 =在6〇0。(：以下之溫度範圍内接合之材料’此處係使用與單 晶矽基板310之材料（矽）之線膨脹差約在25〇 ppm以下者。 此時之線膨脹予以規格化。 此外，考慮施加於單晶矽薄膜3〇5之接合界面的應力。此 時係以顯微制曼測定裝置（如此時係日本分光股份有限公 司製之NR] 800U)測定單晶石夕薄膜3〇5的〇刺曼偏差。此時制 曼峰值之偏差量為 520.52 cm-i(kayser)，σ = 〇 l2 cnrl。因 此，瞭解單晶矽薄膜3〇5上並未施加應力。 -63 - 200306002 (59) Γ~—-- _說明續頁 ，常；使用雷射結晶生長時1曼峰值之偏差量殘留約 J CHT (相當K1〇9Pa)之大的應力。 另外，由於單晶石夕基板310係經由氧化石夕膜在室溫下接合 於玻璃基板等之絕緣基板3G1，因此可使施加於接合之石夕界 :的應力實質上幾乎為零。亦即，藉由使制曼峰值之偏差 置在520.5± 1(519.5〜521.5)^1的範圍，施加於接合之石夕界 面的應力實質上幾乎為零。 藉此，與使用雷射使矽膜結晶生長時之TFT比較，可進一 步確實防止因施加於界面之應力的不均一及變動造成石夕結 晶應變而引起之移動率降低及變動，或是界面之缺陷及隨 半-之界面固疋電荷、界面之局部位準造成之臨限值偏差 及變動、特性穩定性降低等。 另外，本實施形態中增加氫離子之植入能量，加深氫原 子之峰值位置，增加單晶矽薄膜3〇5之膜厚時，於nm〜1〇〇 nm時雖無大的變化，但是增加至3〇〇 nm〜6〇〇 ^^時，通道 邛未旎完全耗盡化，因此，丁打之8值（次臨限值係數）逐漸 變大，且斷開電流顯著增加。 口此，單aa石夕薄膜3 〇 5之膜厚雖亦與通道部之雜質摻雜密 度有關’但是考慮對變動之餘裕，須大致在6〇〇 nm以下， 並宜在約500 nm以下，更宜在1〇〇 nm以下。 此外’先前之形成於多晶矽區域之TFT的移動率（載體移 動率）約為100 cm2/V · sec(N通道），而該液晶顯示用主動矩 陣基板320中，形成於單晶矽區域之TFT則可獲得約550 cm2/V · sec(N通道）的移動率。 -64- 200306002 發明說明續頁 ------ 再者’藉由該液晶顯示用主動矩陣基板32〇,驅動器原本 形成於多晶矽薄膜304區域之裝置需要7〜8 V之訊號與電源 電壓’但是形成於單晶矽薄膜3 〇 5區域之裝置之時間控制器 及微處理器只須3.3 V即可穩定地動作。 另卜。亥液曰“、、員示用主動矩陣基板32〇中，藉由電晶體形 成於多晶矽薄膜304區域與單晶矽薄膜3〇5區域内，形成於 各個區域之同一導電型之電晶體之移動率、次臨限值係數 U艮值中之至少一個於各區域不同。因而可因應必要之 特性而形成於適合電晶體的區域内。 ，此外’該液晶顯示用主動矩陣基板32〇中，藉由積體電路 形成於多晶矽薄膜304區域與單晶矽薄膜3〇5區域内，可因 應必要之構造及特性而形成於適合積體電路的區域内，形 成於各個區域内之積體電路中，當然可製作動作速度及動 作電源電壓等不同性能的積體電路。亦即，可設計成各區 域之閘長、閘極氧化膜之膜厚、電源電壓、邏輯位準中之 至少一個不同。 夕X液日日顯示用主動矩陣基板32〇中，藉由積體電路形成於 :曰b矽薄膜304區域與單晶矽薄膜3〇5區域内，形成於各個 區域之積體電路可適用各區域不同之加工原則。此因，特 別於紐之通道長時，單晶部分無結晶粒場，tft特性之變 動成乎不增加，而多晶部分受到結晶粒場之影響，變動急 遽地私加’因此各個部分需要改變加工原則。因而可因應 加工原則形成於適合積體電路的區域内。 另外’本發明可獲得之單晶矽區域尺寸雖受限於LSI製造 -65- 200306002 (61) -^ 發明說明續頁 裝置之晶圓尺寸’不過只須為於形成要求單晶石夕區域必要 =速性、耗電及變動之高速邏輯、時間產生器、高速之 DAC(電流緩衝器）等時之足夠尺寸即可。 此外，單晶石夕薄膜305之膜厚與多晶石夕薄膜3〇4之 致相等。 藉此，可同時處理包含島狀圖案飯刻之以後步驟的大部 T步驟，且可形成階差小之電晶體或電路。藉此，如為液 日日面板時’單元厚度控制性佳。 p再者，主動矩陣基板32〇中，形成於多晶石夕區域（多晶石夕 薄膜04上）及單曰a矽區域（單晶矽薄膜奶）之的閘長分 別為5微米、〇.8微米，閘極氧化膜厚分別為8〇麵、％職 ’電源電壓分別以8V、3 Μ動作時可敎地動作。 另外，於多晶矽區域内形成閘長為〇·8微米之tft，並以3 v 動作T TFT之特性變動’源極〜汲極間之耐壓不足，往 往不能使用。 此外於夕B日石夕區域内形成閘長為i. 5微米之TFT，並以3 V 動作時，臨限值電壓及其變動大’實用上有問題。 〔弟十種實施形態〕 依據圖12(a)至圖12(h)說明本發明另外一種實施形態如 下。另外，本實施形態中具有與第九種實施形態之構成要 素相同功能之構成要素，註記相同符號，並省略其說明。 圖12(a)至圖12(h)顯示本實施形態之主動矩陣基板33〇 (半導體裝置）之一種製造步驟。如圖丨2(11)所示，本主動矩 陣基板330具備：絕緣基板3〇1、氧化矽（Si〇j膜332，311， -66- (62) 200306002 發明說明續頁 5夕a日石夕薄膜337、單晶矽薄膜334、閘極氧化膜33 8、 閘極321、層間絕緣膜322、及金屬配線324。此外，主動矩 陣基板330具備切換元件之薄膜電晶體（TFt · fnm transistor) 〇 於與第九種實施形態同樣之絕緣基板3〇1表面上，大致全 面地形成有氧化矽膜（第一氧化矽膜）332。氧化矽膜Μ〕之 膜厚約為350 nm。 ' 於乳化矽膜332上形成有氧化矽膜（絕緣膜）335及氧化矽 膜3U。氧化矽膜335之膜厚約為1〇〇nm。氧化矽膜η〗在氧 :夕膜332上’於與氧化梦膜335不同的區域以形成島狀圖 案之方式形成’其膜厚約為2〇〇nm。 於氧化石夕膜335上，進-步以形成島狀圖案之方式形成有 多晶石夕薄膜337。乡曰曰曰石夕薄膜337之膜厚約為5〇 _。 氧化石夕膜332於與多晶石夕薄膜337區域不同的區域内具有 凹部333，其具有約15〇賊之深度（參照圖匕⑷卜凹部奶 内’以島狀圖案之方切成有上述氧切膜⑴，進—步於 其上形成f與氧化矽膜311相同形狀之單晶矽薄膜334。、 夕曰曰石夕薄膜337之區域與單晶石夕薄膜说之區域至少分離 I·3 _，尤宜分離〇.5 μηι以上。藉此防止H錫、@ 等金屬原子擴散於單晶矽區域，促進特性穩定化。 ::個氧化矽膜332、多晶矽薄膜337及單晶矽薄膜334上 开乂成有膜厚約60 nm之閘極氧化膜336。 多晶=薄膜337及單晶石夕薄膜334之各島狀圖案區域上面 之閘極氧化膜336上形成有閘極321。 一 -67- 200306002 (63) 發明說明續頁 此外’與主動矩陣基板320同樣地，形成有層間絕緣膜322 、接觸孔323(參照圖12(g))、及金屬配線324。此外，亦同 樣地’主動矩陣基板320於液晶顯示用上形成有8：^&amp;(氮化 矽）、樹脂平坦化膜、連通孔、及透明電極，於多晶矽區域 形成有驅動器及顯示部用之TFT，於單晶矽區域形成有時 間控制器及微處理器等。 以下’依據圖12(a)〜圖12(h)說明主動矩陣基板330之製造 方法。 首先，於包含c〇del737(CONING公司製）之絕緣基板301 的整個表面上，使用TEOS(四乙氧基矽烷，亦即Si(OC2H5)4) 與氧之混合氣體，藉由p_CVD堆積膜厚約35〇 nm之氧化矽 膜332。而後，藉由蝕刻約15〇 nm氧化矽膜332之特定區域 而形成凹部333(圖12(a))。 另外，準備單晶矽基板310。單晶矽基板310預先藉由氧 化表面或堆積氧化膜（氧化矽膜）形成有膜厚約2〇〇 nm之氧 化矽膜311。此外，單晶矽基板31〇具有以特定能量植入有 5&gt;&lt;1016/〇1112劑量之氫離子之氫離子植入部312，硼約摻雜 3 X 1 〇15cm&quot;3 ° 而後，藉由切割或KOH等之異方性蝕刻等切斷單晶矽基 板310成比凹部333至少小〇·3 μιη，更宜小〇·5 μιη以上的形 狀。 繼續’以微粒子除去與表面活化用之SC-丨洗淨形成有凹 部333之絕緣基板301與單晶矽基板3 1〇之兩基板後，以室溫 使罪近切斷之單晶矽基板3 1〇之氫離子植入部3 12侧的表面 -68- 200306002 (64) 發明說明續頁 密著接合於凹部333(圖12(b))。 而後，以3〇〇°C〜60(TC，此處以約55〇°C之溫度進行熱處 理’使單晶矽基板310之氫離子植入部312的溫度昇溫至氫 自矽脫離之溫度以上。藉此以氫離子植入部3 12為邊界劈開 剝離單晶矽基板3 1 0。 以等方性電漿蝕刻或濕式蝕刻，此處為緩衝氟酸之濕式 蝕刻，藉由約1 〇 nm輕微蝕刻除去經剝離而殘留於絕緣基板 301上之單晶矽基板表面之損傷層。藉此，於絕緣基板 上獲侍各個膜厚約5〇 nm之單晶矽薄膜334。（圖12〇)) ^、、麄項於整個絕緣基板3 0 1表面上，使用矽烷與一氧化二 氮1混合氣體，藉由P-CVD法，堆積膜厚約1〇〇麵之氧化 矽膜335，作為閘極氧化膜3〇6，進一步於其大致整個表面 上使用石夕㈣體，藉由P-CVD法，堆積膜厚約5〇麵之非晶 質矽膜336(圖12(d))。 曰=後，非晶詩膜336上照射準分子雷料以加熱，將非 曰曰貝矽予以晶化，使多晶矽層生長，而形成多晶矽薄膜切 。猎由該加熱可促使單晶矽薄膜334之接合強度提高。 其次’藉由I虫刻除去吝a石々嘀H替。。、 4 1于、云夕日日矽溥胰337之不需要部分與氧 石夕膜335之至少單晶矽薄膜 壯 、 寻胰34上之邛刀。而後，保留構成 衣置之活性區域的部分，莊cb 4古丨rt/v丄 精由蝕刻除去不需要之矽膜而形 成島狀圖案（圖12(e))。 而後，使用TEOS與氧之、、曰入今棘 —， 、虱之/吧&amp;虱體，猎由P-CVD法，堆鈐 搞厚約350 nm之氧化矽膜显 積 /lnA 胰以異方性蝕刻之RIE予以回蝕幼 400 nm。而後，使用矽烷盥一 '、、勺 /汍共乳化一虱之混合氣體，藉由 -69- 200306002 (65) 發明說明續頁 P-CVD法，形成膜厚約6〇nm之閘極氧化膜338(圖i2(f))。 此日^ ’形成之多晶矽薄膜334與單晶矽薄膜337之圖案間 的空間小時階差被埋入，大時則形成側壁。 爾後，與第九種實施形態同樣地形成閘極32 i、層間絕緣 膜（氧化矽膜）322，開設接觸孔323(圖12(g))後，於接觸孔 323内形成金屬配線324(圖12(h))。 先珂之形成於多晶矽區域之N通道TFT的移動率約為100 cm2/V· sec，而該主動矩陣基板mo中，形成於單晶矽區域 之N通道TFT則可獲得約550 cm2/V · sec的移動率。 主動矩陣基板330中，驅動器原本形成於多晶矽薄膜337 區或之衣置舄要7〜8 V之訊號與電源電壓，但是形成於單晶 矽薄膜334區域之裝置之時間控制器及微處理器只須3.3 v 即可穩定地動作。 〔第十一種實施形態〕 依據圖13(a)至圖13(f)說明本發明另外一種實施形態如 下。另外，本實施形態中具有與第十種實施形態之構成要 素相同功能之構成要素，註記相同符號，並省略其說明。 圖13 (a)至圖13 (f)顯示本實施形態之主動矩陣基板（半導 體裝置）之一種製造步驟。如圖13⑴所示，本主動矩陣基板 具備·絕緣基板301、氧化矽（Si〇2)膜362，3n，335、多晶 矽薄膜367、單晶矽薄膜364、及閘極氧化膜368。此外，該 主動矩陣基板與上述第九、十種實施形態同樣，具備：圖 上未顯示之薄膜電晶體（TFT : thln fllm transist〇r)、閘極、 層間絕緣膜、及金屬配線。 -70- 200306002 (66) Π~~-—— 發明說明續頁 於與第十種實施形態同樣之絕緣基板3〇i表面上，大致全 =形成有包含氧切之氧切膜（第—氧化㈣）362。氧 化石夕膜3 62之膜厚約為5〇11111。 、，/M362上形成有氧切膜（絕緣膜）335及氧化与 版3U。氧切膜335之膜厚約為⑽咖。氧切膜3ιι在氧 ^石夕版362上’於與氧切膜335不同的區域以形成島狀圖 荼之方式形成，其膜厚約為2〇〇nm。Silicon), the material of the above-mentioned insulating substrate 301 (codel737 (manufactured by Cooning Corporation)), and cod 7059 (manufactured by Coning Co., Ltd.) including barium-borosilicate peeling, and standardized linear expansion (ΔL / L). The normalized linear expansion (hereinafter referred to as linear expansion) refers to the change in length (ppm) due to temperature changes. That is, 'L is the original length, and Δl is the length after extension (after change). Therefore, the linear expansion coefficient (.〇-1) of '〇〇 心 1737 is about 600 ^: the following is approximately constant' code 1 73 7 and silicon linear expansion have almost no difference at room temperature (about 2yc (Figure 16 shows about In the range of 100% or more> to about 600 ° C, the difference in linear expansion is within 250 ppm. In addition, the linear expansion coefficient of code7059 increases sharply at about 60 ° C, and the linear expansion of code705 9 and Shixi is worse than It becomes as large as about 8000 ppm at about 600 ° C. Therefore, when code 7059 is used on the insulating substrate 301, the success rate of cleaving and peeling is extremely low, even if it can be joined in the same way as co de 737. When splitting and peeling, the single crystal silicon substrate 31 is destroyed, the bonding interface is peeled off, or a defect occurs in the crystal. In addition, the material of the 纟 ba edge substrate 3 01 is used at approximately room temperature and above. 600. (: The materials bonded in the following temperature range 'here is the linear expansion difference between the material (silicon) of the single crystal silicon substrate 310 is less than about 25 ppm. The linear expansion at this time is standardized. In addition, consider the stress applied to the junction interface of the single crystal silicon film 305. At this time The micromanganese measuring device (in this case, NR] 800U manufactured by Japan Spectrum Co., Ltd. was used to measure the zero manganese deviation of the single crystal evening film 305. At this time, the deviation of the manganese peak was 520.52 cm-i. (kayser), σ = 〇l2 cnrl. Therefore, it is understood that no stress is applied to the single crystal silicon thin film 305. -63-200306002 (59) Γ ~ ------ _Describe the continuation page, often; use laser crystal growth At the time, the deviation of the 1-man peak has a stress of approximately J CHT (equivalent to K109 Pa). In addition, the single crystal substrate 310 is an insulating substrate 3G1 that is bonded to a glass substrate or the like at room temperature through a stone oxide film. Therefore, the stress applied to the bonded Shi Xijie: the stress is almost zero. That is, by setting the deviation of the peak value in the range of 520.5 ± 1 (519.5 ~ 521.5) ^ 1, the stress applied to the bonded The stress on the Shi Xi interface is practically zero. By this, compared with the TFT when a silicon film crystal is grown using a laser, the Shi Xi crystal strain caused by unevenness and variation of the stress applied to the interface can be further prevented. Decrease and change of mobile rate, or interface defects and The semi-interfacial solid charge, the threshold deviation and variation caused by the local level of the interface, and the decrease in characteristic stability, etc. In addition, in this embodiment, the implantation energy of the hydrogen ion is increased, the peak position of the hydrogen atom is deepened, and the increase When the film thickness of the single crystal silicon thin film is 305, there is no significant change between nm and 100 nm, but when it is increased to 300 nm to 600 ^^, the channel 邛 is not completely depleted. Therefore, the 8 value of the tinkerer (sub-threshold value coefficient) gradually increases, and the off current increases significantly. At this point, although the film thickness of the single aa Shixi thin film 305 is also related to the impurity doping density of the channel portion, but considering the margin for variation, it must be approximately 600 nm or less, and preferably 500 nm or less. More preferably, it is below 100 nm. In addition, the mobility (carrier mobility) of the TFT formed in the polycrystalline silicon region was about 100 cm2 / V · sec (N channel), and the TFT in the active matrix substrate 320 for the liquid crystal display was formed in the monocrystalline silicon region. A traverse rate of about 550 cm2 / V · sec (N channel) can be obtained. -64- 200306002 Description of the Invention Continued ------ Furthermore, 'With the active matrix substrate 32 for liquid crystal display, the device originally formed in the polycrystalline silicon thin film 304 area requires a signal and a power voltage of 7 to 8 V' However, the time controller and the microprocessor of the device formed in the 305 region of the single-crystal silicon film need only 3.3 V to operate stably. Another Bu. In the liquid crystal active matrix substrate 32, the liquid crystal is formed in the polycrystalline silicon thin film 304 region and the single crystal silicon thin film 305 region by the transistor, and the transistors of the same conductivity type are formed in each region. At least one of the coefficient and the subthreshold coefficient Ugen value is different in each region. Therefore, it can be formed in a region suitable for a transistor according to necessary characteristics. In addition, the active matrix substrate 32 for the liquid crystal display is borrowed. The integrated circuit is formed in the polycrystalline silicon thin film 304 region and the single crystal silicon thin film 305 region, and can be formed in the region suitable for the integrated circuit according to the necessary structure and characteristics, and formed in the integrated circuit in each region. Of course, integrated circuits with different performances such as operating speed and operating power supply voltage can be produced. That is, it can be designed so that at least one of the gate length, gate oxide film thickness, power supply voltage, and logic level is different in each area. The X liquid day-to-day active matrix substrate 32 is formed by integrated circuits in the silicon region 304 and the single crystal silicon region 305, and the integrated circuits are formed in each region. Different processing principles apply in each region. This is because, especially when the channel is long, there is no crystal grain field in the single crystal part, and the change in tft characteristics does not increase, while the polycrystalline part is affected by the crystal grain field, which changes rapidly. Privately, therefore, the processing principle needs to be changed in each part. Therefore, it can be formed in a region suitable for integrated circuits according to the processing principle. In addition, although the size of the single crystal silicon region obtainable by the present invention is limited by LSI manufacturing-65- 200306002 (61 )-^ Description of the invention The wafer size of the continuation device 'is only necessary for the formation of a single crystal region, which is necessary = high speed logic, power consumption and change of high speed logic, time generator, high speed DAC (current buffer) Sufficient size is sufficient at the same time. In addition, the film thickness of the monocrystalline stone thin film 305 is equal to that of the polycrystalline silicon thin film 304. By this, most of the subsequent steps including the island-shaped pattern rice carving can be processed at the same time. In step T, a transistor or circuit with a small step difference can be formed. Thereby, if the liquid-day panel is used, the cell thickness is controlled. P Furthermore, the active matrix substrate 32 is formed in a polycrystalline silicon region. (many On Shixi film 04) and the gate length of the single silicon region (single-crystal silicon film milk) are 5 micrometers and 0.8 micrometers, respectively, and the gate oxide film thickness is 80 planes. When operating at 8V and 3M, it can be operated in a quiet manner. In addition, a tft with a gate length of 0.8 micron is formed in the polycrystalline silicon region, and the characteristics of the T TFT are changed by operating at 3v. In addition, a TFT with a gate length of i. 5 microns is formed in the area of Shixi on the B day, and the threshold voltage and its variation are large when operating at 3 V. There are practical problems. Embodiment] Another embodiment of the present invention will be described below with reference to Figs. 12 (a) to 12 (h). In addition, in this embodiment, components having the same functions as those of the ninth embodiment are marked with the same symbols, The description is omitted. 12 (a) to 12 (h) show a manufacturing step of the active matrix substrate 33o (semiconductor device) according to this embodiment. As shown in Figure 2 (11), the present active matrix substrate 330 is provided with: an insulating substrate 301, a silicon oxide (SiOj film 332, 311, -66- (62) 200306002 Description of the invention, continuation page, 5th a) Even film 337, single crystal silicon film 334, gate oxide film 33 8, gate 321, interlayer insulating film 322, and metal wiring 324. In addition, the active matrix substrate 330 includes a thin film transistor (TFt · fnm transistor) of a switching element. 〇A silicon oxide film (first silicon oxide film) 332 is formed on the surface of the insulating substrate 301 which is the same as the ninth embodiment, and the film thickness of the silicon oxide film M is approximately 350 nm. A silicon oxide film (insulating film) 335 and a silicon oxide film 3U are formed on the emulsified silicon film 332. The film thickness of the silicon oxide film 335 is about 100 nm. The silicon oxide film η is on the oxygen: evening film 332. Different regions of the oxide film 335 are formed in the manner of forming an island pattern, and the film thickness is about 2000 nm. On the oxide stone film 335, polycrystalline stones are further formed in the manner of forming an island pattern. Thin film 337. The film thickness of the stone xi film 337 is about 50 °. The oxidized stone film 332 and polycrystalline stone There are recesses 333 in different areas of the film 337 area, which has a depth of about 150. (Refer to the figure. The inside of the recessed milk is cut into the above-mentioned oxygen-cut membrane in the shape of an island pattern. A single-crystal silicon thin film 334 having the same shape as that of the silicon oxide film 311 is formed. A region of the slab film 337 and a region of the single-crystal slab film are separated by at least I · 3 _, and more preferably separated by 0.5 μηι or more. . This prevents metal atoms such as H tin and @ from diffusing in the single crystal silicon region, and promotes the stabilization of characteristics. :: A silicon oxide film 332, a polycrystalline silicon film 337, and a single crystal silicon film 334 are opened to a thickness of about 60 nm. Gate oxide film 336. Polycrystalline film 337 and single crystal stone film 334 have gate electrodes 321 formed on the gate oxide film 336 on each island-like pattern region. I-67- 200306002 (63) Description of the invention continued In addition, as in the active matrix substrate 320, an interlayer insulating film 322, a contact hole 323 (see FIG. 12 (g)), and a metal wiring 324 are formed. In addition, the active matrix substrate 320 is also used for a liquid crystal display in the same manner. 8: ^ &amp; (silicon nitride), resin flattening film, communication And transparent electrodes, a driver and a display TFT are formed in the polycrystalline silicon region, and a time controller and a microprocessor are formed in the monocrystalline silicon region. The following description will be based on FIG. 12 (a) to FIG. 12 (h). Manufacturing method of the matrix substrate 330. First, a mixed gas of TEOS (tetraethoxysilane, that is, Si (OC2H5) 4) and oxygen is used on the entire surface of an insulating substrate 301 including codel 737 (manufactured by CONING). A silicon oxide film 332 having a film thickness of about 35 nm is deposited by p_CVD. Then, a specific region of the silicon oxide film 332 of about 150 nm is etched to form a recessed portion 333 (Fig. 12 (a)). In addition, a single crystal silicon substrate 310 is prepared. The single crystal silicon substrate 310 is previously formed with a silicon oxide film 311 having a thickness of about 200 nm by oxidizing the surface or depositing an oxide film (silicon oxide film). In addition, the single crystal silicon substrate 31 has a hydrogen ion implantation portion 312 implanted with 5 &lt; 1016 / 〇1112 dose of hydrogen ions at a specific energy, and boron is doped approximately 3 X 1 015 cm &quot; The single crystal silicon substrate 310 is cut by dicing, anisotropic etching such as KOH or the like to have a shape that is at least 0.3 μm smaller than the concave portion 333, and more preferably 0.5 μm or smaller. Continue 'SC- 丨 for fine particle removal and surface activation. After cleaning the two substrates, the insulating substrate 301 having the recessed part 333 and the single-crystal silicon substrate 3 10, the single-crystal silicon substrate 3 is cut off at room temperature. The surface of the 12 side of the 10 hydrogen ion implantation part 3 -68- 200306002 (64) Description of the invention The continuation sheet is tightly joined to the recessed part 333 (Fig. 12 (b)). Then, heat treatment is performed at 300 ° C. to 60 ° C. (here, at a temperature of about 55 ° C.) to raise the temperature of the hydrogen ion implantation portion 312 of the single crystal silicon substrate 310 to a temperature at which hydrogen is released from the silicon. With this, the single-crystal silicon substrate 3 1 0 is cleaved and stripped by using the hydrogen ion implantation portion 3 12 as a boundary. The isotropic plasma etching or wet etching is used here, and the wet etching of buffered fluoric acid is performed by about 1 〇 The nm slightly etched away the damaged layer on the surface of the single crystal silicon substrate that was left on the insulating substrate 301 after being stripped. As a result, the single crystal silicon thin film 334 with a thickness of about 50 nm was served on the insulating substrate. (Figure 12) )) ^, And 麄 on the entire surface of the insulating substrate 301, using a mixture of silane and nitrous oxide 1 gas, by P-CVD method, a silicon oxide film 335 with a thickness of about 100 planes was deposited as The gate oxide film 306 further uses a stone sintered body over substantially the entire surface thereof, and an amorphous silicon film 336 having a thickness of about 50 planes is deposited by a P-CVD method (FIG. 12 (d)). After that, the amorphous poetry film 336 is irradiated with excimer lightning to heat, and the non-crystalline silicon is crystallized to grow the polycrystalline silicon layer to form a polycrystalline silicon thin film. This heating can promote the bonding strength of the single crystal silicon film 334. Secondly, 吝 a stone 々 嘀 H is removed by I insect cutting. . , 4 1 Yu, Yun Xi Ri Ri silicon pancreas 337 needless part and oxygen stone Xi film 335 at least single crystal silicon thin film, looking for the trowel on the pancreas 34. Then, the part that constitutes the active area of the garment is retained, and the Cb 4 rt / v 丄 is removed by etching to remove the unnecessary silicon film to form an island pattern (Fig. 12 (e)). Then, using TEOS, oxygen, and entrapment into the current spine—, and the lice / amp; lice body, the P-CVD method was used to pile up a silicon oxide film with a thickness of about 350 nm / lnA. The square etching RIE etched back 400 nm. Then, a mixed gas of silane, Scoop, and scoop was used to emulsify the lice, and a gate oxide film with a film thickness of about 60 nm was formed by the P-CVD method of -69- 200306002 (65) Invention Description Continued. 338 (Figure i2 (f)). On this date, the small step difference between the pattern of the polycrystalline silicon thin film 334 and the single crystal silicon thin film 337 formed is buried, and when large, a sidewall is formed. Thereafter, the gate electrode 32 i, the interlayer insulating film (silicon oxide film) 322 are formed in the same manner as the ninth embodiment, and after the contact hole 323 (FIG. 12 (g)) is opened, a metal wiring 324 is formed in the contact hole 323 (FIG. 12 (h)). The movement rate of the N-channel TFT formed in the polycrystalline silicon region is about 100 cm2 / V · sec, and the N-channel TFT formed in the monocrystalline silicon region in the active matrix substrate mo can obtain about 550 cm2 / V · sec rate of movement. In the active matrix substrate 330, the driver was originally formed in the polysilicon thin film 337 area or the device was placed with a signal and power voltage of 7 ~ 8 V, but the device formed in the monocrystalline silicon thin film 334 area only had a time controller and a microprocessor. 3.3 v is required for stable operation. [Eleventh Embodiment] Another embodiment of the present invention will be described below with reference to Figs. 13 (a) to 13 (f). In addition, in this embodiment, the constituent elements having the same functions as the constituent elements of the tenth embodiment are denoted by the same reference numerals, and descriptions thereof are omitted. Figs. 13 (a) to 13 (f) show one manufacturing step of the active matrix substrate (semiconductor device) according to this embodiment. As shown in FIG. 13 (a), the active matrix substrate includes an insulating substrate 301, a silicon oxide (SiO2) film 362, 3n, 335, a polycrystalline silicon film 367, a single crystal silicon film 364, and a gate oxide film 368. In addition, the active matrix substrate is provided with a thin film transistor (TFT: thln fllm transistor) (not shown), a gate electrode, an interlayer insulating film, and metal wiring, as in the ninth and tenth embodiments described above. -70- 200306002 (66) Π ~~ -—— The description of the invention is continued on the surface of the insulating substrate 30i which is the same as the tenth embodiment. ㈣) 362. The thickness of the oxidized oxidized membrane 3 62 is about 5011111. An oxygen cutting film (insulating film) 335 and an oxidation and plate 3U are formed on /, / M362. The film thickness of the oxygen-cut film 335 is about ⑽ coffee. The oxygen-cut film 3m is formed on the oxygen-cut stone version 362 'in a region different from the oxygen-cut film 335 to form an island pattern, and the film thickness is about 200 nm.

於氧切膜311上，以形成島狀㈣之方式形成有與氧化 石夕膜3U相同形狀之單晶梦薄膜364。單晶發薄膜364之膜厚 約為loo nm。此外’於氧化石夕膜335上，以形成島狀圖案之 方式形成多晶梦薄膜367。多晶”膜367之膜厚約為5〇nm。 於整個氧化矽膜362、彡晶矽薄膜36?及單晶矽肖膜364上 形成有閘極氧化膜368。閘極氧化膜368之膜厚約為6〇·。 。再者，於多晶矽薄膜367及單晶矽薄膜364之各島狀圖案 區域上面之閘極氧化膜368上形成有圖上未顯示之閘極。閘 極係與第十種實施形態之主動矩陣基板330相同者，如包含 多晶石夕、石夕化物或聚化物等。On the oxygen-cut film 311, a single crystal dream film 364 having the same shape as that of the oxidized stone film 3U is formed so as to form island-shaped ridges. The film thickness of the single crystal thin film 364 is about loo nm. In addition, a polycrystalline dream film 367 is formed on the oxide stone film 335 so as to form an island pattern. The film thickness of the "polycrystalline" film 367 is about 50 nm. A gate oxide film 368 is formed on the entire silicon oxide film 362, a crystalline silicon film 36? And a single crystal silicon film 364. The film of the gate oxide film 368 The thickness is about 60... Further, a gate electrode not shown in the figure is formed on the gate oxide film 368 on each of the island-shaped pattern regions of the polycrystalline silicon thin film 367 and the single crystal silicon thin film 364. The active matrix substrate 330 of the ten embodiments is the same, for example, it includes polycrystalline stones, stone compounds or polymers.

此外，與主動矩陣基板33〇同樣地，形成有圖上未顯示之 層間絕緣膜、接觸孔、及金屬配線。此外，亦同樣地，於 液晶顯示用上形成有SiNx(氮化矽）、樹脂平坦化膜、連通 孔、及透明電極，於多晶矽區域形成有驅動器及顯示部用 之TFT，於單晶矽區域形成有時間控制器及微處理器等。 以下，依據圖13(a)〜圖13⑴說明上述之本實施形態之主 動矩陣基板之製造方法。 -71 - 200306002 (67) 發明說明續頁 首先，於包含C〇del737(CONING公司製）之絕緣基板301 的整個表面上，使用TE0S(四乙氧基矽烷，亦即Si(〇C2H5)4) 與氧之混合氣體，藉由P-CVD堆積膜厚約50 nm之氧化矽膜 362(圖 13(a))。 另外’準備預先切斷成適切形狀之單晶矽基板31〇。單晶 矽基板3 1 0預先藉由氧化表面或堆積氧化膜（氧化矽膜）形 成有膜厚約200 nm之氧化矽膜311。此外，單晶矽基板31〇 具有以特定能量植入有5x l〇16/cm2劑量之氫離子之氫離子 植入部312，硼約掺雜3xl〇15cm-3。 而後’以微粒子除去與表面活化用之SC-1洗淨絕緣基板 3 0 1與單晶石夕基板3 1 〇之兩基板予以活化後，以室溫使靠近 切斷之單晶矽基板3 1 〇之氫離子植入部3丨2側的表面密著接 合於絕緣基板301(圖13(b))。 而後，以30CTC〜600°C ,此處以約550它之溫度進行熱處 理’使單晶矽基板310之氫離子植入部312的溫度昇溫至氫 自矽脫離之溫度以上。藉此以氫離子植入部3丨2為邊界劈開 剥離早晶碎基板3 1 0。 以等方性電漿蝕刻或濕式蝕刻，此處為緩衝氟酸之濕式 蝕刻，藉由約20 nm輕微蝕刻除去經剝離而殘留於絕緣基板 301上之單晶矽基板表面之損傷層。藉此，於絕緣基板3〇1 上獲得膜厚約80 nm之單晶矽薄膜364(圖13(c))。 其次’於整個絕緣基板3 01表面上，使用石夕烧與一氧化二 氮之混合氣體，藉由P-CVD法，堆積膜厚約1〇〇 nm之氧化 矽膜335，進一步於其大致整個表面上使用矽烷氣體，藉由 -72- 200306002 p明說明續頁 P-CVD法，堆積膜厚約5〇證之非晶質石夕膜366(圖_))。 曰:後’非日^膜366上照射準分子雷射予以加熱，將非 。曰：夕;予以曰曰化’使多晶矽層生長，而形成多晶矽薄膜367 猎：σ亥加熱可促使單晶矽薄膜364之接合強度提高。 f次’保留多晶矽薄膜367中構成裝置之活性區域的部分 ’猎由蝕刻至少將單晶矽薄膜364上之部分除去包含不需要 部分的不需要部分，而形成島狀圖案(圖13(e))。 繼績’使用TEOS與氧之混合氣體，藉由p-CVD法，堆積 膜相350細之氧化石夕膜，進一步將約350 nm之光阻作為 _平坦化膜全面塗敷後’使用含氧與四說化碳之混合氣 體平坦化膜之全部與氧化賴335之一部 分。 、'而後，、使用矽烷與一氧化二氮之混合氣體，藉由P_CVD 去，形成膜厚約60nm之閘極氧化膜368(圖13⑴）。 爾後，與第九、十種實施形態同樣地，藉由一般熟知之 P-矽(多晶矽)形TFT矩陣基板之形成製程相同的製程形成 即可。亦即’形成包含多晶矽、矽化物或聚化物等之閘極 而後，植入P及B離子，堆積層間絕緣膜（氧化矽膜）， 開設接觸孔後，於接觸孔内形成金屬配線。 先前之形成於多晶矽區域之N通道tft的移動率約為丨〇〇 cm2/V · sec，而本實施形態之主動矩陣基板中，形成於單 晶矽區域之N通道TFT則可獲得約55〇cm2/v· sec的移動率。 該主動矩陣基板中，驅動器原本形成於多晶矽薄膜367區 域之裝置需要7〜8 V之訊號與電源電壓，但是形成於單晶石夕 -73- (69) (69)200306002 發明說明續頁 薄膜364區域之裝置之時間控制器及微處理器只須3·3 v即 可穩定地動作。 〔第十二種實施形態〕 依據圖14(a)至圖14(e)說明本發明另外一種實施形態如 下。另外’本實施形態中具有與第九種實施形態之構成要 素相同功能之構成要素，註記相同符號，並省略其說明。 本κ施形態之主動矩陣基板係於上述第九種實施形態之 主動矩陣基板320中，形成多晶矽薄膜343來取代多晶石夕薄 膜304，其他構造與主動矩陣基板32〇相同。以下僅說明與 主動矩陣基板320不同之處。 多晶石夕薄膜343包含於藉由金屬協助而促進結晶生長之 多晶石夕的所謂連續結晶粒場矽（Continu〇us Grain SilieQn)。 以下，依據圖14(a)〜圖14(e)說明使用上述多晶矽薄膜343 之主動矩陣基板的製造方法。 首先，於上述之包含c〇del737(CONING公司製）之絕緣基 板301的整個表面上，使用TE〇s(四乙氧基矽烷，亦即 Si(OC2H5)4)與氧（〇2)之混合氣體，藉由p-CvD法堆積膜厚 約100 nm之氧化矽膜302。 繼續，於氧化矽膜302上，藉由使用矽烷氣體之p_CVD&amp; 堆積膜厚約50 nm之非晶質矽膜303。而後於絕緣基板3〇ι 之大致整個表面上，藉由使用矽烷與一氧化二氮之混合氣 體之P-CVD法堆積膜厚約2〇〇 nm之氧化矽膜341(第二氧化 矽膜）。（圖 14(a))。 而後，於上層之氧化矽膜341之特定區域内藉由蝕刻形成 -74- 200306002 發明說明續頁 開口部後’為求控制該開口部之非晶質矽膜303表面的親水 性，將非晶質矽膜303表面輕微氧化而形成氧化矽膜“】， 在其上自旋塗敷醋酸鎳水溶液（圖14〇))。 其次，以600°C之溫度進行約12小時固g生長，藉由u 由金屬協助促進結晶生長之多晶奴所謂連續結晶粒場: (Continuous Grain Sllic〇n)生長，而形成膜厚約5〇㈣之多 晶=薄膜343。進-步除去多晶㈣膜343上之氧㈣膜341 及氧化膜342。而後蝕刻除去多晶矽薄膜343之特 (圖 14(c))。 — 另外，準備單晶石夕基板310。單晶石夕基板310預先藉由氧 化表面或堆疊氧化膜（氧化矽膜）而形成膜厚約2〇〇 nm之氧 化石夕膜3 11。此外，單晶石夕其把1彳n目士 、 平曰7基板310具有以特定能量（此處約 為 24keV)植入有 l〇16/cm2 u ,L ^ ^ Ί , ^伹喇υ /c®以上，此處45xl〇1Vcm2劑量之氕 離子之氫離子植入部312，硼約摻雜扒⑺〜化3。 工 而後，藉由切割或K0H等之異方㈣刻等切斷單晶石夕基 ㈣〇成比藉由_除去多㈣薄膜343之特定區域之形狀 至少小〇_3 ’，t宜小0·5 _以上的形狀。藉此，可防止 ，以後之多晶梦薄膜343製造步驟中使用之鎳、銘、錫、把 等金屬原子擴散於單晶石夕區域，促進特性之穩定化。 繼績，以微粒子除μ表面活化用之心洗淨形成有多 晶石崩343之基板與單晶石夕基板31〇之兩基板予以活化後In addition, similarly to the active matrix substrate 33, an interlayer insulating film, a contact hole, and a metal wiring not shown are formed. In addition, similarly, SiNx (silicon nitride), a resin planarization film, a communication hole, and a transparent electrode are formed on the liquid crystal display, a driver and a display TFT are formed in the polycrystalline silicon region, and a single crystal silicon region is formed. Formed with time controller and microprocessor. Hereinafter, a method for manufacturing the active matrix substrate according to the embodiment described above will be described with reference to Figs. 13 (a) to 13 (a). -71-200306002 (67) Description of the Invention Continued First, TEOS (tetraethoxysilane, that is, Si (〇C2H5) 4) is used on the entire surface of the insulating substrate 301 including Codel737 (manufactured by CONING). A mixed gas with oxygen is deposited on the silicon oxide film 362 with a film thickness of about 50 nm by P-CVD (FIG. 13 (a)). In addition, a single crystal silicon substrate 31 which is cut into a suitable shape in advance is prepared. The single crystal silicon substrate 3 10 is formed with a silicon oxide film 311 having a thickness of about 200 nm by oxidizing the surface or depositing an oxide film (silicon oxide film) in advance. In addition, the single crystal silicon substrate 31 has a hydrogen ion implantation portion 312 implanted with a specific energy at a dose of 5 × 10 16 / cm 2 of hydrogen ions, and boron is doped approximately 3 × 10 15 cm −3. Then, the SC-1 for cleaning and surface activation was used to clean both the insulating substrate 3 01 and the single crystal substrate 3 1 0, and then the single crystal silicon substrate 3 1 near the cut was activated at room temperature. The surface on the side of the hydrogen ion implantation section 3 and 2 is bonded to the insulating substrate 301 (FIG. 13 (b)). Then, heat treatment is performed at 30CTC to 600 ° C, here at a temperature of about 550 'to raise the temperature of the hydrogen ion implantation portion 312 of the single crystal silicon substrate 310 to a temperature at which hydrogen is released from the silicon. Thereby, the early-crystal broken substrate 3 1 0 is cleaved by using the hydrogen ion implantation portion 3 丨 2 as a boundary. By isotropic plasma etching or wet etching, here is buffered hydrofluoric acid wet etching, the damage layer on the surface of the single-crystal silicon substrate that is peeled off and left on the insulating substrate 301 is slightly etched by about 20 nm. Thereby, a single-crystal silicon thin film 364 with a film thickness of about 80 nm was obtained on the insulating substrate 301 (FIG. 13 (c)). Secondly, a silicon oxide film 335 having a thickness of about 100 nm is deposited on the entire surface of the insulating substrate 301 by using a mixed gas of shixiyan and nitrous oxide by the P-CVD method. A silane gas was used on the surface, and an amorphous stone film 366 (Fig. _) With a film thickness of about 50 cards was deposited using the P-CVD method described on -72- 200306002 p. Said: after the non-sun ^ film 366 is irradiated with an excimer laser to heat, will be non-. Said: Xi; be said to make the growth of the polycrystalline silicon layer to form a polycrystalline silicon thin film 367 Hunting: σHai heating can promote the bonding strength of the single crystal silicon thin film 364. The f-times “remaining part of the polycrystalline silicon thin film 367 constituting the active area of the device” is formed by etching to remove at least a portion of the single-crystal silicon thin film 364 from an unnecessary portion including an unnecessary portion, thereby forming an island pattern (FIG. 13 (e) ). Following the achievement of 'using a mixed gas of TEOS and oxygen, p-CVD method was used to deposit a thin film of 350 oxidized oxide films, and a photoresist of about 350 nm was used as a _ flattening film after full coating' using oxygen The mixed gas flattening film with carbon and carbon is part of the oxide film 335. Then, using a mixed gas of silane and nitrous oxide, P_CVD is performed to form a gate oxide film 368 with a film thickness of about 60 nm (Fig. 13). Thereafter, as in the ninth and tenth embodiments, it may be formed by the same process as the formation process of a generally known P-silicon (polycrystalline silicon) TFT matrix substrate. That is, a gate including polycrystalline silicon, silicide, or polymer is formed, and then P and B ions are implanted, an interlayer insulating film (silicon oxide film) is deposited, and a contact hole is opened to form a metal wiring in the contact hole. Previously, the mobility of the N-channel tft formed in the polycrystalline silicon region was about 1.00 cm2 / V · sec. In the active matrix substrate of this embodiment, the N-channel TFT formed in the monocrystalline silicon region can obtain about 55. cm2 / v · sec movement rate. In the active matrix substrate, the device originally formed in the polycrystalline silicon thin film region 367 requires a signal of 7 to 8 V and a power supply voltage, but is formed on a monocrystalline silicon -73- (69) (69) 200306002 Invention Description Continued Film 364 The time controller and microprocessor of the device in the area only need 3 · 3 v to operate stably. [Twelfth Embodiment] Another embodiment of the present invention will be described with reference to Figs. 14 (a) to 14 (e). In addition, in this embodiment, the constituent elements having the same functions as the constituent elements of the ninth embodiment are denoted by the same reference numerals, and descriptions thereof are omitted. The active matrix substrate of this κ mode is formed in the active matrix substrate 320 of the ninth embodiment, and a polycrystalline silicon film 343 is formed instead of the polycrystalline silicon film 304. The other structures are the same as those of the active matrix substrate 32. Only the differences from the active matrix substrate 320 will be described below. The polycrystalline silicon thin film 343 is contained in so-called continuous crystal grain field silicon (Continuus Grain SilieQn) of polycrystalline silicon which promotes crystal growth with the assistance of a metal. Hereinafter, a method for manufacturing an active matrix substrate using the polycrystalline silicon thin film 343 will be described with reference to FIGS. 14 (a) to 14 (e). First, on the entire surface of the above-mentioned insulating substrate 301 including codel 737 (manufactured by CONING), a mixture of TE0s (tetraethoxysilane, that is, Si (OC2H5) 4) and oxygen (〇2) was used. In the gas, a silicon oxide film 302 with a thickness of about 100 nm is deposited by the p-CvD method. Continuing, on the silicon oxide film 302, an amorphous silicon film 303 having a film thickness of about 50 nm was deposited by p_CVD &amp; using a silane gas. Then, a silicon oxide film 341 (second silicon oxide film) having a thickness of about 2000 nm is deposited on a substantially entire surface of the insulating substrate 300 by a P-CVD method using a mixed gas of silane and nitrous oxide. . (Figure 14 (a)). Then, a specific region of the upper silicon oxide film 341 is formed by etching. -74- 200306002 Description of the invention Continuation of the opening after the opening portion 'To control the hydrophilicity of the surface of the amorphous silicon film 303 at the opening portion, the amorphous The surface of the high-quality silicon film 303 is slightly oxidized to form a silicon oxide film "], and a nickel acetate aqueous solution is spin-coated thereon (Fig. 14)). Next, solid-state growth is performed at a temperature of 600 ° C for about 12 hours. u The so-called continuous crystalline grain field of polycrystalline slaves promoted by the metal to promote crystal growth: (Continuous Grain Slicon) grows to form a polycrystalline film = film 343 with a thickness of about 50 。. The polycrystalline fluorene film 343 is further removed The oxygen oxide film 341 and the oxide film 342 are then etched to remove the characteristics of the polycrystalline silicon thin film 343 (FIG. 14 (c)). In addition, a monocrystalline silicon substrate 310 is prepared. The monocrystalline silicon substrate 310 is oxidized on the surface or An oxide film (silicon oxide film) is stacked to form an oxide film 3 with a thickness of about 2000 nm. In addition, a single crystal substrate having a thickness of 1 彳 n, and a substrate 7 having a specific energy (this At about 24keV) implanted with 1016 / cm2 u, L ^ ^ Ί, ^ 伹 拉 υ / c®, At a 45xl01Vcm2 dose of hydrogen ion implantation part 312, boron was doped to approximately 3 ~ 3. Then, the monocrystalline stone was cut by cutting or anisotropic etching such as KOH. Proportionally smaller than the shape of the specific region of the polycrystalline film 343 by removing at least 0_3 ', t should be smaller than 0.5. The shape of this region can be prevented from being used in the subsequent manufacturing steps of the polycrystalline film 343. Diffusion of metal atoms such as nickel, metal, tin, and the like in the monocrystalline region promotes the stabilization of the characteristics. Following the results, the substrate and the monocrystalline polycrystalline avalanche 343 are cleaned by removing the surface activation microparticles with μ. After the two substrates of the crystal slab substrate 31 are activated,

以至使#近切斷之單晶矽基板31〇之氫離子植入部Μ〗 側的表面密著接合於银刻除去（參照圖μ 14(d))。 V -75- 200306002 { } 發明說明續頁 而後，藉由使用雷射照射或包含約7〇〇°C以上之峰值溫度 之燈退火，使單晶矽基板3 1 〇之氫離子植入部3丨2的溫度昇 溫至氫自矽脫離之溫度以上。藉此以氫離子植入部312為邊 界自絕緣基板3 0 1劈開剝離單晶石夕基板3 1 〇。 以等方性電漿蝕刻或濕式蝕刻，此處為緩衝氟酸之濕式 蝕刻，藉由約10 nm輕微蝕刻除去經剝離而殘留於絕緣基板 301上之單晶矽基板表面之損傷層。藉此，於絕緣基板 上獲得膜厚約50 nm之單晶矽薄膜3〇5(圖14(e))。 其次，於裝置之活性區域近旁的氧化矽膜上形成開口部 ，為求除去將氧化矽膜作為掩模促進結晶生長而添加之鎳 ’植入南濃度之P +離子（15 keV，sxio’cm2)，以RTA，在約 8〇〇°C之溫度下進行i分鐘之熱處理。其係以避免單晶矽薄 膜305中鎳原子擴散之方式，於單晶矽薄膜305與多晶矽薄 膜343之間物理性納入空間，不過極微量之鎳原子仍可能混 入衣私中，因此單晶石夕之活性區域亦宜進行上述除去步驟 另外’優先空間時，亦可依設計上考慮省略除去步驟。 其次’保留構成裝置活性區域之部分，蝕刻除去多晶矽 薄膜343之不需要部分與單晶矽薄膜305之不需要部分，獲 得島狀圖案（對應於圖11(e))。 以後之步驟（對應於圖u(f)〜圖u(h))與第九種實施形態 相同，因此省略。 先所之形成於連續結晶粒場矽區域之N通道TFT的移動 率約為200 cm2/V · sec，而本實施形態之主動矩陣基板中 ’形成於單晶石夕區域之N通道TFT則可獲得約550 cm2/V· sec -76- 200306002 ㈤ I發明說明續頁 的移動率。 該主動矩陣基板中，驅動器原本形成於多晶矽薄膜343區 域之裝置需要7〜8 V之訊號與電源電壓，但是形成於單晶矽 溥膜305區域之裝置之時間控制器及微處理器只須3·3 v即 可穩定地動作。 另外，圖14(b)所示之步驟係使用醋酸鎳水溶液自旋塗敷 ，不過並不限定於此，如亦可使用乙醇等。 〔弟十二種實施形態〕 依據圖15⑷至圖15⑻說明本發明另外一種實施形態如 下。另外，本實施形態中具有與第九種實施形態之構成要 素相同功能之構成要素，註記相同符號，並省略其說明。 餅本實施形態之主動矩陣基板35〇係形成絕緣膜352、非晶 貝夕膜353來取代上述第九種實施形態之主動矩陣基板”^ 中之氧化石夕膜302、非晶質石夕膜3〇3，其他構造與主動矩陣 基板320相同。以下僅說明與主動矩陣基板不同之處。 如圖15(h)所示，主動矩陣基板35〇於絕緣基板3〇1上具有 深度約15〇nm之凹部351，並形成有膜厚約35〇nmi包含氧 化石夕膜及氮化矽膜等之絕緣膜352。 於氧化矽胲302上形成有多晶矽薄膜354及氧化矽膜 。多/矽薄膜354與多晶矽薄膜304同樣地形成島狀圖案， ，厚約50 nm。氧化矽膜311於絕緣膜352上，且在與多晶 薄膜354不同的區域内形成島狀圖案，其膜厚約為 /、氧，石夕膜3 11上’進—步以島狀圖案之方式形成有相同 元狀之早晶石夕薄膜3Q5。單晶石夕薄膜3G5之膜厚約為⑽_。 -77- 200306002 (73) 煢明戰明續頁 另外’本實施形態之氧化矽膜3 11的膜厚為4〇〇 nm。 以下’依據圖l5(a)〜圖15(h)說明主動矩陣基板35〇之製造 方法。 首先，於上述之包含c〇del737(CONING公司製）之絕緣基 板301的整個表面上，使用矽烷與一氧化二氮之混合氣體， 藉由P-CVD法堆積膜厚約350 nm之絕緣膜352。繼續於其整 個表面上使用矽烷氣體，藉由P_CVD法堆積膜厚約5〇nm2 非晶質矽膜353(圖15(a))。 而後，於非晶質矽膜353上照射準分子雷射，予以加熱、 晶化，使多晶矽層生長而形成多晶矽薄膜354。 藉由为1 5 0 nm姓刻除去特定區域之多晶矽薄膜3 5 4與絕 緣膜352之一部分，形成深度約2〇〇nm之凹部35ι(圖i5(b))。 另外，準備單晶矽基板31〇。單晶矽基板31〇預先藉由氧 化表面或堆疊氧化膜（氧化矽膜）而形成膜厚約4〇〇 nm之氧 化矽膜3 11。此外，單晶矽基板3丨〇具有以特定能量（此處約 為24 keV)植入有10i6/cm2以上，此處為⑽2劑量之氫 離子之氫離子植入部312。 一而後，藉由切割或異方性蝕刻等切斷單晶矽基板310成比 藉由蝕刻除去多晶矽薄膜354之特定區域之形狀小〇·5 &quot; m 以上的形狀。 、、廬,以微粒子除去與表面活化用之SC-1洗淨形成有多 晶石夕^ 354之基板與單晶碎基板3U)之兩基板予以活化後 以至/服使罪近切斷之單晶矽基板之氫離子植入部Μ] 側的表面密著接合於凹部351(圖i5(c))。 -78- 200306002 () 發明說明續頁 而後，以300 C〜600°C，此處以約55〇。〇之溫度進行加熱 處理，使單晶矽基板310之氫離子植入部312的溫度昇溫至 虱自矽脫離之溫度以上。藉此以氫離子植入部3 12為邊界劈 開剝離單晶石夕基板3 1 0。 以等方性包漿蝕刻或濕式蝕刻，此處為緩衝氟酸之濕式 蝕刻，藉由約1 0 n m輕微蝕刻除去經剝離而殘留於絕緣基板 3 0 1上之單3曰矽基板表面之損傷層。藉此，於絕緣基板π 1 上獲得各個膜厚約50 nm之多晶矽薄膜354與單晶矽薄膜 305(圖 15(d))。 、 而後，以約800°C進行1分鐘的燈退火。 其次，保留構成裝置之活性區域的部分，藉由蝕刻除去 不需要之矽薄膜354, 305，獲得島狀圖案（圖15(e))。 繼鉍，使用TEOS與氧（〇2)之混合氣體，藉由p-CVD法堆 積膜厚約350 nm之氧化矽膜，以異方性蝕刻之RIE(反應性 離子蝕刻）將其回蝕約400 nm。而後，使用矽烷與一氧化二 虱之混合氣體，藉由P_CVD法形成膜厚約6〇nm之閘極氧化 膜306(氧化矽膜）（圖15(f))。 以後之步驟（圖l5(g)、圖15(h)(對應於圖11(g)、圖11(11)) 與第九種實施形態相同，因此省略。 先七之形成於多晶矽區域之N通道TFT的移動率約為1 〇〇 cm /V · sec ’而該液晶顯示用主動矩陣基板36〇中，形成於 單晶矽區域之N通道TFT則可獲得約550 cm2/V· sec的移動 率 〇 该主動矩陣基板350中，驅動器原本形成於多晶矽薄膜 -79- (75) (75)200306002 發明說明續頁 抑品或之衣置需要7〜8 V之汛號與電源電壓，但是形成於 單曰曰矽溥膜305區域之裝置之時間控制器及微處理器只須 3·3 V即可穩定地動作。 此/卜，該主動矩陣基板350係使用形成有約400 nm之氧化 矽膜3 11的單晶矽基板310，所獲得之TFT之臨限值的變動 ，，使用形成有約200 nm之氧化矽膜311之單晶矽基板31〇 之第九種κ施形態時的0.3 ν( ± σ )比較，為約i/2之〇· i 5 V (土 J )，特別是於低電壓時之動作穩定性提高。 此因接合之單晶矽基板與絕緣基板界面之污染，或是晶 秸應又及不完全性引起之固定電荷的影響減輕。上述約4〇〇 nm之氧化矽膜311之膜厚愈厚，臨限值之變動愈少，不過 藉由氧化石夕膜3 11之形成步驟的效率（氧化所需時間）與階 、勺折衷適切值大致為200 nm〜400 nm。重視變動時，適 切值大致為400 nm，重視階差及效率時，適切值大致為2〇〇 nm ° 當然，階差不構成問題時，須大致在4〇〇 nm以上。 再者，亦可於形成凹部351後，藉由使用TE〇s與氧氣之 PECVD法，以覆蓋整個絕緣基板3〇1之方式堆積數i〇nm之 氧化矽膜之後，接合單晶矽基板3 1 0與絕緣基板3 0 1。藉此 接合性改善，可更確實且良率良好的接合。 此日可，上述之單晶石夕基板3 1 〇係使用以特定能量植入有 5x l〇16/cm2劑量之氫離子者，不過以下係說明使用以特定能 量植入有3xl016/cm2劑量之氫離子之單晶矽基板。 使用單晶矽基板310(氫離子劑量·· 5x i〇16/cm2)時，為求 -80 - (76) 200306002 發明說明續頁 獲得單晶矽薄膜3〇5，传 係於約550 C之溫度中進行熱處理， 而使用單晶矽基板（氫離 丁釗里·3χ1〇 /cm2)時，則係以多 :曰石夕層形成時之大致60〜8〇%之能量照射準分谓 〇，與^晶石夕層生長時同樣地藉由照射全面進行熱處理。 月况下先别之形成於多晶石夕區域之N通道TFT的移 動率約為1 〇〇 Cm2/V · Sec，而形成於單晶石夕區域之N通道TFT 則可獲得約60〇cm2/V· sec的移動率。The surface of the hydrogen ion implantation portion M of the # nearly-cut single-crystal silicon substrate 31 ° was tightly bonded to the silver cut and removed (see FIG. 14 (d)). V -75- 200306002 {} Description of the Invention Continued on the next page, the hydrogen ion implantation portion 3 of the single crystal silicon substrate 3 1 〇 is annealed by using laser irradiation or a lamp containing a peak temperature above about 700 ° C to anneal The temperature of 2 rises above the temperature at which hydrogen escapes from the silicon. Thereby, the single crystal substrate 3 1 0 is cleaved and peeled from the insulating substrate 3 0 1 with the hydrogen ion implantation portion 312 as a boundary. By isotropic plasma etching or wet etching, here is a wet etching of buffered fluoric acid, and the damage layer on the surface of the single crystal silicon substrate left on the insulating substrate 301 by peeling is removed by light etching at about 10 nm. Thereby, a single-crystal silicon thin film 3 05 having a film thickness of about 50 nm was obtained on the insulating substrate (FIG. 14 (e)). Next, an opening is formed on the silicon oxide film near the active area of the device. In order to remove the nickel + implantation concentration of P + ions (15 keV, sxio 'cm2) added to remove the silicon oxide film as a mask to promote crystal growth. ), Heat treatment was performed at RTA for about 1 minute at a temperature of about 800 ° C. It is a way to avoid the diffusion of nickel atoms in the single crystal silicon film 305, and physically incorporate the space between the single crystal silicon film 305 and the polycrystalline silicon film 343, but a very small amount of nickel atoms may still be mixed into the clothing, so the single crystal It is also appropriate to perform the above removal step in the active area of the evening, and when the priority space is used, the removal step may be omitted according to design considerations. Secondly, the portion constituting the active area of the device is left, and the unnecessary portion of the polycrystalline silicon film 343 and the unnecessary portion of the single-crystalline silicon film 305 are removed by etching to obtain an island pattern (corresponding to FIG. 11 (e)). The subsequent steps (corresponding to Fig. U (f) to Fig. U (h)) are the same as those in the ninth embodiment, and are omitted. The mobility of the first N-channel TFT formed in the continuous crystal grain field silicon region is about 200 cm2 / V · sec. In the active matrix substrate of this embodiment, the N-channel TFT formed in the single crystal region can be used. Obtained about 550 cm2 / V · sec -76- 200306002 ㈤ I Invention description The movement rate of the continuation page. In the active matrix substrate, the device originally formed in the polycrystalline silicon thin film region 343 requires a signal of 7 to 8 V and the power supply voltage, but the device formed in the single crystal silicon thin film 305 region only needs a time controller and a microprocessor. · 3 v for stable operation. In addition, the step shown in FIG. 14 (b) is spin coating using an aqueous nickel acetate solution, but it is not limited to this. For example, ethanol or the like may be used. [Twelfth Embodiment] Another embodiment of the present invention will be described with reference to Figs. 15 (a) to 15 (b). In addition, in this embodiment, the constituent elements having the same functions as the constituent elements of the ninth embodiment are denoted by the same reference numerals, and descriptions thereof will be omitted. The active matrix substrate 35 of the present embodiment forms an insulating film 352 and an amorphous bezel film 353 to replace the active matrix substrate of the ninth embodiment described above. ^ The oxide stone film 302 and the amorphous stone film The other structure is the same as that of the active matrix substrate 320. Only the differences from the active matrix substrate are described below. As shown in FIG. 15 (h), the active matrix substrate 35 has a depth of about 15 on the insulating substrate 300. A concave portion 351 of nm is formed with an insulating film 352 including a stone oxide film and a silicon nitride film with a thickness of about 350 nm. A polycrystalline silicon film 354 and a silicon oxide film are formed on the silicon oxide 302. The poly / silicon film 354 forms an island-like pattern similar to the polycrystalline silicon thin film 304, and has a thickness of about 50 nm. A silicon oxide film 311 is formed on the insulating film 352, and an island-like pattern is formed in a region different from the polycrystalline silicon thin film 354, and its film thickness is about / , Oxygen, Shi Xi film 3 11 'advance-step' is formed in the manner of an island-like pattern of premature stone Xi film 3Q5. Monocrystalline Shi film 3G5 film thickness is about ⑽. -77- 200306002 ( 73) Ming Ming Zhan Ming Continued In addition, 'Silicon oxide film 3 11 of this embodiment The film thickness is 400 nm. The method of manufacturing the active matrix substrate 350 is described below with reference to FIGS. 15 (a) to 15 (h). First, the above-mentioned insulating substrate 301 including codel 737 (made by CONING) is described below. On the entire surface, a mixed gas of silane and nitrous oxide was used to deposit an insulating film 352 having a film thickness of about 350 nm by the P-CVD method. Continuing to use silane gas on the entire surface to deposit the film thickness by the P_CVD method. The amorphous silicon film 353 is about 50 nm 2 (FIG. 15 (a)). Then, the amorphous silicon film 353 is irradiated with an excimer laser, heated, crystallized, and a polycrystalline silicon layer is grown to form a polycrystalline silicon film 354. A part of the polycrystalline silicon thin film 3 54 and the insulating film 352 in a specific region was removed by engraving at 150 nm to form a recess 35m with a depth of about 200 nm (Fig. I5 (b)). In addition, a single-crystal silicon substrate was prepared. 31．Single-crystal silicon substrate 31. A silicon oxide film 3 having a thickness of about 400 nm is formed by oxidizing a surface or stacking an oxide film (silicon oxide film) in advance. In addition, the single-crystal silicon substrate 3 has Specific energy (here about 24 keV) is implanted with more than 10i6 / cm2, here is ⑽2 dose of hydrogen The hydrogen ion implantation part 312. After that, the single crystal silicon substrate 310 is cut by cutting or anisotropic etching, etc., which is smaller than the shape of a specific region of the polycrystalline silicon thin film 354 by etching. The shape of the substrate is cleaned with SC-1 for fine particle removal and surface activation. The substrate with polycrystalline stone ^ 354 and the single crystal broken substrate (3U) are activated and the two substrates are nearly cut. The surface of the broken single crystal silicon substrate on the hydrogen ion implantation portion M] side is closely bonded to the recessed portion 351 (FIG. I5 (c)). -78- 200306002 () Description of the invention continued on 300 ° C ~ 600 ° C, here about 55 °. The heat treatment is performed at a temperature of 0 to raise the temperature of the hydrogen ion implantation portion 312 of the single crystal silicon substrate 310 to a temperature above the temperature at which the lice detach from the silicon. Thereby, the single crystal substrate 3 1 0 is cleaved and stripped by using the hydrogen ion implantation portion 3 12 as a boundary. By isotropic slurry etching or wet etching, here is the wet etching of buffered fluoric acid. The surface of the silicon substrate, which is left on the insulating substrate 3 0 1 after peeling, is removed by light etching at about 10 nm. Damage layer. Thus, a polycrystalline silicon thin film 354 and a single crystal silicon thin film 305 each having a thickness of about 50 nm are obtained on the insulating substrate π 1 (FIG. 15 (d)). Then, lamp annealing was performed at about 800 ° C. for 1 minute. Next, the portion of the active area constituting the device is left, and unnecessary silicon thin films 354, 305 are removed by etching to obtain an island pattern (Fig. 15 (e)). Subsequent to bismuth, a silicon oxide film with a film thickness of about 350 nm was deposited by a p-CVD method using a mixed gas of TEOS and oxygen (〇2), and was etched back by RIE (reactive ion etching) with anisotropic etching. 400 nm. Then, a gate oxide film 306 (silicon oxide film) having a thickness of about 60 nm is formed by a P_CVD method using a mixed gas of silane and dioxygen monoxide (Fig. 15 (f)). The subsequent steps (Fig. 15 (g), Fig. 15 (h) (corresponding to Fig. 11 (g), Fig. 11 (11)) are the same as the ninth embodiment, and are therefore omitted. The first seven are formed in the polycrystalline silicon region. The channel TFT has a movement rate of about 100 cm / V · sec ', and in the active matrix substrate 36 for a liquid crystal display, an N-channel TFT formed in a single crystal silicon region can obtain a movement of about 550 cm2 / V · sec. Rate: In this active matrix substrate 350, the driver was originally formed on a polycrystalline silicon film -79- (75) (75) 200306002. Description of the invention Continuation sheet or clothing requires a 7-8 V flood number and power supply voltage, but is formed in The time controller and the microprocessor of the device in the region 305 of the silicon silicon film alone can operate stably with only 3.3 V. This active matrix substrate 350 uses a silicon oxide film with a thickness of about 400 nm. For the single-crystal silicon substrate 310 of 3 11 and the variation of the threshold value of the obtained TFT, the ninth κ application form of the single-crystal silicon substrate 31 with a silicon oxide film 311 of about 200 nm formed is 0.3 ν (± σ), it is about i / 2 to 0 · i 5 V (soil J), and the operation stability is improved especially at low voltage. The contamination of the interface between the single crystal silicon substrate and the insulating substrate, or the effect of fixed charges caused by the incompleteness of the crystal straw and the incompleteness is reduced. The thickness of the above-mentioned silicon oxide film 311 of about 400 nm is thicker, and the threshold is The change in value is smaller, but the efficiency (time required for oxidation) and the step and spoon tradeoffs are approximately 200 nm to 400 nm based on the formation steps of the oxide stone film 3 11. When the variation is valued, the appropriate value is approximately 400. nm, when the step and efficiency are valued, the appropriate value is approximately 2000 nm ° Of course, when the step is not a problem, it must be approximately 400 nm or more. After forming the recess 351, it can also be used. After the PECVD method of TE〇s and oxygen is used to cover the entire insulating substrate 301, a silicon oxide film having a number of 10 nm is deposited, and then the single crystal silicon substrate 3 1 0 and the insulating substrate 3 0 1 are joined. It is possible to connect more reliably and with good yield. Today, the above-mentioned monocrystalline substrate 3 1 〇 is a person who implants a hydrogen ion with a dose of 5 × 1016 / cm2 at a specific energy, but it is used in the following description. Single crystal implanted with a specific energy at a dose of 3xl016 / cm2 of hydrogen ions Substrate. When using a single crystal silicon substrate 310 (hydrogen ion dose · 5x i〇16 / cm2), to obtain -80-(76) 200306002 Description of the invention Continuing to obtain a single crystal silicon film 3 05, which is about 550 Heat treatment is performed at a temperature of C, and when a single-crystal silicon substrate (hydrogen ionized Ding Zhaoli · 3 × 10 / cm2) is used, it is irradiated with approximately 60 ~ 80% of the energy when the Shi Xi layer is formed. Assume that the heat treatment is performed on the entire surface by irradiation in the same manner as when the spar layer is grown. Under the moon condition, the mobility of the N-channel TFT formed in the polycrystalline region is about 1000 Cm2 / V · Sec, and the N-channel TFT formed in the monocrystalline region can obtain about 60 cm2. / V · sec movement rate.

另外於使用單曰曰矽基板310之主動矩陣基板35〇(參照圖 (h))中先鈾之形成於單晶矽區域之TFT的移動率約為 550 cm2/V • sec ° 其差異係因使用單晶矽基板（氫離子劑量：3xi〇16/cm2)所 獲得之單晶石夕薄膜減少氫離子植入量，而可減少隨植入氫 離子造成單晶石夕的損傷，來改善TFT特性。In addition, in the active matrix substrate 35 using a single silicon substrate 310 (refer to Figure (h)), the mobility of the TFT formed in the single crystal silicon region is about 550 cm2 / V • sec °. The difference is due to the difference The use of a single crystal silicon film obtained from a single-crystal silicon substrate (hydrogen ion dose: 3xi〇16 / cm2) reduces the amount of hydrogen ion implantation, and can reduce the damage of the single crystal stone caused by the implantation of hydrogen ions to improve the TFT. characteristic.

此外，使用單晶矽基板（氫離子劑量：3xl〇16/cm2)時，驅 動态原本升&gt; 成於多晶石夕薄膜區域之裝置需要7〜8 v之訊號 與電源電壓，但是形成於單晶矽薄膜區域之裝置之時間控 制器及微處理器只須3·3 V即可穩定地動作。 另外，本發明並不限定於上述各種實施形態，在申請專 利範圍内可作各種變更，適切組合分別揭示於不同實施形 態中之技術性手段而獲得之實施形態亦包含在本發明之技 術性範圍内。 此外，本發明之實施形態並不限定於本内容，如多晶石夕 形成法或層間絕緣膜之材料、膜厚等，當然亦可藉由其他 本領域之技術人員獲知之手段實現。此外，材料方面，一 -81 - (77) (77)200306002 發明說明續頁 般而言，只要為相同目的使用者，即使為不者缺 仍可獲得相同效果。 田…、 再者上述第九、+、十二及十三種實施形態、中，接合 於形成在絕緣基板3Q1上之單晶石夕薄膜之表面的氧化錢 :亦可蝕刻多晶矽薄膜或絕緣基板3〇1之一部分，形成凹部 後堆積。 半導體裝置除上述構造外，亦可以前述單 ㈣與W述絕緣基板之接合側表面被氧化，或前述單 =與前述絕緣基板之接合側表面堆積有氧化石夕膜的方式 再者，可以前述絕緣基板之簞a切垃人Μ φ 土饭 &lt; 早日日矽接合側表面亦堆積有 氧化矽膜的方式構成。另外， 貝另 力外早日日矽之接合侧表面之氧化 石夕膜的膜厚宜在lOOnm以上，更宜在5()〇 丄 文且在5〇〇 nm以上。μ此， 可藉由接合之單晶矽薄膜經 猎此 哥胰、、工由虱化層或虱化矽膜與絕緣基 板接合，防止因施加於接人 „ ^ 镬σ之矽界面之應力造成矽結晶應 k而引起之移動率降低，十H wt 0 ^ # ^ 一 ^疋”面之缺陷及隨伴其之界面 固疋電何、界面之局部作淮、生 卩位丰化成之限值偏差、特性轉定 性降低等。 訂丨土 i疋 此外，藉此，I須你田^ ^ , σ # 、 止因與揭示於特開平1 1-163363 號公報之石英基板之執膨阻# ★,、 古牛醉、止成古疒 &quot; 差而進行加熱接合強度提 问步驟k成破壞用之調餐细 乃正組成的晶化玻璃。因而不發生因 日日化玻辦產生之驗性今厪、生&gt;、 欢！·生至屬造成污染的問題，因此，即使使 用低成本之一般主動拓鱼田古产^ . 用鬲應受點玻璃，仍可防止因埶 膨脹係數羞而進行加熱接合 …、 口通没徒阿步驟中之破壞及剝落。 -82- 200306002 發明說明續頁 口而不I生於纟巴緣基板上使用晶化玻璃而產生之驗性 金屬造成污染的問題，且可低成本化。 本务明之半導體裝置除上述構造外，前述半導體裝置可 以為於前述絕緣基板上形成包含數個M〇SFEt之積體電路 之主動矩陣基板的方式構成。 藉由上述構造，進一步由於半導體裝置為於前述絕緣基 板上形成包含數個M0S(金屬氧半導體）FET之積體電路的 主動矩陣基板，因此可獲得具有前述特徵之主動矩陣基板。 本發明之半導體裝置，除上述構造外，前述絕緣基板可 以包含至少於單晶矽存在之區域表面形成有氧化矽膜之高 應變點玻璃之方式構成。 如鈾所述，由於無須使用調整組成之晶化玻璃，因此藉 由自主動矩陣驅動之液晶顯示面板等上一般所使用之高應 t點玻璃改採絕緣基板，可以低成本製造半導體裝置。 本發明之半導體裝置，除上述構造外，前述絕緣基板可 以包含表面形成有氧化矽膜之鋇-鋁硼矽酸玻璃、鹼土類-鋁硼矽酸玻璃、硼矽酸玻璃、鹼土類_鋅_鉛_鋁硼矽酸玻璃 、鹼土類-鋅-鋁硼矽酸玻璃中之任何一種的方式構成。 一藉由上述構造，進一步由於自自主動矩陣驅動之液晶顯 不面板等上一般所使用之高應變點玻璃之上述揭示之玻璃 改採絕緣基板，因此可以低成本製造適於主動矩陣基板之 半導體裝置。 本發明之半導體裝置，除上述構造外，亦可以形成於前 述絕緣基板上之丽述單晶矽薄膜區域與前述多晶矽薄膜區 -83- (79) (79)200306002 域至少分離0.3微米以上的方式構成。 藉由上述構造，進一步由於單晶矽薄膜之區域盥多曰 薄膜之區域至少分離0.3微米以上，因此可防止鎳、鈾曰: 2等自多晶0擴散至單晶％，可促進半導體裝置之特性 穩定。 μ明之半導體υ ’除上述構造外，亦可以分別形 於前述不同區域内之相同導電型之電晶體中，移動率、次 臣品限值係數、臨限值中之至少一侗俞 構成。 個刖述各區域不同的方式 、藉由上述構造’ it-步由於分別形成於不同區域之 導電型之電晶體中’移動率、次臨限值係數、㉟限值中之 至少-個不同，因此可因應必要之特性形 之區域。 心口电曰曰體 本發明之半導體裝置’除上述構造外，亦可以 於前述不同區域之積體電路中刀別形成 、電源電壓、邏輯位準中之至少_ 版之犋厗 式構成。 至〆個-逑各區域不同的方 :由上述構造，㊣―步由於分別形成於不同區 長、閘極氧化膜之膜厚、電源電壓、邏輯位； 中之至少-個不同，因此可因應必要之構 ： 適合積體電路之區域。 、 y成於 本發明之半導體裝置，除上述 不同區域内之積體電刀没^成於剛述 之方式構成。 丨了以則述各區域之加工原則不同 -84- (80) 200306002In addition, when using a single-crystal silicon substrate (hydrogen ion dose: 3x1016 / cm2), the driving state was originally increased> a device formed in a polycrystalline silicon film region requires a signal of 7 to 8 v and a power supply voltage, but is formed at The time controller and microprocessor of the device in the monocrystalline silicon thin film area only need 3 · 3 V to operate stably. In addition, the present invention is not limited to the above-mentioned various embodiments, and various changes can be made within the scope of the patent application. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention. Inside. In addition, the embodiments of the present invention are not limited to this content, such as the polycrystalline stone formation method, the material of the interlayer insulating film, and the film thickness, etc., of course, can also be realized by other means known to those skilled in the art. In addition, in terms of materials, I -81-(77) (77) 200306002 Description of the Invention Continued In general, as long as the user is the same purpose, the same effect can be obtained even if it is not lacking. Tian ..., and the ninth, +, twelve, and thirteenth embodiments described above, in which the oxide is bonded to the surface of the monocrystalline stone film formed on the insulating substrate 3Q1: polycrystalline silicon film or insulating substrate can also be etched Part of 301 was deposited after forming a recess. In addition to the above-mentioned structure, the semiconductor device may be oxidized on the surface of the joint side of the insulating substrate and the insulating substrate, or the method of depositing an oxide film on the surface of the joint side of the insulating substrate and the insulating substrate. The substrate of the substrate is cut into pieces and the rice is made of rice. <Silicon oxide film is also deposited on the surface of the silicon bonding side at an early date. In addition, the thickness of the oxidized stone film on the junction side surface of silicon at the early date should be above 100 nm, more preferably 5 () ° and above 500 nm. μ Therefore, the bonded monocrystalline silicon film can be bonded to the insulating substrate through the pancreas layer, the panicle layer, or the panicle silicon layer to prevent the stress caused by the stress applied to the silicon interface of the ^ ^ σ The reduction of the mobility caused by silicon crystals due to k, the defects of ten H wt 0 ^ # ^ a ^ 疋 "surface and the accompanying limits of the interface solidification, the interface's localization of the interface, and the formation of the full-thickness potential Deviations and reduced qualitative characteristics.丨 丨 土 疋 In addition, by this, I need you ^ ^, σ #, the cause and the expansion of the quartz substrate disclosed in Japanese Unexamined Patent Application Publication No. 1 1-163363 # ★, Gu Niu, Zhi Cheng Gu 疒 Poor heating joint strength questioning step k into destruction of fine-tuned crystallized glass. As a result, the experience of today's chemical industry, such as today's chemical industry, and life, will not happen! · It is a problem that causes pollution, so even if you use low-cost general active fish farm ancient products ^. Use of glass should be used to prevent the thermal bonding due to the expansion coefficient of thallium ... A step of destruction and spalling. -82- 200306002 Description of the Invention Continued The problem of contamination caused by the metal caused by the use of crystallized glass on the substrate of the stubble edge, and the cost reduction. In addition to the above-mentioned structure of the semiconductor device of the present invention, the semiconductor device may be configured to form an active matrix substrate including an integrated circuit including several MOSFETs on the insulating substrate. With the above structure, since the semiconductor device is an active matrix substrate including an integrated circuit including a plurality of MOS (metal oxide semiconductor) FETs on the aforementioned insulating substrate, an active matrix substrate having the aforementioned characteristics can be obtained. In the semiconductor device of the present invention, in addition to the above-mentioned structure, the aforementioned insulating substrate may be configured to include a high strain point glass having a silicon oxide film formed on a surface of a region where single crystal silicon exists. As described by uranium, since it is not necessary to use crystallized glass with an adjusted composition, it is possible to manufacture semiconductor devices at low cost by using high-resistance point glass, which is generally used in active-matrix driven liquid crystal display panels and the like, to change to an insulating substrate. In the semiconductor device of the present invention, in addition to the above-mentioned structure, the aforementioned insulating substrate may include barium-aluminum borosilicate glass, an alkaline earth-aluminum borosilicate glass, borosilicate glass, and alkaline earth_zinc_ with a silicon oxide film formed on the surface. It is composed of any one of lead_aluminum borosilicate glass and alkaline earth-zinc-aluminum borosilicate glass. With the above structure, since the glass disclosed in the above-mentioned high-strain-point glass used in an active matrix driven liquid crystal display panel or the like is changed to an insulating substrate, a semiconductor suitable for an active matrix substrate can be manufactured at a low cost. Device. In addition to the above-mentioned structure, the semiconductor device of the present invention may also be formed in such a manner that the Rasho single crystal silicon thin film region and the polysilicon thin film region -83- (79) (79) 200306002 domains formed on the insulating substrate are separated by at least 0.3 micrometers or more. Make up. With the above structure, the area of the single-crystal silicon thin film is further separated by at least 0.3 micrometers, so that nickel and uranium can be prevented from diffusing from polycrystalline 0 to single crystal%, which can promote the semiconductor device. Stable characteristics. In addition to the above-mentioned structure, μ Ming's semiconductor υ ′ can also be formed in transistors of the same conductivity type in the aforementioned different regions, each of which has at least one of mobility, substandard limit coefficient, and threshold. The different ways of describing each region, with the above-mentioned structure, it-step is different from at least one of the mobility, the subthreshold coefficient, and the threshold value due to the conductive transistors formed in different regions, Therefore, it is possible to respond to the necessary characteristic area. The electrocardiogram of the present invention, in addition to the above-mentioned structure, the semiconductor device of the present invention can also be formed in the integrated circuit of the different regions described above by at least _ version of the formation, power supply voltage, and logic level. To each of the different areas: from the above structure, since the steps are formed in different area lengths, the film thickness of the gate oxide film, the power supply voltage, and the logic bit; at least one of them is different, so it can respond to Necessary structure: Area suitable for integrated circuits. And y are formed in the semiconductor device of the present invention, except that the integrated electric knife in the different regions described above is not formed in the manner just described.丨 The processing principles of each area are different according to the rules -84- (80) 200306002

猎由上述構造，進一步由於分別形成於不 體電路的加工原則不同，因此可因應加 二或内之積 積體電路之區域。 、、开）成於適合 本發明之半導體裝置，除上述構造外， 矽薄膜之膜厚d為對於以雜質鎳所定義月lj述早晶 包含變動餘. 耗进長Wm， 二動粑圍之小值’亦即即使雜質密度為 _為大致600 nnm下的方式構成。 此％，Wm= [4sskTln (Ni/ni) q2Ni]W2 ，kA、、古耳-田#奴 1為固有载體密度 k為波耳絲哭常數，τ為絕對溫度，£ 又 為電子電荷，Ni為雜質密度。 S”、、&quot;电常數’q 藉二上述構造’由於單晶編之膜厚 下，因此半導體裝置之S值變小，且斷開電流減少。 石夕tr月之半導體裝置’除上述構造外，亦可以前述單晶 夕潯艇之膜厚在10011111以下的方式構成。 藉由上述構造’由於單晶矽薄膜之膜厚在i⑽腿以下， 二匕，+導體裝置之S值進_步變小，且斷開電流減少。 本發明之半導體裝置之製造方法，除上述構造外，亦可 以藉由300°C以上，650°Γ以τ / 、+、&amp;士 65〇C以下之1個階段的溫度步驟進行前 迷熱處理之方式構成。 =由上述構造，進-步由於藉由_階段之溫度步驟進行 …、處理，SUb可以！個步驟進行熱處理。 本發明之半導體奘詈之制、生+ ^ x 衣置之衣运方法，除上述構造外，亦可 、、藉由300 C以上，650 C以下之多階段的溫度步驟進行前 述熱處理之方式構成。 -85- (81) (81)200306002 藉由上述構造，it —步由於藉由多階段之 熱處理，目此可減少因單㈣_造成㈣進行 本發明之半導體裝置之製造方法， 以使前述多晶石夕層生長時，於前述 可 翻、錫、^之至少-種的方式構成。 添加鎳、 藉由上述構造’進—步於使多晶 侧添加&quot;、鍚、財之至少-種，：藉 之移動率，有助於驅動電二成生等長。。因而可提高多晶” 以半導體褒置之製造方法’除上述構造外，亦可 产’、使前述單晶碎基板之氫離子植入區域溫 石脫離之溫度以上，進行以氫離子植入區域 為邊界義前述單_基板之步㈣方式構成。 1述構l進纟由於藉由雷射照射’將單晶石夕基 ^氫離子植人區域之溫度予以昇溫，因此可僅昇溫㈣ 軛圍的區域，可抑制單晶矽的損傷。 、本發明之半導體裝置之製造方法，除上述構造外，亦可 以進仃包含大致7 0 0。(：以上之峰值溫度的燈退火，以氫離子 植入區域為邊界剝離前述單晶矽基板之方式構成。 藉由上述構造，進-步進行包含大致7〇代以上之峰值溫 度之瞬間熱退火（Rapid Thermal Anneal，以下稱似）之燈 退火、’卩氫離子植入部為邊界剝離單晶石夕基板，因此接合 強度進一步提高，並且藉由恢復剝離界面及單晶矽薄膜内 部之氫離子植人造成的損傷，可提高電晶體的特性。另外 -86 - (82) 200306002 發明說明續] 雖燈退火之峰值溫度愈高電晶體的特性愈高，但 的=曲及伸縮變大。因而只須依基板尺寸及形成之裝= 類遥擇適切之溫度與保持時間即可。 本發明之半導體裝詈夕制、皮士 1 A 以前述單晶卿：== 法，除上述構造外，亦可 早7㈣之取大尺寸在10 cm以下的方式構成。 猎由上述構造，進一步單晶石夕薄膜之最大尺寸在… 下時，與單晶石夕之熱膨脹係數差大於石英基板，— 即使使用主動矩陣驅動之液晶顯示面板等上通常使用又之： 應變點玻璃，仍可防止龜料破壞切之剥落 = =晶㈣膜之最大尺寸，係指具有厚度薄之單晶㈣$ 形二开尺：中？大的尺寸。如單晶㈣膜為圓盤 '才’卞a 直徑，單晶矽薄膜為薄立方體時，係指上 面四方形狀之對角線長度。 ，、曰上 ^發明之半導體裝置之製造方法，除上述構造外，亦可 以刖述早晶矽薄膜之最大尺寸在5cm以下之方式構成。 下rt㈣造，進—步單晶石夕薄膜之最大尺寸在5⑽以 ^舁早晶矽之熱膨脹係數差大於石英基板，一般而言 P使使用主動矩陣驅動之液晶顯示面 * 應變:玻璃，仍可進一步防止龜裂等破壞及石夕之X 本^明之半導體裝置之製造方法，除上述構造外，亦可 述絕緣基板上形成有前述多晶石夕薄膜與前述單晶石夕 將二 $ —步包含：蝕刻除去步驟’其係藉由等方性電 2刻或濕式姓刻’姓刻除去前述單晶石夕薄膜表面之損傷 运’島狀餘刻圖案化步驟’其係將前述多晶石夕薄膜與前述 -87- (83) (83)200306002 單晶矽薄膜蝕刻圖案化成島狀；回蝕步驟，其係於 述多晶矽薄膜與前述單晶矽薄 ’、 M , M ^ lL 、工箄槓弟一乳化矽膜後， 猎由異方性蝕刻，保留前述第一負 + , 乐虱化矽胰之膜厚的一部分 ，或回蝕全部；及堆積步驟，苴 第二氧化韻，·之方式構成。㈣作相極、絕緣膜之 藉由上述構造，進一步由於進行一般之多晶矽 驟，因此可使用先前之步驟製 戍 、、 衣以具有則述特徵之TFT 〇 士述亡製造方法中’宜使前述多晶矽薄膜圖案與 -膜厚之兩倍相等。藉此==前述第一氧化 編圖案間之溝狀部内殘留氧：曰：嶋前述單晶 化。 次W虱化膜，整個基板予以平坦 本發明之半導體裝置之製造方法， 以使前述多晶矽薄膜圖宰盥前、f 述構-外，亦可 圖案間之空間大致與前述第 日日夕缚胰 式構成。 夕膜厗之兩倍相等的方 本發明之半導體裝置之製造方法， 以進一步包含P +離子植入+ 偁、外亦可 板上之乂、十…σ a办一 ^ π，”係將形成於前述絕緣基 溥膜與前述多晶石夕薄膜钱刻圖案化成良 狀’而形成聰電晶體’ _ M〇s電晶體刪= 之源巍沒極區域之至少—部分大 」=體 5Χ〜以下之P +離子的方式構成。 一上， 曰_ 步由於N型Mos電晶體及Ρ型M〇s + 晶體之源極及汲極區域 ^ 3之至少一部分大致植入1015/cm2以 -88- 200306002 (84) i說明續頁 i等=::=以下之〆離子，因此而後藉由rta、雷射、 Γ' 1、、、处理，除多晶矽薄膜區域外，單晶矽薄膜區 ::、亦同呀猎由除去金屬原子，而可獲得特性變動更小而： 性穩定之丁F丁。 夂轫旯小而4寸 本發明之半導體穸w 剧 彳體衣置之製造方法，除上述構造外，亦可 等:方:::賴之膜厚與前述多晶”膜之膜厚大致相 2由上述構造，進—步由於單晶⑪薄膜之 ;:=大致相等’因此可同時處理包含島狀-刻二: 步驟，且可形成階差小之電晶體或電路。 口而如為液晶面板時，單元厚度控制性佳。 t ^月之半導體裝置之製造方法’除上述構造外，亦可 膜所形成之前述氧一膜厚 «明之半導體裝置之製造方法，除上述構 H由^早二曰乳化石夕膜上預先藉由氧化表面或堆積氧化石夕 版斤形成之IT述氧切膜之膜厚在· nm以上的方式構成。 产雖氧化石夕膜之膜厚愈厚’臨限值之變動愈小，不過藉由 乳化石夕膜形成步驟之效率(氧化所需時間)與階差的折衷， 適切值大致為200 nm〜400 nm。重視變動時適切值大致 4〇〇麵以上，重視階差及效率時適切值大致為腿〜· 麵，更宜為25。nm~35() nm。氧化石夕膜之膜厚較厚時 別於低電壓時動作的舞定性接古 , ' 獨㈣冋。此因接合之單日日日石夕基板 舁玻璃基板等絕緣基板界面之污染，或晶格應變及不完全 -89- (85) (85)200306002 發明說明續頁 性引起之固定電荷的影響減少。 此外可獲侍g品限值之變動與氧化矽膜形成步驟之效率 及階差之均衡性適切的半導體基板。 此外本毛明之S〇I基板可以前述非晶質無鹼玻璃基板之 熱膨脹率與前述單晶矽相等或大於的方式構成。 藉由上述構造，為求提高單晶㈣膜之分離及對基板之 ㈣力進行熱處理㈣露於高溫下時，在其熱處理之溫度 靶圍内’因基板之熱膨脹率大於單晶矽之熱膨脹率 。…⑽’，因此基板向下翹曲於凸方向。終藉由 懦如Waals力而接著之兩者中，單晶石夕片之基板附近的 部分橫方向拉扯，藉由箭^； A &amp; 糟®刖述向下翹曲於凸方向，自單晶矽 片之端剝離之力與㈣方向—致，其抵銷單晶w自接著 面剝離力’不引起自接著面剝離’成為形成結合鍵的要素 。因而可防止單晶石夕薄膜自基板剝離及基板之破裂。 亦即’於使植人單晶^内之氫離子消散分離之步驟及 提高單晶石夕片對基板接著力之步驟中的熱處理時，基板向 下μ曲於凸方向’自單晶⑪片之端剝離之力與翹曲方 致二引起剝離。藉此可抑制基板破裂及單晶石夕片的剝離。 再者，本發明之s〇I基板可以前述非晶質無驗 驗土類-銘财酸玻璃、鋇·銘财酸玻璃、驗土類-辞: 鋁硼矽酸玻璃或鹼土類-鋅-鋁硼矽酸玻璃之方式構成° 述構造，可獲得熱膨脹率與上述單一㈣或大 此外，本發明之s〇I基板可以前述單晶石夕片之貼合表面為 -90- 200306002 發明說明續直 (111)面、（110)面或（100)面之方式構成。 藉由上述構造，藉由使用具有上述面方位之單晶矽片， 完全同樣地自形成時，可製造具有表面無須研磨之平坦之 矽膜面的SOI基板。 而作為前述單晶矽片，與最容易獲得表面為（100)方位者 比較，方位| ’由於最接近之各原子絕大部分排列於 該（110)面上，因此分離該單晶石夕片時，分離面極為平坦， 可減少作成於本SOI基板上之矽電晶體的不良率。 此外，採用⑴狀位者時，分離之面與單晶石夕塊之劈開 面-致，且於同平面内，最接近之各原子存在於自該⑴U 面稍微偏差的角度’因此分離該單晶矽片日寺，分離面極為 平坦’可進—步降低作成於本S0I基板上切電晶體的不良 率 0 再者，本發明之S01基板之製造方法，可以將前述熱處理 设定在3〇(TC以上，7〇〇。〇以下之溫度範圍内，以多階段之 溫度步驟進行的方式構成。 猎由上述構造，藉“多階段之溫度步驟進行熱處泡 可進一步減少單晶矽薄膜之剝落。尤其是，以 被氫離子植人面分離之溫度進行接著力強化用之第一巧 的熱處理，而t，進行分離用之第二階段的熱處理，^ ㈣，可減少單晶石夕片於熱處理後剝落之繼 數夏。Due to the above-mentioned structure, because the processing principles of the separate circuits are different, they can be added to the area of the integrated circuit. (,, on) into a semiconductor device suitable for the present invention, in addition to the above-mentioned structure, the film thickness d of the silicon thin film includes a margin of variation for the early crystals defined by the impurity nickel. The consumption is long Wm, and the second dynamic range is A small value 'is configured such that the impurity density is at about 600 nnm. This%, Wm = [4sskTln (Ni / ni) q2Ni] W2, kA ,, Guer-Tian # slave 1 is the inherent carrier density, k is the Boer ’s crying constant, τ is the absolute temperature, and £ is the electronic charge. Ni is the impurity density. "S", "Quotient constant" q by two of the above structures "Because the film thickness of the single crystal braid is reduced, the S value of the semiconductor device becomes smaller, and the off current is reduced. The semiconductor device of Shi Xi tr Yue's structure is in addition to the above structure In addition, the film thickness of the aforementioned single crystal boat can be made below 10011111. With the above structure, 'Since the film thickness of the single crystal silicon thin film is below i, the S value of the + conductor device is further advanced. In addition to the above structure, the manufacturing method of the semiconductor device of the present invention can also be reduced by 300 ° C or higher and 650 ° Γ by τ /, +, &amp; 65 ° C or less. The temperature step of each stage is performed in the manner of pre-heat treatment. = With the above structure, the step-by-step temperature treatment is performed by _ stage, SUb can be heat-treated in one step. In addition to the above-mentioned structure, the method of transporting clothes + ^ x clothes can also be constructed by performing the aforementioned heat treatment through temperature steps of 300 C or more and 650 C or less. -85- (81) ( 81) 200306002 With the above structure, it — Because of the multi-stage heat treatment, the manufacturing method of the semiconductor device of the present invention can be reduced due to the single-phase heat treatment, so that when the foregoing polycrystalline layer is grown, at least the above-mentioned invertible, tin, and ^- Adding nickel, through the above structure, 'adding at least one of the polycrystalline side', 钖, and wealth: by virtue of its mobility, it can help drive the two equal lengths of electricity. Therefore, it is possible to improve the polycrystalline silicon manufacturing method "in addition to the above-mentioned structure, it is also possible to produce", and the hydrogen ion implantation region of the single-crystal broken substrate described above can be released above the temperature of the chrysotile to perform hydrogen ion implantation. The area is constituted by the steps of the single substrate described above. As described above, since the temperature of the single crystal yttrium hydrogen ion implantation region is increased by laser irradiation ', only the region surrounded by the yoke can be heated, and damage to the single crystal silicon can be suppressed. In addition to the above-mentioned structure, the method for manufacturing a semiconductor device according to the present invention may include approximately 700. (: The lamp annealing at the above peak temperature is constituted by stripping the aforementioned single crystal silicon substrate with the hydrogen ion implantation area as a boundary. With the above structure, the instantaneous thermal annealing including the peak temperature of approximately 70 generations or more is further performed. (Rapid Thermal Anneal, hereinafter referred to as the like) lamp annealing, the 'Hydrogen ion implantation part is the boundary peeling single crystal substrate, so the bonding strength is further improved, and the hydrogen ions inside the peeling interface and the single crystal silicon film are restored by restoring The damage caused by implantation can improve the characteristics of the transistor. In addition -86-(82) 200306002 Description of the invention continued] Although the higher the peak temperature of the lamp annealing, the higher the characteristics of the transistor, the greater the curvature and the expansion. Just select the appropriate temperature and holding time according to the size of the substrate and the type of the substrate. The semiconductor device of the present invention is manufactured by the leather company 1 A. According to the aforementioned single crystal: == method, in addition to the above structure, It can also be constructed in a way that the large size is less than 10 cm as early as 7 centimeters. With the above structure, when the maximum size of the single crystal evening film is below, the thermal expansion coefficient difference from the single crystal evening film is greater than that of the stone. Substrate, — even if it is usually used on an active matrix driven liquid crystal display panel, etc .: Strain point glass can still prevent tortoise material from cutting and peeling = = the largest size of a crystal film, which refers to a single crystal with a thin thickness. $ Shape two opening ruler: Medium? Large size. For example, the diameter of the single crystal ㈣ film is the diameter of the disk 才 a, and the diameter of the single crystal silicon film is a thin cube, which refers to the diagonal length of the square shape above. In addition to the above structure, the method for manufacturing the semiconductor device of the above invention can also be described in such a way that the maximum size of the early-crystal silicon film is less than 5 cm. The next step is to fabricate, and the maximum size of the single-crystal silicon film is 5 在. The difference in thermal expansion coefficient of premature silicon is larger than that of quartz substrates. Generally speaking, P makes the liquid crystal display surface driven by an active matrix. * Strain: glass, which can further prevent damage such as cracks and X-ray semiconductor devices. In the manufacturing method, in addition to the above structure, the aforementioned polycrystalline silicon thin film and the aforementioned monocrystalline silicon thin film may be formed on an insulating substrate. The step includes: an etching removal step, which is performed by isotropic electricity. Or wet-type surname engraved with 'surname engraving to remove the damage on the surface of the aforementioned monocrystalline stone film' 'island-like remaining patterning step', which is to combine the aforementioned polycrystalline stone film with the aforementioned -87- (83) (83) 200306002 single The crystalline silicon thin film is etched and patterned into an island shape. The etch-back step is performed after the polycrystalline silicon thin film and the aforementioned single crystal thin silicon thin film, M, M ^ lL, and industrial silicon emulsion film, and then anisotropic etching is performed. A part of the film thickness of the first negative +, or etched silicon pancreas is retained, or the whole is etched back; and the stacking step is constituted by the second oxidation rhyme, and the structure is used as the phase pole and the insulating film. Further, since a general polycrystalline silicon step is performed, a TFT having the characteristics described above can be used in the previous steps to fabricate the crystalline silicon. In the manufacturing method, it is desirable to make the aforementioned polycrystalline silicon thin film pattern equal to twice the film thickness. This == residual oxygen in the groove-shaped portion between the aforementioned first oxidized patterns: 嶋: The aforementioned single crystal. The second substrate is flattened, and the entire substrate is flattened. The manufacturing method of the semiconductor device of the present invention enables the aforementioned polycrystalline silicon film to be cleaned before and after the structure is described, and the space between the patterns may be roughly the same as that of the first day and night. Make up. The method of manufacturing the semiconductor device of the present invention, which is twice as large as the film, further includes P + ion implantation + 偁, 乂 on the outside,… σ a do one ^ π, ”will form The aforementioned insulative base film and the aforementioned polycrystalline silicon film were patterned into a good shape to form a "smart transistor" _ M0s transistor = at least part of the source weird electrode region-large "= body 5 × ~ It is constituted by the following P + ions. First, said _ step because at least part of the source and drain regions of N-type Mos transistor and P-type Mos + crystal ^ 3 is roughly implanted at 1015 / cm2 with -88- 200306002 (84) i description continued i etc. = :: = The following ions of plutonium, so by rta, laser, Γ '1 ,,, and treatment, except for the polycrystalline silicon thin film region, the single crystal silicon thin film region ::, also the same way to remove metal atoms , And can obtain smaller changes in characteristics and: stable Ding Ding. In addition to the above-mentioned structure, the manufacturing method of a small and 4-inch semiconductor semiconductor w-body garment according to the present invention can also be equivalent to: Fang ::: The film thickness of Lai is approximately the same as the film thickness of the aforementioned polycrystalline "film. 2 From the above structure, because of the single-crystal ytterbium thin film :: = approximately equal, it can be processed at the same time including the island-cut 2: step, and can form a transistor or circuit with a small step difference. As the liquid crystal In the case of a panel, the thickness of the cell is well controlled. In addition to the above-mentioned structure, a semiconductor device manufacturing method of the aforementioned oxygen-film thickness of the film formed by the film can also be used. The second is that the film thickness of the oxygen cutting film formed on the emulsified stone film by an oxidized surface or stacked oxide stone film is set to be greater than · nm. The smaller the variation of the limit value, but the compromise between the efficiency (the time required for oxidation) and the step of the film formation step of the emulsified stone is approximately 200 nm to 400 nm. When the variation is valued, the approximation value is approximately 400 planes. From the above, when the step and efficiency are valued, the appropriate cut-off value is approximately legs ~ , More preferably 25.nm ~ 35 () nm. When the film thickness of the oxidized stone film is thicker, it is different from the low-voltage operation. Contamination of the interface between insulating substrates such as substrates and glass substrates, or lattice strain and incompleteness -89- (85) (85) 200306002 Description of the invention The effect of the fixed charge caused by the continuation of the sheet is reduced. In addition, the limit of the g product can be obtained. The semiconductor substrate has a suitable balance between the efficiency of the variation and the step of forming the silicon oxide film, and the step difference. In addition, the S0I substrate of this Maoming can be in a manner that the thermal expansion coefficient of the aforementioned amorphous alkali-free glass substrate is equal to or greater than that of the single crystal silicon With the above-mentioned structure, in order to improve the separation of the single crystal film and heat treatment of the substrate, when exposed to high temperature, the thermal expansion rate of the substrate within the temperature target range of the heat treatment is greater than that of the single crystal silicon. Thermal expansion rate .... ⑽ ', so the substrate is warped downward in the convex direction. Finally, by Waals force followed by the two, the part near the substrate of the single crystal evening piece is pulled in the transverse direction, by the arrow ^; A &amp; Bad® warps downwards to convex The direction of the peeling force from the end of the single crystal silicon wafer is the same as that of the ㈣ direction, which offsets the peeling force of the single crystal w from the bonding surface 'does not cause the peeling of the bonding surface' to become an element for forming a bonding bond. Therefore, the single crystal can be prevented. The film is peeled from the substrate and the substrate is cracked. That is, the heat treatment in the step of dissipating and separating hydrogen ions in the implanted single crystal ^ and the step of increasing the adhesion of the single crystal chip to the substrate, the substrate is downward μ The force of peeling from the end of the single crystal cymbal in the direction of the convexity and the warpage will cause peeling. This can suppress the substrate cracking and the peeling of the single crystal chip. Furthermore, the SOC substrate of the present invention can The aforementioned non-amorphous soil test-Ming Cai acid glass, barium · Ming Cai acid glass, soil test-Word: aluminoborosilicate glass or alkaline earth-zinc-aluminum borosilicate glass , The thermal expansion coefficient can be obtained with the above-mentioned single ㈣ or large. In addition, the soi substrate of the present invention can be the bonding surface of the aforementioned single crystal chip is -90- 200306002. Description of the invention Continued straight (111) plane, (110) plane or (100) surface. With the above-mentioned structure, by using the single crystal silicon wafer having the above-mentioned surface orientation, it is possible to manufacture an SOI substrate having a flat silicon film surface that does not need to be polished when it is formed in the same manner. As for the aforementioned single crystal silicon wafer, compared with the easiest to obtain the (100) orientation surface, the orientation | 'is separated from the single crystal wafer because most of the closest atoms are arranged on the (110) plane. In this case, the separation surface is extremely flat, which can reduce the defect rate of the silicon transistor formed on the SOI substrate. In addition, when using the ⑴-like position, the separating surface is the same as the splitting surface of the monocrystalline stone block, and in the same plane, the closest atoms exist at an angle slightly deviated from the ⑴U-plane, so the single is separated. Crystal silicon wafer Risi, the separation surface is extremely flat 'progressive'-further reducing the defect rate of the transistor cut on the S0I substrate 0 Furthermore, in the manufacturing method of the S01 substrate of the present invention, the aforementioned heat treatment can be set to 30%. (Above TC, below 70.00 ° C, it is constructed in a multi-step temperature step. The above structure can be used to further reduce the temperature of the single crystal silicon film by using the "multi-step temperature step for thermal treatment." Exfoliation. In particular, the first heat treatment for strengthening is performed at the temperature at which the hydrogen ion is implanted on the human face, and the second stage heat treatment for separation is performed at t, which can reduce the number of monocrystalline stones. After the heat treatment, it was peeled off for several summers.

w外本發明之SOI基板之製造方法可以前述氫離子之 冰度為40〜200 nm之方式構成 -91 - (87) (87)200306002 發Η月說明續頁 藉由上述構造，如以卜舶、+、卜 單晶石夕薄膜之厚户若h / ’讀子之植人深度，亦即 化之電日p二 nm以下時，可獲得完全耗盡 .,〇 一 + 田知回特性，亚且加工亦容易。另外， 比40 nm溥時，容易破生 乃卜 h ^ ^ ^ ^ ^ V致衣坆上之安全係數降低。 之區域的t 置可以絕緣基板包含至少於單晶石夕存在 二、面上形成有氧化矽層之包含鹼土類，硼矽酸 玻埚之南應變點玻璃之方式構成。 藉由上述構造，由於無須使用調整組成之晶化玻璃，因 此猎由絕緣基板包含主動矩陣驅動之液晶顯示面板等上— 般所使用之高應變點玻璃，可以低成本製造半導體裝置。 ，述半‘ to衣置可以絕緣基板包含鋇_鋁硼矽酸玻璃、鹼 土類-鋁硼矽酸玻璃、硼矽酸玻璃、鹼土類-鋅_鉛-鋁硼矽酸 玻璃、鹼土類-鋅-鋁硼矽酸玻璃中之任何一種之方式構成。 藉由_上述構造，進一步由於自主動矩陣驅動之液晶顯示 面板等上一般所使用之高應變點玻璃之上述玻璃形成絕緣 基板，因此可以低成本製造適用於主動矩陣基板之半導體 裝置。 上述半導體裝置可以絕緣基板上為包含由數個m〇sfet 、雙極電晶體或s I丁構成之積體電路之主動矩陣基板的方式 構成。 藉由上述構成，進一步由於半導體裝置係於絕緣基板上 形成包含數個MOS(金屬氧半導體）FET(TFT)之積體電路的 主動矩陣基板，因此可獲得具有上述特徵之主動矩陣基板。 上述半導體裝置可以形成於絕緣基板上之單晶矽薄膜區 -92- 200306002 (88) 域：ί晶石夕薄膜區域分離ο·3_以上之方式構成。 碎签“ 1述半導體裝置更宜為形成於絕緣基板上之單曰 石夕㈣區域與多晶石夕薄膜區域分離0.5 _以上。早曰曰 稭由上述構造，可防止如鎳、鉑、 散至單晶％，可促進半導體裝置之特師^ 'Μ 1 ^晶石夕擴 型中導tr?:別形成於〜區域之相同導電 r 私動率、次臨限值係 個土述各區域不同的方式構成U數6^限值中之至少一 藉由上述構造，進一步由於分別形 :電型電晶體中，移動率、次臨限值係數不相同 i。個不R，因此可因應所需特性形成於適合電晶體= 上述之半導體裝置可以分別形成於 中，閘長、閘極氧化膜之膜厚、電之積體電路 至少-個上述各區域不同的方式構成。1迷輯位準中之 藉由上述構造，進一步由於分別形 電路中，m、閘極氧化膜之膜厚 2R區域之積體 中之至少—個不同，因此可因應所f M %壓、邏輯位準 適合積體電路之區域。 冓造及特性形成於 上述之半導體裝置可以分別形成於不 中加工原則係上述各區域不同的方 區域之積體電路 恭藉由上述構造，進一步由於分別形x成:成。 电路之加工原則不同，因此可因應加〈不同區域之積體 體電路之區域。 原則形成於適合積 -93- 200306002 發明說明續頁 所上述之半導體裝置，可以單晶矽薄膜之膜厚d為對於以雜 、、/、斤疋義之最大耗盡長wm，包含變動範圍之小值，亦即 即使雜f密度為實用性下限之l〇15cm·3，d之上限仍為大致 600 nm以下的方式構成。 此日守，Wm= [4sskTln (Ni/ni) q2Ni]1/2，ni為固有載體密度 、’ k為波耳兹曼常數，T為絕對溫度，ss為矽之介電常數，q 為電子電荷，Ni為雜質密度。 精由上述構造，由於單晶矽薄膜之膜厚大致在600 nma 下，因此半導體裝置之S值（次臨限值係數）變小，且斷開電 流減少。 上述之半導體裝置，可以單晶矽薄膜之膜厚在1〇〇 nmw 下的方式構成。 糟由上述構造，半導體裝置之3值（次臨限值係數）進一步 變小’且斷開電流減少。 、上述半導體裝置之製造方法，可以藉由30(rc以上，65(rc 、、下之1個卩白^又或多階段的溫度步驟進行上述熱處理之方 式構成。 稭由上述方法，可以i個階段之溫度步驟，亦即以1個牛 驟進行熱處理。 / 、上述半導體裝置之製造方法，可以使多晶矽層生長時， 於上述非晶質矽膜内添加鎳、鉑、錫、鈀中之至少一 方式構成。 、 藉由上述方法，於使多晶石夕層生長時，於非晶質矽膜内 添加錄、m巴中之至少-種，並藉由其後之加熱， &gt;94- (90) 200306002 可促進多晶矽層之結晶生長。 率，有助於驅動電路形成等。 上述半導體裝置之製造方法 晶石夕基板之氫離子植入部溫度 上，進行以氫離子植入部為邊 驟的方式構成。 口而可&amp;南多晶吩層之移動 了以猎由雷射照射，使單 昇溫至氫自矽脫離之溫度以 界劈開剝離單晶矽基板之步 由上述方法，由於藉由雷射照#，將單晶矽基板之 子植入部之溫度予以昇溫’因此可僅昇溫狹窄範圍的 ’可抑制單晶矽的損傷 上述之半導體裝置 峰值溫度的燈退火， 板之方式構成。 ’可以藉由進行包含大致700°C以上之 以氫離子植入部為邊界剝離單晶石夕基 糟由上述方法，由於進行包含大致700°C以上之峰值严产 之瞬間熱退火(Rapid Thermal Αη_υ之燈退火，以氫：； 植）邛為邊界剝離單晶矽基板，因此接合強度進一步提高 丄並且藉由恢復剝離界面及單晶矽薄膜内部之氫離子植二 k成的損知，可^咼電晶體的特性。另外，雖燈退火之峰 值溫度愈高電晶體的特性愈高，但是基板㈣曲及伸縮變 大。因而只須依基板尺寸及形成之裝置種類選擇適切之溫 度與保持時間即可。 輒 上述半+導體裝置之製造方法，可以於絕緣基板上形成有 夕曰曰矽溥膜與單晶矽薄膜後，進一步包含：蝕刻除去步驟 三其係藉由等方性電漿蝕刻或濕式蝕刻，蝕刻除去單晶矽 薄膜表面之損傷層；島狀圖案化步驟，其係藉由蝕刻多晶 -95- (91) (91)200306002 發明說明續頁 石夕薄膜與單晶石夕薄膜而圖荦· 整個多晶梦薄膜…==島狀，步驟’其係於 …早曰曰$㈣上堆積回㈣氧化石夕膜後， 曰/、 刻，保留回蝕用氧化矽膜之一部分，或回蝕 =㈣極絕緣膜形成步驟’其係藉由堆積氧化石夕 膜形成閘極絕緣膜；之方式構成。 此==方法牛由於進行一般之多晶石夕TFT形成步驟，因 此可使用先W之步驟製造具有前述特徵之TFT。 上體裝置之製造方法’可以於絕緣基板上形成有 述夕s曰矽溥膜舆上述單晶矽薄膜後，進-步包含：蝕刻 除去步驟，其係藉由等方性雷將 曰 f電水蝕刻或濕式蝕刻，蝕刻除 处早a曰矽溥膜表面之損傷層；島狀圖案化步驟，其係 藉由I虫刻上述多晶石夕薄膜鱼卜 σσ '、 狀；塗敷步驟，夕溥膜而圖案化成島 一 /、係於正個上述多晶矽薄膜及上述單晶矽 溥^上堆積回蝕用氧化矽膜徭 化膜；回❹驟❹Γί方；!： 敷樹脂平坦 ，、糸猎由異方性蝕刻，回蝕上述樹脂平 坦化膜之全部與上述回餘用 $ 絕緣膜形成步驟，盆传切膜之一部分；及間極 ;之方式構成。 ^化侧成間極絕緣膜 稭由上述方法’可於多晶矽薄膜與單晶矽薄膜之圖案間 的溝狀部内殘留氧化膜（氧切膜），可促進整個基 坦化。 上述半導體裝置之製造方法，可以進一步包含ρ+離子植 入步驟’其係藉由I虫刻形成於絕緣基板上之上述單晶石夕薄 膜與上述多晶石夕薄膜’圖案化成島狀，而形成M0S電晶體 -96- (92)200306002 發明說明辑頁 N型MOS電晶體及PsM〇s電晶體之源極及汲極區域之至 ^ 部分大致植入l〇15/cm2以上，5x 1015/cm2以下之P+離子 的方式構成。 藉由上述方法，係於N型MOS電晶體及P型MOS電晶體之 源極及沒極區域之至少一部分大致植入1〇15/cm2以上， 1〇 /cm2以下之p +離子。因此而後藉由RTA、雷射、爐等 進订加熱處理，除多晶矽薄膜區域外，單晶矽薄膜區域亦 同時藉由除去金屬原子，而可獲得特性變動更小而特性穩 定之TFT。 夕上述半導體裝置之製造方法，可以單晶矽薄膜之膜厚與 多晶矽薄膜之膜厚大致相等的方式構成。 猎由上述方法，可同時處理包含島狀圖案化用之蝕刻之 以後步驟之大部分步驟，且可形成階差小之電晶體或電路 因而如為液晶面板時，單元厚度控制性佳。 上述半‘體裝置之製造方法，可以預先形成於單晶矽基 板表面所幵^成之氧化石夕膜之膜厚在以上，更宜在％〇 以上的方式構成。 通常氧化矽膜之膜厚愈厚，臨限值之變動愈小，不過藉 由氧化矽膜形成步驟之效率（氧化所需時間）與階差的折衷 ，適切值大致為200 nm〜400 nm。重視變動時適切值大致為 400 nm以上，重視階差及效率時適切值大致為2〇〇 〜々⑻打❿ ，更宜為25〇11111〜35〇11111。氧化矽膜之膜厚較厚時，特別於 低電壓時動作的狀性提高。此因接合之單晶石夕基板與玻 璃基板等絕緣基板界面之污染，或晶格應變及不完全性引 -97- (93) 200306002The manufacturing method of the SOI substrate of the present invention can be constituted in such a manner that the ice degree of the hydrogen ion is 40 to 200 nm. -91-(87) (87) 200306002 If the thickness of the single crystal eve thin film is h / 'the depth of implantation of the reader, that is, when the electric day is less than two nm, the complete depletion can be obtained. 〇 一 + Tian Zhihui characteristics, It is also easy to process. In addition, compared with 40 nm 溥, it is easier to break Nab h ^ ^ ^ ^ ^ V causes a reduction in the safety factor on clothing. The location of the area can be composed of an insulating substrate containing at least one monocrystalline stone. 2. A silicon oxide layer formed on the surface, including alkaline earth, and borosilicate glass, south strain point glass. With the above-mentioned structure, since it is not necessary to use crystallized glass with an adjusted composition, it is possible to manufacture a semiconductor device at a low cost by hunting an insulating substrate including an active matrix driven liquid crystal display panel or the like, a high strain point glass generally used. The substrate can be insulated with barium _ aluminoborosilicate glass, alkaline earth-aluminum borosilicate glass, borosilicate glass, alkaline earth-zinc_lead-aluminum borosilicate glass, alkaline earth-zinc -Aluminum borosilicate glass. With the above-mentioned structure, since the above-mentioned glass of the high-strain point glass generally used in active-matrix-driven liquid crystal display panels and the like forms an insulating substrate, a semiconductor device suitable for an active-matrix substrate can be manufactured at low cost. The semiconductor device may be configured as an active matrix substrate including an integrated circuit composed of a plurality of MOSFETs, bipolar transistors, or SiO 2 on an insulating substrate. With the above-mentioned configuration, since the semiconductor device is formed on an insulating substrate with an active matrix substrate including a integrated circuit of a plurality of MOS (metal-oxygen semiconductor) FETs (TFTs), an active matrix substrate having the above characteristics can be obtained. The above-mentioned semiconductor device may be formed in a single-crystal silicon thin film region on an insulating substrate. The region is formed by separating the thin film region from the above. The chip "1" semiconductor device is more preferably separated from the monolithic polysilicon region and polycrystalline polysilicon thin film region formed on the insulating substrate by more than 0.5 _. As mentioned earlier, the above structure can prevent such as nickel, platinum, and To single crystal%, it can promote the special engineer of semiconductor devices ^ 'M 1 ^ Stone crystal expansion medium guide tr ?: Do not form the same conductivity in the ~ area At least one of the U number 6 ^ limit values is formed by different methods. With the above structure, further, since the mobility and the sub-threshold coefficient are different in the shape: electric transistor, the number is not R, so it can be applied according to the situation. The required characteristics are formed in suitable transistors = the above semiconductor devices can be formed separately, and the gate length, the film thickness of the gate oxide film, and the integrated circuit of electricity are constituted by at least one of the above-mentioned different regions. 1 fan level With the above structure, furthermore, in the separate circuit, at least one of the products in the 2R region of m and the gate oxide film thickness is different, so it can be suitable for the product according to the f M% pressure and logic level. The area of the circuit. Fabrication and characteristics formed in the above Semiconductor devices can be formed separately in the integrated circuit of the processing principle, which is different from each of the above-mentioned areas. With the above structure, it is further formed as: x. The processing principles of the circuits are different, so you can add < The area of the integrated circuit. The principle is formed in the suitable semiconductor device described in the above-93-200306002 description of the continuation sheet. The film thickness d of the single crystal silicon thin film can be the maximum depletion of impurities. The length wm includes a small value of the variation range, that is, even if the density of the impurity f is 1015 cm · 3, which is the lower limit of practicality, the upper limit of d is approximately 600 nm or less. On this date, Wm = [4sskTln (Ni / ni) q2Ni] 1/2, where ni is the intrinsic carrier density, 'k is the Boltzmann constant, T is the absolute temperature, ss is the dielectric constant of silicon, q is the electronic charge, and Ni is the impurity density. The structure, because the film thickness of the single crystal silicon film is approximately 600 nma, the S value (sub-threshold coefficient) of the semiconductor device becomes smaller, and the off current is reduced. The above semiconductor device can be a film of the single crystal silicon film. 100nm thick It is structured in the following way. With the above structure, the three values (sub-threshold coefficient) of the semiconductor device are further reduced, and the off current is reduced. The manufacturing method of the above semiconductor device can be determined by 30 (rc or more, 65 (rc ,,, or a multi-stage temperature step to perform the above-mentioned heat treatment. The straw is made of the above method, and the i-stage temperature step can be used to perform heat treatment in one step. / In the method for manufacturing the semiconductor device, when the polycrystalline silicon layer is grown, at least one of nickel, platinum, tin, and palladium is added to the amorphous silicon film. According to the method, the polycrystalline silicon layer is formed. At the time of growth, at least one of the crystalline and m-bar is added to the amorphous silicon film, and by subsequent heating, &gt; 94- (90) 200306002 can promote the crystal growth of the polycrystalline silicon layer. Rate to help drive circuit formation and so on. In the method for manufacturing the semiconductor device described above, the hydrogen ion implantation portion of the spar substrate is configured to have the hydrogen ion implantation portion as a step. The step of removing the polycrystalline phenoline layer was to irradiate it with laser light, so that the temperature of the single crystal was raised to the temperature at which hydrogen was separated from silicon, and the step of peeling off the single crystal silicon substrate was cut by the above method. #, The temperature of the sub-implanted portion of the single crystal silicon substrate is increased, so that only a narrow range of temperature can be increased, and the damage of the single crystal silicon can be suppressed. 'The above method can be used to peel off the monocrystalline stone substrate with the hydrogen ion implantation portion as the boundary containing approximately 700 ° C or higher. The lamp of Αη_υ is annealed, and the single-crystal silicon substrate is peeled with hydrogen :; 植) as the boundary, so the bonding strength is further improved. 丄 By recovering the loss of hydrogen ions from the peeling interface and the inside of the single-crystal silicon film, it can be learned ^ Characteristics of transistors. In addition, the higher the peak temperature of the lamp annealing, the higher the characteristics of the transistor, but the larger the warpage and expansion of the substrate. Therefore, it is only necessary to select an appropriate temperature and holding time according to the size of the substrate and the type of device to be formed.辄 The above-mentioned method for manufacturing a semi- + conductor device may include forming a silicon-silicon film and a single-crystal silicon film on an insulating substrate, and further including: etching and removing step 3, which is performed by isotropic plasma etching or wet Etching, etching to remove the damaged layer on the surface of the single crystal silicon film; the island-like patterning step is performed by etching the polycrystalline -95- (91) (91) 200306002 invention description Figure 荦 · The entire polycrystalline dream film ... == island-like, step 'It is based on ... After the oxidized oxidized oxidized oxidized film was deposited on the ㈣ ㈣, a part of the silicon oxide film for etchback was retained, Or etchback = step of forming the insulating film of the cathode, which is formed by depositing the oxide film on the gate; This == method is because the general polycrystalline silicon TFT formation step is performed, so a TFT having the aforementioned characteristics can be manufactured using the first step. The manufacturing method of the upper body device may include a silicon oxide film on the insulating substrate and the above-mentioned single-crystal silicon film, and further includes: an etching removal step, which is performed by isotropic thunder electro-water etching Or wet etching to etch away the damaged layer on the surface of the silicon wafer; the island-like patterning step is performed by engraving the above polycrystalline silicon thin film fish film σσ ′, shape; the coating step, evening The film is patterned into an island. The silicon oxide film is etched on the polycrystalline silicon film and the single-crystalline silicon film, and is deposited on the polycrystalline silicon film and the monocrystalline silicon film. It is constituted by anisotropic etching to etch back all of the above resin flattening film and the above-mentioned insulating film forming step, a part of the pot cut film; The formation of an interlayer insulating film from the above-mentioned method can leave an oxide film (oxygen cut film) in the groove portion between the pattern of the polycrystalline silicon film and the single crystal silicon film, which can promote the entire radicalization. The method for manufacturing the semiconductor device may further include a step of ρ + ion implantation, which is patterned into an island shape by the monocrystalline silicon film and the polycrystalline silicon film that are formed on the insulating substrate by I insect etching, and Formation of M0S transistor-96- (92) 200306002 Description of the invention Page N-type MOS transistor and PsM0s transistor source and drain regions up to ^ partly implanted above 1015 / cm2, 5x 1015 / Structure of P + ions below cm2. By the above method, at least a part of the source and non-electrode regions of the N-type MOS transistor and the P-type MOS transistor is implanted with p + ions of at least 1015 / cm2 and at most 10 / cm2. Therefore, the heat treatment is then ordered by RTA, laser, furnace, etc. In addition to the polycrystalline silicon thin film region, the single crystal silicon thin film region is also removed by removing metal atoms at the same time, so that a TFT with less characteristic variation and stable characteristics can be obtained. In the above-mentioned method for manufacturing a semiconductor device, the film thickness of the single crystal silicon thin film and the film thickness of the polycrystalline silicon thin film can be made substantially equal. The above method can simultaneously process most of the subsequent steps including the etching of the island pattern, and can form a transistor or a circuit with a small step difference. Therefore, in the case of a liquid crystal panel, the cell thickness is controlled. The above-mentioned method for manufacturing a semi-body device can be formed in advance in a manner such that the thickness of the oxide stone film formed on the surface of the single crystal silicon substrate is greater than or equal to% 0. Generally, the thicker the thickness of the silicon oxide film, the smaller the variation of the threshold value. However, based on the compromise between the efficiency (time required for oxidation) and step of the silicon oxide film formation step, the appropriate value is approximately 200 nm ~ 400 nm. When the emphasis is placed on the variation, the appropriate cut-off value is approximately 400 nm or more, and when the step and the efficiency are attached, the cut-off value is approximately 2,000 to 々⑻ hiccup, and more preferably 25 011 111 to 35 011 111. When the thickness of the silicon oxide film is thicker, the operating characteristics are improved particularly at low voltage. This is due to the contamination of the interface between the bonded monocrystalline substrate and the insulating substrate such as the glass substrate, or the lattice strain and incompleteness. -97- (93) 200306002

起之固定電荷的影響減少。 因此’藉由上述方法，可從π 了獲侍g品限值之變動與氧化石夕 形成步驟之效率及階差之均衡性適切的半導體基板。、 上述半導體裝置之製造方法，可以單晶石夕薄膜之最大 寸在10 cm以下的方式構成。 猎由上述方法，ψ曰Z：^7 Π·*， τ-ι I力凌早日日矽溥肤之最大尺寸在10 cm以下時， 2單晶奴熱膨脹係數差大於石英基板，—般而言吏 用主動矩陣驅動之液曰曰 ^ Η 動之液曰曰頌不面板等上通常使用之高應變點 埚’仍可防止破壞及奴㈣ 矽薄膜之最大尺寸，係扣1古培十 吓明早曰日 '、扎/、有；度薄之單晶矽薄膜之表面 中最大的尺寸。如單晶石夕薄膜為圓盤形狀時 ，^曰其直徑，單晶石夕薄膜為薄長方形時，係、指上面四方 开&gt; 狀之對角線長度。 =半導體裝置之製造方法，Τ以單晶石夕薄膜之 寸在5 cm以下之方式構成。 猎士由上述方法’進—步單晶梦薄膜之最大尺寸在5 cm以 下時，與單晶石夕之熱膨脹係數差大於石英基才反，一般而古 =二動矩陣驅動之液晶顯示面板等上通常使用之高 應受點_ ’仍可進-步防止龜裂等破壞切之剝落。 上述半導體裝置之製造方法， \ 基板之規格化料膨脹差，於A致室溫以上n 溫度範圍内，約為250 ppm以下之方式構成。 藉由上述方法，絕緣基板與單晶⑪薄膜之線膨脹係數差 變小。因此於在絕緣基板上形成單晶石夕薄膜用的步驟中， -98 - 200306002 (94) 赛明_月續頁 可確實防止因熱膨脹係數差造成自氫植入位置劈開剝離步 驟之破壞及接合界面剝離，或於結晶中產生缺陷，並可促 進加熱接合強度的提高。 上述半導體裝置之製造方法，可以植入氫離子植入部之 氫離子劑量在1016/cm2以上，進一步約為3xl〇i6/cm2的方式 構成。 藉由上述方法，可使形成於單晶矽薄膜區域之TFT之移動 率等的特性提高。 另外，發明說明項中形成之具體實施態樣或實施例僅在 說明本發明之技術性内容，不應狹義解釋成僅限定於此種 具體例，只要在符合本發明之精神及以下之申請專利範圍 内’可作各種變更來實施。 圖式之簡單說明 圖Ua)〜圖1(h)係顯示本發明_種半導體裝置之製造步驟 的剖面圖。 圖2(a)圖2(h)係顯示本發明其他半導 例的剖面圖。 圖3(a)〜圖3(d)係顯示本發明另外半導 例的剖面圖。 圖4(a)〜圖4(h)係顯示本發明另外半導 的剖面圖。 ’ 體裝置之製造步驟 體裝置之製造步驟 體裝置之製造步驟 圖5係本發明另外_ 圖6俜蹲干將星 貫施形態之⑽1基板的剖面圖。 回〇你鋇不將早晶矽片貼合 之狀態的剖面圖 於高應變點無鹼玻璃基板前 -99- (95) 200306002 模圖=)係顯示圖5所示之s〇1基板之製作程序圖。 之單曰^本發明之高應變點錢玻璃基板與接著 之早日“夕片於熱處理時輕曲的狀態圖。 圖9係顯示本發明2 + 圖10传自Η 9所-貫施形態之⑽1基板之製作程序圖。 面圖。自圖9所不之S〇1基板製出之-種薄膜電晶體的剖The effect of the fixed charge is reduced. Therefore, by using the above method, a semiconductor substrate having a proper balance between the variation in the limit value of the obtained g product and the efficiency and step difference of the formation step of the oxidized stone can be obtained. The method for manufacturing the semiconductor device described above may be configured such that the maximum size of the single crystal thin film is less than 10 cm. According to the above method, ψ said Z: ^ 7 Π · *, τ-ι I. When the maximum size of the silicon skin is less than 10 cm, the thermal expansion coefficient difference of 2 single crystal slaves is larger than that of the quartz substrate. The active matrix-driven liquid is used to ^ Η The dynamic liquid is used to praise the high strain point pots commonly used on panels and the like, which can still prevent damage and slavery. The largest size of the silicon film is fastened to 1 guppy and 10 in the morning. "Ji Ri", Zha /, Yes; the largest size on the surface of a thin monocrystalline silicon film. For example, when the single crystal evening film is in the shape of a disk, ^ is its diameter, and when the single crystal evening film is in a thin rectangular shape, it means the length of the diagonal of the square above. = Semiconductor device manufacturing method, T is constructed in such a way that the size of the single crystal thin film is less than 5 cm. The hunter is advanced by the above method-when the maximum size of the single crystal dream film is less than 5 cm, the thermal expansion coefficient difference between the single crystal and the single crystal is greater than that of the quartz substrate, and the average is ancient = two-motion matrix driven liquid crystal display panel The commonly used high stress point _ 'can still be further-to prevent cracking and other destructive peeling. The above-mentioned method for manufacturing a semiconductor device is structured such that the expansion difference of the normalized material of the substrate is within a temperature range of A to room temperature above n and about 250 ppm or less. By the above method, the difference in linear expansion coefficient between the insulating substrate and the single crystal rhenium film becomes small. Therefore, in the step for forming a monocrystalline thin film on an insulating substrate, -98-200306002 (94) Saiming_Month Continued can surely prevent the destruction and bonding of the splitting and peeling step from the hydrogen implantation site due to the difference in thermal expansion coefficient. Interfacial peeling, or defects in the crystals, can promote the improvement of heat-bonding strength. The manufacturing method of the semiconductor device described above can be configured by implanting a hydrogen ion implantation portion with a hydrogen ion dose of 1016 / cm2 or more, and further about 3x10i6 / cm2. By the above method, characteristics such as the mobility of the TFT formed in the single crystal silicon thin film region can be improved. In addition, the specific implementation forms or examples formed in the description of the invention are only for describing the technical content of the present invention, and should not be construed as limited to such specific examples in a narrow sense, as long as the patent application conforms to the spirit of the present invention and below Various changes can be implemented within the scope. Brief Description of Drawings Figures Ua) to 1 (h) are cross-sectional views showing the manufacturing steps of a semiconductor device of the present invention. Fig. 2 (a) and Fig. 2 (h) are sectional views showing other semiconducting examples of the present invention. 3 (a) to 3 (d) are cross-sectional views showing another semi-conductive example of the present invention. 4 (a) to 4 (h) are cross-sectional views showing another semiconductor according to the present invention. The manufacturing steps of the body device The manufacturing steps of the body device Fig. 5 shows another part of the present invention. The cross-sectional view of the state where you barium is not bonded to the early-crystal silicon wafer before the high strain point alkali-free glass substrate -99- (95) 200306002 mold =) shows the production of the s〇1 substrate shown in Figure 5 Procedure diagram. The description of the present invention is a state diagram of the high strain money glass substrate of the present invention and the subsequent "Evening piece is lightly bent during heat treatment. Fig. 9 shows the invention 2 + Fig. 10 is transmitted from-9-施 施 式 的 形态 1 Substrate production process chart. Top view. Section of a thin film transistor made from the S01 substrate shown in Figure 9.

:⑷圖11(h)係顯示本發明另外實施形態之半導體 置的一種製造步驟剖面圖。 ^⑷圖12(h)係顯示本發明另外實施形態之半導體 置的一種製造步驟剖面圖。 圖13(a)〜圖！ 3⑴係顯示本發明另夕卜實施形態之半導^ 置的一種製造步驟剖面圖。 ~ Θ (a)圖14(e)係顯示本發明另外實施形態之半導俨纟 的一種製造步驟剖面圖。 圖1 5(a)〜圖15(h)係顯示本發明另外實施形態之半， 置的一種製造步驟剖面圖。 iFig. 11 (h) is a sectional view showing a manufacturing step of a semiconductor device according to another embodiment of the present invention. ^ ⑷ Fig. 12 (h) is a sectional view showing a manufacturing step of a semiconductor device according to another embodiment of the present invention. Figure 13 (a) ~ Figure! 3 is a cross-sectional view showing a manufacturing step of a semiconducting device according to another embodiment of the present invention. ~ Θ (a) FIG. 14 (e) is a sectional view showing a manufacturing step of a semiconducting wafer according to another embodiment of the present invention. 15 (a) to 15 (h) are cross-sectional views showing a manufacturing step of another embodiment of the present invention. i

圖Μ係顯示單晶石夕基板材料之石夕、絕緣基板材料： el737、及包含鋇、硼矽酸玻璃之⑶心7〇59之線膨賬 圖式代表符號說明 _ 1 2, 32, 52 3, 36, 53 4, 37, 43, 54 5, 34 絕緣基板 氧化矽膜（絕緣膜) 非晶質石夕薄膜 多晶矽薄膜 單晶石夕薄膜 -100- 200306002 (96) 發明說明續頁 6, 38, 56 矽氧化膜（閘極絕緣膜） 10, 60 早晶梦基板 11，61 氧化矽膜 12, 62 氫離子植入部 20, 30, 50 半導體裝置 33, 55 凹部 35, 41 第二氧化矽膜 201， 211 SOI基板 202 Τ§7應變點無驗玻璃基板（非晶質無驗玻璃基板) 203, 204 二氧化矽膜 205 單晶矽薄膜 206 早晶梦片 210 氫離子植入面 212 多晶矽薄膜 213 絕緣膜 214 非晶質矽膜 221 薄膜電晶體 222 閘極絕緣膜 223 閘極膜 224 η+或ρ+區域 225 通道區域 226 層間絕緣膜 227 源極、汲極金屬膜 301 絕緣基板Figure M shows the monolithic stone substrate material, the stone substrate, and the insulating substrate material: el737, and the linear expansion chart of the core 7705 which contains barium and borosilicate glass. Symbol description of the symbol_ 1 2, 32, 52 3, 36, 53 4, 37, 43, 54 5, 34 Insulating substrate silicon oxide film (insulating film) amorphous stone film polycrystalline silicon film single crystal film -100- 200306002 (96) Description of the invention continued on page 6, 38, 56 Silicon oxide film (gate insulation film) 10, 60 Premature dream substrate 11, 61 Silicon oxide film 12, 62 Hydrogen ion implantation section 20, 30, 50 Semiconductor device 33, 55 Recess 35, 41 Second oxidation Silicon film 201, 211 SOI substrate 202 Τ§7 Strain point-free glass substrate (amorphous glass substrate) 203, 204 Silicon dioxide film 205 Monocrystalline silicon film 206 Premature dream piece 210 Hydrogen ion implantation surface 212 Polycrystalline silicon film 213 Insulating film 214 Amorphous silicon film 221 Thin film transistor 222 Gate insulating film 223 Gate film 224 η + or ρ + region 225 Channel region 226 Interlayer insulating film 227 Source and drain metal film 301 Insulating substrate

-101 - 200306002 (97) 302, 332, 352, 362 303, 336, 353 304, 337, 343, 354 305, 334 306, 338 310 311 312 320, 330, 350 333, 355 335 341 發明說明續頁 氧化石夕膜（絕緣膜、第一氧化石夕膜) 非晶質矽薄膜 多晶矽薄膜 單晶矽薄膜 閘極絕緣膜（矽氧化膜） 早晶碎基板 氧化秒膜 氫離子植入部 半導體裝置 凹部 氧化矽膜（絕緣膜） 氧化矽膜（第二氧化矽膜）-101-200306002 (97) 302, 332, 352, 362 303, 336, 353 304, 337, 343, 354 305, 334 306, 338 310 311 312 320, 330, 350 333, 355 335 341 Shi Xi film (insulation film, first oxide film) Amorphous silicon film, polycrystalline silicon film, single crystal silicon film, gate insulating film (silicon oxide film), premature crystal substrate, second oxide film, hydrogen ion implantation, semiconductor device recess, oxidation Silicon film (insulating film) Silicon oxide film (second silicon oxide film)

Claims (1)

200306002 拾、申請專利範圍 1·:::導體裝置，其係於絕緣基板 晶矽溥膜分別形成於不同之區域。 h專㈣早 如申請專利範圍第i項之半導體裝置， σ曰 薄膜與前述絕緣基板之接人 /、刖述早日日矽 ^ 安口侧表面破氧化，岑前诂留曰 了與前述絕緣基板之接合側表面堆積有 如申請專利範圍第&quot;員之半導 裝置係於前述絕緣μ 乂人/其中前述半導體 體電路之主動矩;ίΓΓ由數個職FET構成之積 如申請專利範圍第丨項之半導 板包含至少於單晶訂二=成中有前=緣基 之高應變點玻璃。 #面开/成有乳化石夕層 如申請專利範圍第4項之半導體 板包含鋇-鋁硼矽酸玻璃、浐 /、則述絕緣基 酸玻璃、驗土類-鋅-二，夕 矽酸玻璃中之任何一種。 双土頌-鋅-鋁硼 如申請專利範圍第！項之半導 絕緣基板上之前述輩a心- ’、中形成於前述 敬上之別述早晶石夕缚膜區域 區域至少分離0.3微米以上。 、夕日日矽溥胰 如申請專利範圍第3項之半導 前述不同區域内之相同導電型之電晶體中中刀別形成於 臨限值係數、臨限值中 Α夕動率、次 ,.^ ^ 個月丨J迷各區域不同。 如申请專利範圍第3項之半導體裝置，门、 前述不同區域之積體電路中刀形成於 兒峪甲閘長、閘極氧化膜之膜厚 2. 3. 4. 5. 6 · 8. 200306002 鄭·—.. _ 申請•利範圍續頁 、電源電壓、邏輯位準中之至少-個前述各區域 9.如申請專利範圍第3項之半導體裝置，其=同。 别述不同區域内之積^ $成於 不同。 #粗電路之加工原則係前述各區域 !〇.如申請專利範圍第4之半導體裝置，其 薄膜之膜厚大致在600 nm以下。 述早日日矽 11. 如申請專利範圍第1項之半導體裝置，其中前述。„曰 薄膜之膜厚在100 nm以下。 述早日日矽 12. 種半導體裝置之製造方法，其係於 多晶石夕薄膜與單晶石夕薄膜，且包含：、、’、土反上形成有 堆積步驟，其係於絕緣基板表面 非晶質矽膜； β隹檟虱化矽膜及 多晶矽薄膜形成步驟，其係將前述非晶 熱晶化，使多晶石夕層生長而形成多晶石夕薄膜；、予乂加 域姓刻除去步驟’其係蚀刻除去前述多晶石夕層之特定區 ::步驟，其係將預先氧化表面或堆積氧切 定深度植人特定濃度之氫離子之氫離子植入 ;早曰曰石夕基板切割成覆蓋前述蝕刻除去之區域形狀 之一部分或大致全部區域的特定形狀； 狀 气=合步驟’其係將前述切斷之單晶犧使植入 ^子側之面密著貼合於前述钱刻除去之區域；及 單晶矽薄膜形成步驟，其係益 / ^稭由熱處理，以前述氫離 植入部為邊界剝離而形成單晶矽薄膜。 200306002 申，靑專利範圍續頁 少曰a 一 ，、1小肛々巴琢丞板上形成有 夕曰日矽溥膜與單晶矽薄膜，且包含： 非:積:::其係於絕緣基板表面依序堆積氧切膜及 多晶矽薄膜形成步驟，苴係 埶 係將刚述非晶質矽膜予以加 '、、、曰曰化，使多晶矽層生長而形成多晶矽薄膜. /虫刻除去步驟’其㈣刻除去以區域之前述多晶石夕 :部:且姓刻除去該區域之前述氧切膜在厚度方向之 :=驟，其係將預先氧化表面或堆積氧 深度植人特定濃度之氫離子之氫離子植人 :之早曰曰石夕基板切割成覆蓋前述蚀刻除 之—部分或大致全部區域的特定形狀； 次形狀 密著貼合步冑，其係將前述單 氣!:側之面密著貼一刻除板:植入 14. 子:::==驟，其係藉由熱處理，以前述氫離 — 卩為邊界剝離而形成單晶矽薄膜。 —種半導體裝置之製造方法，置 多晶石夕薄臈與單晶發薄膜，/包含：、，、e、.基板上形成有 牛其係於絕緣基板表面堆積氧化發膜； d除去步驟，其係蝕刻除去特 獏在厚度方向之一部分； 戍之則述乳化矽 切斷步驟’其係將預先氧化 有在特定深产楣人Μ ~&amp; *償虱化，且具 度植入特疋痕度之氫離子之氫離子植入部 200306002 15. 16. 17. 18. _請專利範圍顏 ^ ^阳矽基板切割成覆蓋前述蝕刻除去之區域形狀之 F刀或大致全部區域的特定形狀； &amp;密著貼合步驟，其係將前述切斷之單晶梦基板使植入 子侧之面密著貼合於前述蝕刻除去之區域； 單晶矽薄膜形成步驟’其係藉由熱處理，以前述氫離 植入部為邊界剝離而形成單晶矽薄膜； 堆積步驟，其係於前述絕緣基板上依序堆積第二氧化 石夕膜及非晶質矽膜；及 f晶矽薄膜形成步驟，其係將前述非晶質矽膜予以加 熱晶化，使多晶矽層生長而形成多晶矽薄膜。 2申請專利範圍第12至14項中任一項之半導體裝置之 製造方法，其中藉由3⑻。c以上，65〇t以下之i個階段 的溫度步驟進行前述熱處理。 如申明專利範圍第丨2至14項中任一項之半導體裝置之 ‘ ^方法，其中藉由3⑻°C以上，ό 5 0 〇C以下之多階段的 溫度步驟進行前述熱處理。 如申請專利範圍第12至14項中任一項之半導體裝置之 衣k方法’其中使前述多晶矽層生長時，於前述非晶質 矽膜内添加鎳、鉑、錫、鈀中之至少一種。 如申請專利範圍第丨2至14項中任一項之半導體裝置之 製造方法’其中藉由雷射照射，使前述單晶矽基板之氫 離子植入區域溫度昇溫至氫自矽脫離之溫度以上，進行 以氫離子植入部為邊界剝離前述單晶矽基板之步驟。 如申请專利範圍第12至14項中任一項之半導體裝置之 19. 200306002 20. 21. 22. 23. 24. 如申請專利範圍第12至 申請專利範圍續頁 製造方法’其中藉由進行包含大致700°C以上之峰值溫 度的燈退火，以氫離子植入部為邊界剝離前述單晶矽基 板。 如申請專利範圍第丨2至丨4項中任一項之半導體裝置之 製造方法’其中前述單晶矽薄膜之最大尺寸在1〇 〇111以 下。 如申請專利範圍第12至14項中任一項之半導體裝置之 製造方法，其中前述單晶矽薄膜之最大尺寸在5 以下。 如申請專利範圍第12至14項中任一項之半導體裝置之 衣k方法，其中於前述絕緣基板上形成有前述多晶石夕薄 膜與前述單晶矽薄膜後，進一步包含： 蝕刻除去步驟，其係藉由等方性電漿蝕刻或濕式蝕刻 ’蝕刻除去前述單晶矽薄膜表面之損傷層； 島狀圖案化步驟，其係將前述多晶矽薄膜與前述單晶 石夕薄膜蝕刻圖案化成島狀； 回蝕步驟，其係於整個前述多晶矽薄膜與前述單晶矽 薄膜上堆積第-氧化矽膜後’藉由異方性蝕刻，保留前 述第一氧化矽膜之一部分，或回蝕全部；及 堆積步驟’其係堆積作為閘極絕緣膜之第二氧化石夕膜。 如二請專利範圍第22項之半導體裝置之製造方法，其中 使前述多晶矽薄膜圖案與前述島狀蝕刻前之單晶矽薄 :圖案間之空間大致與前述第—氧化石夕膜厚之兩倍相 14項中任一項之半導體裝置之 200306002 25. 26. 27. 28. 29. 30. 电請專利範圍續頁 衣k方法，其中進一步包含p +離子植入步驟，其係將形 成於前述絕緣基板上之前述單晶矽薄膜與前述多晶矽 薄膜蝕刻圖案化成島狀，而形成MOS電晶體，]^型1^〇8 電晶體及P型M0S電晶體之源極及汲極區域之至少一部 刀大致植入1〇15/cm2以上，5xl015/cm2以下之p +離子。 如申請專利範圍第12至14項中任一項之半導體裝置之 製造方法，其中前述單晶矽薄膜之膜厚與前述多晶矽 膜之膜厚大致相等。 〆 2申請專利範圍第12至14項中任一項之半導體裝置之 、°方法其中預先藉由氧化表面或堆積氧化石夕膜而形 成於單晶矽基板上之氧化矽膜之膜厚在2〇〇 nm以上。 ^申請專利範圍第12至14項中任一項之半導體裝置之 製造f法，其中預先藉由氧化表面或堆積氧化矽膜而形 成於早晶石夕基板上之氧化矽膜之膜厚在300 nm以上。 一種SOI基板，其係包含： 非晶質無鹼破璃基板；及 '日日貝热驗玻璃基板上貼合植入氫離子之單 、^片^ 4述氫離子植入層使前述單晶矽片分段而形 成早晶碎薄膜。 η利範圍第28項之S0I基板，其中前述非晶質無 枚螭土反之熱膨脹率與前述單晶矽相等或大於。 如申明專利轭圍第29項之soi基板，其中前述非晶質無 驗玻璃基板為驗土類，财酸玻璃H呂梦酸玻璃 、驗土類-鋅春銘硼石夕酸玻璃錢土類·鋅，石朋石夕酸玻 申請專利範圍續頁 如申請專利範圍第28項之S0I基板，其中前述單晶矽片 之貼合表面為（111)面、（110)面或（1〇〇)面。 種㉙示裝置’‘述非晶質無鹼玻璃基板係透過可視光 之非晶質玻璃材料，且使用前述申請專利範圍第28項之 s〇I基板。 種SOI基板之製造方法，其係於非晶質無鹼玻璃基板 上貼合植入氫離子之單晶石夕片， 、、，，以最高溫度約為60(rc之溫度進行熱處理，以前 =氫離子植入層使岫述單晶矽片分割而形成單晶 粑W…丞板之製造方法，其中於 C以上’ 70〇。(^以下之、、西f闲 步驟進行前述熱處理圍内，以多階段之溫度 = 基板之製造方法，其係於非晶質錢 上貼合植入氫離子之單晶矽片， 板 藉：以包含大致85吖以上之峰值溫度之燈 前錢料植人層使前述單_片 成早晶矽薄膜。 U 專利範圍第33或35項之s〇I基板之製造方法，其 序：：步:化其係在前述非晶質無驗玻璃基板之表面依 序—乳化矽膜及非晶質矽膜； 前述多晶石夕薄膜形成步驟，其係將前述非晶質石夕膜予 200306002 …日日1C，使多晶矽層生長而 斂列咚土止时 4 ❿攻夕日日矽溥膜； U除去步驟，其係银刻除去預定區域 層，亚且蝕刻除去相同區介 U夕晶矽 向之一部分； 則述一乳化矽膜在厚度方 切斷步驟，其係將 成覆蓋前述蝕刻除去 晶梦片切斷 前述植入有氫離子之單 之區域的形狀； 入:：:二步驟二ί係將前述切斷之單晶石夕片使前述植 至 貞1之面密著貼合於前述蝕刻除去之區域；及 37. 38. 單晶石夕薄膜形成步驟，其係實施前述熱處理，藉 述氫脆化使前述單晶矽片分割而形成單晶矽薄膜。 如:請專利範圍第33或35項之s㈣板之製造方法，其 中前述氫離子之植入深度為4〇〜2〇〇 nm。 “ 一種半導體裝置，其係於絕緣基板上，多晶矽薄膜與單 晶矽薄膜分別形成於不同區域，上述絕緣基板與上述單 晶矽薄膜之規格化之線膨脹差，大致於室溫以上，6〇〇t 以下之溫度範圍内約在25〇 ppm以下。 39· —種半導體裝置，其係於絕緣基板上，多晶矽薄膜與單 晶矽薄膜分別形成於不同的區域，且上述單晶矽薄膜之 喇交峰值之偏差量在519.5 cm-1以上，且在521.5 cm·1以 下0 40·如申請專利範圍第38或39項之半導體裝置，其中上述絕 緣基板包含高應變點玻璃，該高應變點玻璃包含至少於 200306002 41. 42. 43. 44. 45. 46. 申請專利範圍續頁 單晶矽存在之區域的表面形成有氧化矽層之鹼土類_鋁 硼矽酸玻璃。 如申請專利範圍第38或39項之半導體裝置，其中上述絕 緣基板包含鋇-鋁硼矽酸玻璃、鹼土類_鋁硼矽酸玻璃、 硼矽酸玻璃、鹼土類-鋅-鉛-鋁硼矽酸玻璃、鹼土類_鋅_ 鋁硼石夕酸玻璃中之任何一種。 如申請專利範圍第38或39項之半導體裝置，其中上述半 ‘體衣置係於上述絶緣基板上包含由數個、雙 極電晶體或SIT構成之積體電路之主動矩陣基板。 如申請專利範圍第邮39項之半導體裝置，其中形成於 士述絕緣基板上之上述單晶矽薄膜區域與上述多晶矽 薄膜區域至少分離〇·3 μηι以上。 如申請專利範圍第38或39項之半導體裝置，其中形成於 j述絕緣基板上之上述單晶妙薄膜區域與上述多晶石夕 薄膜區域至少分離〇·5 μηι以上。 如申請專利範圍第38或39項之半導體裝置，其中分別形 成於上述不同區域内之相同導電型之電晶體中，移動率 臨限值係數、臨限值中之至少一個上述各區域不同。 2 =利範圍第38或39項之半導财置，其中分別形 :厂不同區域之積體電路中’問長、閑極氧化膜之 二子、電源電壓、邏輯位準中之至少-個上述各區域不 ^申請專利範圍第3 8或3 9項之半導體裝置，其中分別妒 成於上述不同區域内之積 ^ 價奴電路之加工原則係上述各 47. 200306002 申請專利範圔續頁 匪场1不同。 48·如申請專利範圍第38或39 干¥體裝置，其中上述單 日日石夕潯膜之膜厚大致在6〇〇 nm以下。 49·如申請專利範圍第38或39項 曰〜一+ 只心千蛉體叙置，其中上述單 曰日石夕溥膜之膜厚在10〇 nm以下。 50 .一種半導體裝置之製造方法，其^ ^ ^ ^ ^ ^ 少曰a — 你於、乡巴緣基板上形成有 夕日日矽溥膜與單晶矽薄膜，且包含··200306002 Patent application scope 1 · ::: Conductor device, which is formed on an insulating substrate. A crystalline silicon film is formed in different areas. h Specially, as early as the semiconductor device in the scope of application for patent i, σ said that the connection between the thin film and the aforementioned insulating substrate /, said that the early silicon ^ Ankou side surface is broken and oxidized. The junction side surface is stacked with the active moment of the semiconductor device circuit as described in the above-mentioned patent application range, and the "inductive moment of the semiconductor circuit"; ΓΓ The product composed of several professional FETs is as described in the patent application item The semi-conducting plate includes a high strain point glass having at least two single crystals and a front edge. # 面 开 / 成 有 胶 石 石 层 If the semiconductor board of the patent application No. 4 contains barium-aluminum borosilicate glass, 浐 /, then said insulating base acid glass, soil test-zinc-di, silicate Any of glass. Double earth song-zinc-aluminum-boron The semiconducting element of the item on the insulating substrate is formed of the above-mentioned precocious sterilized film region on the insulating substrate, and the region is separated by at least 0.3 micrometers. For example, in the silicon nitride pancreas of the third application of the patent scope of the patent application, in the transistor of the same conductivity type in the aforementioned different regions, the knife is formed in the threshold value, the threshold value, and the threshold value. ^ ^ Month 丨 J fans are different in each area. For example, for a semiconductor device with the scope of patent application No. 3, the gate and the integrated circuit in the aforementioned different regions are formed by the gate length and the gate oxide film thickness. 2. 3. 4. 5. 6 · 8. 200306002 Zheng · — .. _ Application • At least one of the aforementioned areas in the continuation page, power supply voltage, and logic level. 9. For a semiconductor device with a scope of patent application item 3, it is the same. Do not mention the product in different areas ^ $ 成 于 Different. #Rough circuit processing principle is the aforementioned areas! 〇 As for the semiconductor device in the scope of patent application No. 4, its film thickness is approximately 600 nm or less. Said early silicon 11. As for the semiconductor device of the scope of application for patent 1, the foregoing. "The film thickness of the thin film is less than 100 nm. Said early silicon 12. A method for manufacturing a semiconductor device, which is based on a polycrystalline silicon film and a monocrystalline silicon film, and includes: ,,,, There is a stacking step, which is an amorphous silicon film on the surface of the insulating substrate; a beta tick silicon film and a polycrystalline silicon thin film forming step, which is a method of thermally crystallizing the aforementioned amorphous to grow a polycrystalline layer to form a polycrystalline silicon Shi Xi thin film; Yu Yun Jiayu's step of removing step 'It is etching to remove the specific area of the aforementioned polycrystalline stone layer :: Step, it is to oxidize the surface in advance or deposit oxygen to a certain depth to implant a specific concentration of hydrogen ions Hydrogen ion implantation; early said that the Shi Xi substrate was cut into a specific shape covering a part or almost all of the shape of the area removed by the etching; the shape gas = the closing step ', which is the implantation of the cut single crystal ^ The sub-side surface is closely adhered to the area removed by the aforementioned coin; and the step of forming the single crystal silicon film, which is performed by heat treatment, and the single crystal silicon film is formed by using the hydrogen ion implantation part as a boundary to form a single crystal silicon film 200306002 The scope of patents is continued on the following pages: a, 1, and 1 small anal ridges are formed with a silicon silicon film and a single crystal silicon thin film, and include: non :::: It is on the surface of an insulating substrate The oxygen cutting film and the polycrystalline silicon thin film formation steps are sequentially stacked, and the actinide system is to add the amorphous silicon film just described, and the polycrystalline silicon layer is grown to form a polycrystalline silicon film. The area in which the aforementioned polycrystalline stone is removed by the seal: and the name of the oxygen cut film in the area is removed in the thickness direction: = step, which is to oxidize the surface in advance or accumulate oxygen to a specific concentration of hydrogen ions. Planting hydrogen ions: Early on, said Shi Xi substrate was cut into a specific shape covering part or almost all of the foregoing etching; the sub-shape is closely attached to the step, which is the aforementioned single gas !: side surface Immediately remove the plate with close adhesion: implant 14. Sub ::: == step, which forms a single-crystal silicon thin film by heat treatment and peeling with the aforementioned hydrogen ion-— as a boundary. — A method for manufacturing a semiconductor device, Polycrystalline stone thin film and single crystal hair film, / contains: ,, e. The substrate is formed with an oxide film deposited on the surface of the insulating substrate; d removing step, which is to remove a part of the thickness in the thickness direction by etching; There is a hydrogen ion implantation section in a specific deep-producing human population ~ &amp; * compensation and implantation of hydrogen ions with a special degree of traceability 200306002 15. 16. 17. 18. _Please patent scope Yan ^ ^ The anodic silicon substrate is cut into a specific shape of the F-knife covering almost the area removed by the aforementioned etching, or a specific shape of the entire area; &amp; Adhesion bonding step, which is to close the cut single crystal dream substrate to make the surface on the implant side dense The single crystal silicon thin film is formed on the region removed by the aforementioned etching; the single crystal silicon thin film formation step is performed by heat treatment and the hydrogen ion is removed from the implanted part as a boundary to form a single crystal silicon thin film; and the stacking step is performed on the aforementioned insulating substrate A second oxide film and an amorphous silicon film are sequentially deposited; and a f-crystalline silicon thin film forming step is to heat and crystallize the aforementioned amorphous silicon film to grow a polycrystalline silicon layer to form a polycrystalline silicon film. 2 A method for manufacturing a semiconductor device according to any one of claims 12 to 14, wherein 3⑻ is used. The above-mentioned heat treatment is performed at a temperature step of i or higher and i stages of 65 or less. For example, the method of the semiconductor device of any one of claims 2 to 14 is declared, wherein the aforementioned heat treatment is performed by a temperature step of 3 ° C or more and 50 ° C or less. In the method for fabricating a semiconductor device according to any one of claims 12 to 14, when the aforementioned polycrystalline silicon layer is grown, at least one of nickel, platinum, tin, and palladium is added to the aforementioned amorphous silicon film. For example, the method for manufacturing a semiconductor device according to any one of claims 2 to 14 'wherein the temperature of the hydrogen ion implantation region of the aforementioned single crystal silicon substrate is raised to a temperature above the temperature at which hydrogen is released from silicon by laser irradiation. Performing a step of peeling the aforementioned single crystal silicon substrate with the hydrogen ion implantation portion as a boundary. If you apply for a semiconductor device in any of the patent scope items 12 to 14, 19.200306002 20. 21. 22. 23. 24. If you apply for the patent scope scope 12 to the patent scope of the continuation page manufacturing method 'wherein The lamp was annealed at a peak temperature of approximately 700 ° C or higher, and the aforementioned single crystal silicon substrate was peeled off with the hydrogen ion implantation portion as a boundary. For example, the method for manufacturing a semiconductor device according to any one of claims 1-4 to 1-4, wherein the maximum size of the aforementioned single crystal silicon thin film is less than 10011. For example, the method for manufacturing a semiconductor device according to any one of claims 12 to 14, wherein the maximum size of the aforementioned single crystal silicon thin film is 5 or less. For example, the method for applying a semiconductor device according to any one of claims 12 to 14, wherein the polycrystalline silicon thin film and the single crystal silicon thin film are formed on the insulating substrate, and further include: an etching removal step, It is to remove the damaged layer on the surface of the monocrystalline silicon film by isotropic plasma etching or wet etching. The island-like patterning step is to pattern the polycrystalline silicon film and the monocrystalline silicon film into islands. Etchback step, which is to deposit the first silicon oxide film on the entire polycrystalline silicon film and the single crystal silicon film, and to retain a part of the first silicon oxide film by anisotropic etching, or etch back all; And a stacking step, which is to deposit a second oxide film as a gate insulating film. For example, the method of manufacturing a semiconductor device according to item 22 of the patent, wherein the aforementioned polycrystalline silicon thin film pattern and the aforementioned monocrystalline silicon thin film before the island-like etching are made: the space between the patterns is approximately twice the thickness of the aforementioned -stone oxide film 200306002 of any one of the 14th semiconductor devices. 25. 26. 27. 28. 29. 30. The method of patent application continues the k-method, which further includes a p + ion implantation step, which will be formed in the foregoing The monocrystalline silicon film and the polycrystalline silicon film on the insulating substrate are etched and patterned into an island shape to form a MOS transistor. At least one of the source and drain regions of the ^ type 1 ^ 08 transistor and the P type M0S transistor. The knife was implanted with p + ions above 1015 / cm2 and below 5xl015 / cm2. For example, the method for manufacturing a semiconductor device according to any one of claims 12 to 14, wherein the film thickness of the aforementioned single-crystal silicon thin film is approximately equal to the film thickness of the aforementioned poly-crystalline silicon film. 〆2 The method of applying a semiconductor device according to any one of the items 12 to 14 of the patent scope, wherein the thickness of the silicon oxide film formed on the single crystal silicon substrate by oxidizing the surface or stacking the oxide stone film in advance is 2 OOnm or more. ^ The method for manufacturing a semiconductor device according to any one of the claims 12 to 14, wherein the thickness of the silicon oxide film formed on the prespar substrate by oxidizing the surface or stacking the silicon oxide film in advance is 300 nm or more. An SOI substrate, comprising: an amorphous alkali-free glass-breaking substrate; and a single, ^ implanted hydrogen ion implantation layer on a glass substrate of Japan and Japan, wherein the hydrogen ion implantation layer described above makes the single crystal The silicon wafer is segmented to form a prematurely broken film. In the SOI substrate of the ninth range, the thermal expansion coefficient of the aforementioned amorphous non-aqueous clay is equal to or greater than that of the aforementioned single crystal silicon. For example, the soi substrate of the 29th item of the patent yoke encirclement, in which the aforementioned non-amorphous glass substrates are soil inspection type, acid glass H Lumeng acid glass, soil inspection type—zinc Chunming borosilicate acid glass money earth type · Zinc, sapphire glass acid patent application continuation page, such as the SOI substrate of the 28th patent application scope, in which the bonding surface of the aforementioned single crystal silicon wafer is (111) surface, (110) surface or (100) )surface. Kind of display device 'The above-mentioned amorphous alkali-free glass substrate is an amorphous glass material that transmits visible light, and uses the soI substrate of the aforementioned 28th patent scope. A manufacturing method of an SOI substrate, which is based on bonding a monocrystalline stone sheet implanted with hydrogen ions on an amorphous alkali-free glass substrate, and heat-treated at a maximum temperature of about 60 (rc, previously = The hydrogen ion implantation layer divides the monocrystalline silicon wafer to form a monocrystalline cymbal W ... fascia plate, wherein the above heat treatment is performed at a temperature of C or more and 70 ° or less. Multi-stage temperature = substrate manufacturing method, which is based on bonding monocrystalline silicon wafers implanted with hydrogen ions on amorphous money. Board borrowing: planting materials in front of lamps with a peak temperature of approximately 85 ac Layer to make the aforementioned monocrystalline silicon wafer into a premature silicon thin film. U The method for manufacturing a soI substrate of the 33rd or 35th patent scope, the sequence is as follows: Step: It is based on the surface of the foregoing amorphous glassless substrate. Sequence—emulsified silicon film and amorphous silicon film; the aforementioned step of forming polycrystalline silicon film is to apply the aforementioned amorphous stone film to 200306002… 1C every day, so that the polycrystalline silicon layer grows and converges. 4 ❿Silicon silicon film; U removal step, which is planned to remove silver engraving The domain layer is etched to remove a part of the same region U. Si crystal silicon. Then, the step of cutting an emulsified silicon film in the thickness side is described, which is to cover the etching and remove the crystal dream sheet to cut off the implanted hydrogen ions. The shape of the area of the single; into :: two steps two is to cut the aforementioned single crystal evening piece so that the surface planted to Zhen 1 closely adheres to the area removed by the foregoing etching; and 37. 38. The step of forming a single crystal thin film is to perform the aforementioned heat treatment, and to split the aforementioned single crystal silicon wafer by hydrogen embrittlement to form a single crystal silicon thin film. For example, please refer to the method for manufacturing a slab in the patent scope item 33 or 35, The implantation depth of the foregoing hydrogen ions is 40 to 200 nm. "A semiconductor device is mounted on an insulating substrate, and a polycrystalline silicon film and a single crystal silicon film are formed in different regions, respectively, said insulating substrate and said single crystal silicon The normalized linear expansion difference of the thin film is approximately above room temperature and less than 25 ppm within a temperature range of less than 600 t. 39. A semiconductor device, which is on an insulating substrate, a polycrystalline silicon film and a single crystal Silicon film The semiconductor devices are formed in different regions, and the deviation of the pull-off peaks of the above-mentioned single crystal silicon thin film is 519.5 cm-1 or more and 521.5 cm · 1 or less 0 40. For a semiconductor device in the 38th or 39th scope of the patent application, The above-mentioned insulating substrate includes high strain point glass, and the high strain point glass includes at least 200306002 41. 42. 43. 44. 45. 46. The scope of the patent application continued on the surface of the region where the single crystal silicon exists is formed with a silicon oxide layer. Alkaline earth_aluminum borosilicate glass. For example, the semiconductor device under the scope of patent application No. 38 or 39, wherein the above-mentioned insulating substrate includes barium-aluminum borosilicate glass, alkaline earth_aluminum borosilicate glass, borosilicate glass, alkaline earth Any one of the class-zinc-lead-aluminoborosilicate glass, alkaline earth _zinc_ aluminosilicate glass. For example, the semiconductor device of the 38th or 39th scope of the application for patent, wherein the above-mentioned half body is placed on the above-mentioned insulating substrate and includes an active matrix substrate composed of a plurality of integrated circuits composed of bipolar transistors or SITs. For example, the semiconductor device according to item 39 of the patent application scope, wherein the above-mentioned single crystal silicon thin film region and the above-mentioned polycrystalline silicon thin film region formed on the insulating substrate are separated by at least 0.3 μm. For example, the semiconductor device according to claim 38 or 39, wherein the above-mentioned single crystal thin film region and the above-mentioned polycrystalline silicon film region formed on the j-insulating substrate are separated by at least 0.5 μm. For example, if the semiconductor device according to item 38 or 39 of the patent application scope is formed in transistors of the same conductivity type in the different regions, at least one of the threshold value coefficient and the threshold value of the mobility is different in each of the above regions. 2 = semi-conductor property in the 38th or 39th of the profit range, which are respectively shaped as follows: in the integrated circuits of different areas of the factory, at least one of the two of the "length, the oxide film of the leisure electrode, the power voltage, and the logic level Each region does not apply for the semiconductor device of the 38th or 39th scope of the patent application, which is jealous of the product in the different regions mentioned above. The processing principle of the valence circuit is the above. 47.200306002 Patent Application Continued Bandits 1 different. 48. If the patent application is No. 38 or 39, the film thickness of the above-mentioned single-day stone eve film is approximately 600 nm or less. 49. If item 38 or 39 of the scope of the application for a patent is applied, a single-hearted centipede is described, in which the film thickness of the above-mentioned monolithic membrane is below 100 nm. 50. A method for manufacturing a semiconductor device, comprising: ^ ^ ^ ^ ^ ^ Shao a — you have formed a sunset silicon wafer and a single crystal silicon film on a substrate of a country and a country, and include ... 非=其係於絕緣基板表面依序堆積氧化-膜及 敎曰多:“夕ff形成步驟，其係將上述非晶質鶴以加 ，、、、曰曰 &lt;吏多晶矽層生長而形成多晶矽薄膜； 域钱刻除去步驟，其係钱刻除去上述多晶石夕層之特定區 表=驟’其！將預先氧化表面或堆積氧化膜，而在 '離‘之：，矽M ’且具有在特定深度植入特定濃度之 風離子之虱離子植入部置曰 ,ψ^ . 之早日日矽基板切割成覆蓋上述Non = It sequentially deposits oxide-films on the surface of the insulating substrate and said: "Xi ff formation step, which is to add the above amorphous crane to the polycrystalline silicon layer to form polycrystalline silicon. Thin film; the step of removing inscriptions is to remove the specific area of the polycrystalline stone layer as described in the above table = step 'its! The surface or oxide film will be oxidized in advance, and in the' off ':, silicon M' and have The lice ion implantation part implanted with a specific concentration of wind ions at a specific depth is set to ψ ^. As soon as possible, the silicon substrate is cut to cover the above. =除去之區域形狀之—部分或大致全部區域的特定 Γ:广系洗淨上述絕緣基板與單晶梦基板，將 4兩基板之表面予以活化； 肝 接合步驟，其係將上 使植入氫離子侧之面p 板’在室溫下 *耆於上述蝕刻除去之區域，接合 上述兩基板；及 牧σ 早晶矽薄膜形成步驟’其係藉由熱處理，以上述氫離 -10- 200306002 电請專利範圍續頁 石夕薄^部為邊界劈開剝離，於上述絕緣基板上形成單晶 51. 體裝置之製造方法，其係在絕緣基板上形成有 夕日日夕溥膜與單晶矽薄膜，且包含·· 非其係於絕緣基板表面依序堆積氧化碎膜及= The shape of the removed area—partial or substantially all of the area. Γ: Canton cleans the above-mentioned insulating substrate and single crystal dream substrate, and activates the surfaces of the two substrates. In the liver bonding step, it implants hydrogen. Ion-side surface p-plate 'at room temperature * in the area removed by the above-mentioned etching, joining the two substrates; and the step of forming a sigma-early-early-silicon thin film' is performed by heat treatment with the above-mentioned hydrogen ionization -10- 200306002 electricity The scope of the patent is continued. The thin part of Shi Xi is the boundary cleaving and peeling to form a single crystal 51. bulk device on the above-mentioned insulating substrate. The manufacturing method of the device is to form a day and night film and a single crystal silicon film on the insulating substrate, and Contains a non-sequentially deposited oxide film on the surface of the insulating substrate and 敎多：”膜形成步驟’其係將上述非晶質石夕膜予以加 …使夕日曰矽層生長而形成多晶矽薄膜； 广蝕刻除去步驟，其係餘刻除去特定區域之上述多晶石夕 二肤二：且蝕刻除去相同區域之上述氧化矽膜在厚度方 向之一部分； 切斷步驟，其係將預先氧化表面或堆積氧化 面形成氧切膜，且具有在特定深度植人特定濃产之t 離子植人部之單^基板切割成覆蓋上述姓 :“去之區域形狀之一部分或大致全部區域的特定形 狀^ ，Many: "The film forming step" is to add the above amorphous stone film ... to grow a silicon layer to form a polycrystalline silicon thin film; a wide etching removal step is to remove the polycrystalline stone in a specific area in a short time. Second skin two: and etching to remove a part of the above-mentioned silicon oxide film in the same area in the thickness direction; the cutting step is to form an oxygen-cut film by oxidizing the surface in advance or stacking the oxidized surface, and implanting a specific concentrated product at a specific depth The single ^ substrate of the ion implantation department is cut to cover the above-mentioned last name: "a specific shape of part or almost all of the area to go ^, 上活化步驟，其係洗淨上述絕緣基板與單晶㊉基板，將 該兩基板之表面予以活化； 接合，驟，其係將上述切斷之單晶石夕基板，在室溫下 使植入氫離子側之面密著於上述蝕刻除去之區域，接合 上述兩基板；及 口 單晶石夕薄膜形成步驟，其係藉由熱處理，以上述氯離 子植入部為邊界劈開剝離，於上述絕緣基板上形成單晶 -11 - 200306002 52. 一種半導體裝置之製造方法， 多晶矽薄膜與單晶矽薄膜，且 申請專利範圍糸賈頁 其係在絕緣基板上形成有 包含： 堆積步驟’其係於絕緣基板表面堆積氧化石夕膜； 切斷步驟，其係將預先氧化表面或堆積氧化膜，於表 面形成氧切膜，且具有在特定深度植人特定濃度之氫 離子之虱離子植人部之單晶⑪基板切割成特定形狀；In the activation step, it cleans the above-mentioned insulating substrate and the single-crystal osmium substrate, and activates the surfaces of the two substrates; bonding, and then, the above-mentioned cut-off single-crystal substrate is implanted at room temperature. The surface on the hydrogen ion side is in close contact with the area removed by the etching, and the two substrates are bonded; and the step of forming a monocrystalline silicon thin film is split and peeled by the heat treatment with the chloride ion implantation portion as a boundary, and is insulated on the insulation. Forming a single crystal on a substrate-11-200306002 52. A method for manufacturing a semiconductor device, a polycrystalline silicon film and a single crystal silicon film, and the scope of the patent application, which is formed on an insulating substrate, includes: a stacking step, which is based on insulation Oxidation stone film is deposited on the surface of the substrate; the cutting step is to oxidize the surface or deposit the oxide film in advance to form an oxygen cutting film on the surface, and implant the lice ions into the human body at a specific depth to implant hydrogen ions of a specific concentration. The wafer substrate is cut into a specific shape; ^活化步驟，其係洗淨上述絕緣基板與單晶⑪基板，將 该兩基板表面予以活化； 密著接合步驟，其係將上述切斷之單晶石夕基板，在室 ，下使植人氫離子側之面密著接合於上述絕緣基板之 氧化石夕膜侧表面之特定位置； 單晶矽薄膜形成步驟， 子植入部為邊界劈開剝離 石夕薄膜； 其係藉由熱處理，以上述氫離 ’於上述絕緣基板上形成單晶 係於上述絕緣基板上依序堆積絕緣膜 非晶質矽膜；及 53.^ The activation step is to clean the above-mentioned insulating substrate and the single-crystal osmium substrate, and to activate the surfaces of the two substrates; the close bonding step is to cut the above-mentioned single-crystal slab substrate, and implant it in the chamber. The surface of the hydrogen ion side is tightly bonded to a specific position on the side surface of the oxidized stone film of the above-mentioned insulating substrate; in the step of forming the single crystal silicon film, the sub-implanted part is a boundary cleave peeled stone film; Hydrogen ion 'on the above-mentioned insulating substrate to form a single crystal system on the above-mentioned insulating substrate in order to sequentially deposit an insulating film amorphous silicon film; and 53. 多晶石夕薄膜形成步驟，其係將上述非晶質石夕膜予以 熱，使多晶石夕層生長而形成多晶石夕薄膜。 =半導體裝置之製造方法，其係在絕緣基板上形成 夕曰曰矽薄膜與單晶矽薄膜，且包含： 堆積步驟，其係於絕緣基板表面堆積氧化石夕膜； :刻除去步驟’其係蝕刻除去特定區域之上述氧化 勝在厚度方向之一部分； 切斷步驟’其係將預先氧化表面或堆積氧化膜，於 • 12 - 200306002 輸專利範圔續頁 面形成氧切膜，μ有在特定深度植人特定 離子之氫離子植入部之單Β々其 又風 ^入i 早日日矽基板切割成覆蓋上述蚀 刻除去區域之—部分或大致全部區域之特定形狀； ::步：，其係洗淨上述絕緣基板與單晶石夕基板，將 口亥兩基板表面予以活化； :著接合㈣’其係、將上述㈣之單^基板之植入 鼠：子曰側之面，在室溫下密著接合於上述蝕刻除去區域; 子：B曰彻形成步驟’其係藉由熱處理，以上述氫離 子植入部為邊界劈開剝離，而形成單晶矽薄膜； 堆積步驟，其係於上述絕緣美拓 、 非晶質麵；&amp; e緣基板上依序堆積絕緣膜及 54.The polycrystalline stone thin film forming step is to heat the above-mentioned amorphous stone polycrystalline film to grow a polycrystalline polycrystalline layer to form a polycrystalline polycrystalline film. = Semiconductor device manufacturing method, which is to form a silicon thin film and a single crystal silicon thin film on an insulating substrate, and includes: a stacking step which deposits an oxide stone film on the surface of the insulating substrate; Etching removes a part of the above-mentioned oxide in a specific direction in the thickness direction; the cutting step is to oxidize the surface in advance or deposit an oxide film, and form an oxygen-cut film on • 12-200306002 Patent Continuation Page. Μ has a certain depth The single ion implantation part of the hydrogen ion implantation part of the human being, it is windy, and it will be cut into a specific shape covering a part or almost all of the above-mentioned etching-removed area as early as possible; :: Step :, it is washed Clean the above-mentioned insulating substrate and single crystal substrate, and activate the surfaces of the two substrates;: Bond the ㈣ 'system, and implant the single ^ substrate of the ㈣ above into the rat: the side surface at room temperature, at room temperature Tightly bonded to the above-mentioned etch-removed area; sub-B: a complete formation step 'which forms a single-crystal silicon thin film by cleaving and stripping with the hydrogen ion implantation portion as a boundary by heat treatment; Stacking step, which is based on the above-mentioned insulating MITO, amorphous surface; &amp; e-substrate sequentially stacked insulating film and 54. 敎多rrf膜形成步驟，其係將上述非晶質石夕膜予以加 …、使夕曰日矽層生長而形成多晶矽薄膜。 嶋置之製造方法，其係在絕緣基板上形成有 夕日日矽溥膜與單晶矽薄膜，且包含：The step of forming a multi-rrf film is to add the aforementioned amorphous stone film to a polysilicon film by growing the silicon layer. The manufacturing method of the device is to form a silicon substrate and a single crystal silicon film on an insulating substrate, and include: 膜堆二步：:其係於絕緣基板表面依序堆積第-㈣ 胰、非晶質矽膜及第二氧化矽膜； 露出步驟，其係蝕刻除去上述第二氧化0 ^ β ^ 域，使上述非晶詩膜之—部^出减#之特定區 自旋塗敷步驟，其係氧化上述露出之非晶❹膜而妒 成乳化m ’於該氧化膜上自旋塗敷醋酸鎳水溶液./ 多晶矽薄膜形成步驟’其係將上述非晶質矽膜 …，使藉由金屬協助而促進結晶生長之 17 而形成多晶矽薄膜； 7層生長， -13- 200306002 申請專利範圍續頁 除去步驟，其係除去上述 化矽肤與上述氧化膜 域钱刻除去步驟，其係钱刻除去上述多晶石夕層之特定區 :斷步驟，其係將預先氧化表面或堆積氧化膜，於表 ==:，且/有在θ特定深度植-特定濃度之氫 入°卩之早晶矽基板切割成覆蓋上述蝕 刻除去區域之一部分或大致全部區域之特定形狀，· =步驟，其係洗淨上述絕緣基板與單晶⑦基板，將 邊兩基板表面予以活化； :合步驟，其係將上述切斷之單晶石夕基板，在室溫下 使植入氣離子侧之面密㈣上述_除去區域，接合上 述兩基板；及 單晶石夕薄膜形成步驟，其係藉由熱處理，以上述氫離 子植入部為邊界劈開剝離’於上述絕緣基板上形成單晶 矽薄膜。 55Two steps of the film stack: it is to sequentially deposit the first-pancreas, the amorphous silicon film, and the second silicon oxide film on the surface of the insulating substrate; the exposure step is to remove the second oxide 0 ^ β ^ domain by etching, so that The above-mentioned amorphous poetry film-part ^ 出 MIN # spin-coating step in a specific region, which is to oxidize the exposed amorphous ytterbium film and jealously emulsify m 'to spin-coat the nickel acetate aqueous solution on the oxide film. / Polycrystalline silicon thin film formation step 'It is a polycrystalline silicon thin film formed by the above amorphous silicon film ... to promote the growth of crystals with the assistance of metal; 7-layer growth, -13-200306002 Application for the scope of patent continuation page removal step, which It is a step of removing the above-mentioned siliconized skin and the above-mentioned oxide film, which is a step of removing a specific region of the polycrystalline stone layer: a step of breaking, which is to oxidize the surface or deposit an oxide film in advance, as shown in the table ==: And / with a pre-crystal silicon substrate implanted at a specific depth of θ-a specific concentration of hydrogen into ° 卩 into a specific shape covering a part or almost all of the above-mentioned etch-removed area, a step of washing the insulating substrate Single crystal ⑦Substrate, the surface of the two substrates are activated;: combination step, which is the above-mentioned cut single crystal substrate, the surface of the implanted ion side is sealed at room temperature above the _ removal area, and the two A substrate; and a step of forming a monocrystalline silicon thin film, which forms a single-crystalline silicon thin film on the insulating substrate by heat splitting and peeling off the hydrogen ion implantation portion as a boundary. 55 如申請專利範圍第5〇至54項中任一項之半導體裝置之 製造方法’其中藉由300t以上’ 65(rc以下之一個階段 或夕卩白!又之溫度步驟進行上述熱處理。 56.如申請專利範圍第5〇至54項中任一項之半導體裝置之 製造方法，其中使上述多晶⑪層生長時，於上^晶質 矽膜内添加鎳、鉑、錫、鈀中之至少一種。 、 57·如申請專利範圍第5〇至54項中任一項之半導體裝置之 製造方法，其中藉由雷射照射’使上述單晶石夕基板之氮 離子植入部溫度昇溫至氫自矽脫離之溫度以上，進行以 -14- 200306002 甲請拿利範_賣頁 氫離子植入部為邊界劈開剝離上述單晶矽基板之步驟。 制申°月專利範圍第50至54項中任一項之半導體裝置之 衣w方法，其中藉由進行包含大致7〇〇它以上之峰值溫 度的燈退火’以氫離子植人部為邊界剝離上述單晶石夕基 ”，丨，…上T1士一項之半For example, if the method for manufacturing a semiconductor device according to any one of claims 50 to 54 is applied, the above-mentioned heat treatment is performed by a temperature step of 300 t or more and 65 (rc or less) or a temperature step. 56. Such as The method for manufacturing a semiconductor device according to any one of claims 50 to 54, wherein at least one of nickel, platinum, tin, and palladium is added to the upper crystalline silicon film when the polycrystalline silicon layer is grown. 57. The method for manufacturing a semiconductor device according to any one of claims 50 to 54 in the patent application range, wherein the temperature of the nitrogen ion implantation part of the single crystal substrate is raised to hydrogen from Above the temperature at which the silicon is detached, perform the step of cleaving and peeling the above-mentioned single crystal silicon substrate with a -14-200306002 A. Please take the hydrogen ion implantation section as a boundary. Any one of the 50th to 54th patent scope Item of the method of semiconductor device, in which the above-mentioned single crystal yoke is peeled off with a hydrogen ion implanted part as a boundary by performing a lamp annealing including a peak temperature of approximately 700 or more thereof, and T1 Half of one 其中於上述絕緣基板上形成有上述多晶石夕 朕人上述早晶矽薄膜後，進一步包含： ，：：：去步驟:其係藉由等方性電漿敍刻或濕式姓 7示去上述單晶矽薄膜表面之損傷層； 島狀圖案化步驟，立你驻 + /糸猎由蝕刻上述多晶矽薄膜與_ 过早曰曰矽溥膜而圖案化成島狀； 薄其係於整個上述多晶石夕薄膜與上述單^ : ㈣㈣氧切膜後，藉由異方性钱刻，保^ ^ 化石夕膜之一部分，或回姓膜厚全部；及 閘極絕緣膜。 ，、係猎由堆積氧切膜而則Wherein, after the polycrystalline stone and the early-crystal silicon thin film are formed on the insulating substrate, the method further includes:, ::: Step: It is shown by isotropic plasma engraving or wet type 7 Damage layer on the surface of the above single-crystal silicon film; The island-like patterning step is performed by etching the polycrystalline silicon film and the silicon-silicon film prematurely; and it is patterned into an island shape; After the crystal stone film and the above-mentioned monolayer: oxygen-cut film, a part of the fossil layer film, or the entire film thickness is saved by an anisotropic money engraving; and a gate insulating film. ,, Department of hunting by stacked oxygen cut film 6〇.如申請專利範圍第5〇 製造方法，兑中於…員中任一項之半導體裝置$ 膜與上述單晶成有上述多晶㈣ 餘刻除去步驟，1係菇 ，蝕刻除去上述單曰欲二、電漿蝕刻或濕式蝕亥( 島狀圖案化步j = ^ 述單晶石夕薄膜而圖案化成：狀；…多晶嫌舆上 -15- 200306002 衷請麵範圍續頁 —塗敷步驟，其係於整個上述多晶梦薄膜及上述單晶石夕 薄膜上堆積回钮用氧化石夕膜後，&amp; 一步全面塗敷樹脂平 坦化膜； 回蝕步驟，其係藉由異方性蝕刻，回蝕上述樹脂平坦 化膜之全部與上述回蝕用之氧化矽膜之一部分；及 閘極絕緣膜形成步驟，其係藉由堆積氧化矽膜形成閘 極絕緣膜。 6!.如申請專利範圍第50至54項中任一項之半導體裝置之 製造方法，其中進一步包含P +離子植入步驟，其係藉由 蝕刻形成於上述絕緣基板上之上述單晶矽薄膜與^述 多晶矽薄膜，圖案化成島狀，而形成M〇s電晶體，^^型 MOS電晶體及P型M0S電晶體之源極及汲極區域之至少 一部分大致植入l〇15/cm2以上，5xl〇i5/cm2以下之p+離子。 62·如申請專利範圍第5〇至54項中任一項之半導體裝置之 製造方法，其中上述單晶矽薄膜之膜厚與上述多晶矽薄 膜之膜厚大致相等。 63·如申請專利範圍第5〇至54項中任一項之半導體裝置之 ‘ ie方法其中形成於單晶石夕基板表面之氧化石夕膜之膜 厚在200 nm以上。 64·如申請專利範圍第50至54項中任一項之半導體裝置之 ‘ k方法，其中形成於單晶石夕基板表面之氧化石夕膜之膜 厚在300 nm以上。 65·如申請專利範圍第50至54項中任一項之半導體裝置之 製造方法，其中上述單晶矽薄膜之最大尺寸在1〇 cm以 - 16- 200306002 申請專利範圔續頁 66. 67. 68. 69. 70. 71. 下。 如申請專利範圍第50至54項中任一項之半導體裝置之 製造方法，其中上述單晶矽薄膜之最大尺寸在5 〇ηι以下。 如申凊專利範圍第5 〇至5 4項中任一項之半導體裝置之 製造方法，其中上述單晶矽薄膜與上述絕緣基板之規格 化之線膨脹差，大致於室溫以上，600t以下之溫度範 圍内約在250 ppm以下。 如申請專利範圍第50至54項中任一項之半導體裝置之 製造方法，其中植入上述氫離子植入部之氫離子劑量在 1 〇16/cm2 以上。 如申請專利範圍第50至54項中任一項之半導體裝置之 製造方法，其中植入上述氫離子植入部之氫離子劑量大 致為 3xl〇16/cm2。 如申請專利範圍第12至14,50至54項中任_項之半導體 裝置之製造方法’其中前述單晶矽薄膜之最大尺寸在二 cm以下。 如申請專鄕圍第12至14，赃則巾任—項 I置之製造方法，其中前述單曰 Μ 、 _ 、 j這早日日矽溥肤之最大尺寸在560. If the manufacturing method of the scope of patent application is No. 50, the semiconductor device of any one of the $ members and the above-mentioned single crystal is formed into the above-mentioned polycrystalline silicon. The remaining removal step is a series of mushrooms, and the above-mentioned single is removed by etching. Yu Er 2. Plasma etching or wet etching (island-like patterning step j = ^ The monocrystalline stone thin film is patterned into a shape: ... Polycrystalline 1-15-200306002 Sincerely, please continue to page range— The coating step is to deposit the oxide oxide film for the button on the entire polycrystalline dream film and the single-crystal stone film, and then apply the resin flattening film in one step; the etchback step is performed by Anisotropic etching etches back all of the resin flattening film and a part of the silicon oxide film used for the etch-back; and the gate insulating film forming step, which forms the gate insulating film by stacking the silicon oxide film. 6! The method for manufacturing a semiconductor device according to any one of claims 50 to 54, further comprising a P + ion implantation step, which is formed by etching the above-mentioned single-crystal silicon thin film and the above-mentioned insulating substrate Polycrystalline silicon thin film, patterned into An island shape is formed, and at least a part of the source and drain regions of the MOS transistor, the ^ -type MOS transistor, and the P-type MOS transistor is implanted at least about 1015 / cm2 and less than 5x10i5 / cm2. p + ion. 62. The method for manufacturing a semiconductor device according to any one of claims 50 to 54, wherein the film thickness of the single-crystal silicon thin film is approximately equal to the film thickness of the poly-crystalline silicon thin film. 63. If a patent is applied The method of the semiconductor device according to any one of the range 50 to 54, wherein the film thickness of the oxide stone film formed on the surface of the single crystal substrate is 200 nm or more. The method of the semiconductor device according to any one of the above items, wherein the thickness of the oxide stone film formed on the surface of the single crystal substrate is greater than 300 nm. 65. As described in any one of the claims 50 to 54 The method for manufacturing a semiconductor device, wherein the maximum size of the above-mentioned single crystal silicon thin film is in the range of 10 cm-16- 200306002, and the application for a patent is continued on 66. 67. 68. 69. 70. 71. Manufacturing of a semiconductor device according to any one of 50 to 54 Method, wherein the maximum size of the above-mentioned single crystal silicon thin film is less than 50 nm. The method for manufacturing a semiconductor device according to any one of claims 50 to 54 of the patent scope, wherein the above-mentioned single crystal silicon thin film and the above-mentioned insulating substrate The normalized linear expansion difference is approximately above room temperature and below 250 ppm in a temperature range below 600t. For example, a method for manufacturing a semiconductor device according to any one of the 50th to 54th scope of the patent application, wherein the above is implanted The hydrogen ion implantation portion has a hydrogen ion dose of more than 1016 / cm2. For example, the method for manufacturing a semiconductor device according to any one of claims 50 to 54, wherein the dose of hydrogen ions implanted into the hydrogen ion implantation portion is approximately 3 × 10 16 / cm 2. For example, the method for manufacturing a semiconductor device in any of the 12th, 14,50th, and 54th in the scope of the patent application ', wherein the maximum size of the aforementioned single crystal silicon thin film is less than 2 cm. For example, if you apply for the 12th to 14th, and the manufacturing method of the item I is the item, the maximum size of the silicon skin at the earliest date is M, _, j. -17--17-
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TWI816513B (en) * 2021-12-27 2023-09-21 大陸商西安奕斯偉材料科技股份有限公司 A method and system for measuring wafer surface damage depth

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FR2837980B1 (en) 2007-04-06
US7619250B2 (en) 2009-11-17
US7884367B2 (en) 2011-02-08
US20100019242A1 (en) 2010-01-28
US7119365B2 (en) 2006-10-10
TWI235486B (en) 2005-07-01
KR100532557B1 (en) 2005-12-01
FR2837980A1 (en) 2003-10-03
US20030183876A1 (en) 2003-10-02

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