GB0914251D0 - A hybrid substrate - Google Patents
A hybrid substrateInfo
- Publication number
- GB0914251D0 GB0914251D0 GBGB0914251.4A GB0914251A GB0914251D0 GB 0914251 D0 GB0914251 D0 GB 0914251D0 GB 0914251 A GB0914251 A GB 0914251A GB 0914251 D0 GB0914251 D0 GB 0914251D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- hybrid substrate
- hybrid
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/185—Joining of semiconductor bodies for junction formation
- H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBGB0914251.4A GB0914251D0 (en) | 2009-08-14 | 2009-08-14 | A hybrid substrate |
| PCT/IE2010/000049 WO2011018780A1 (en) | 2009-08-14 | 2010-08-16 | A process for manufacturing a hybrid substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GBGB0914251.4A GB0914251D0 (en) | 2009-08-14 | 2009-08-14 | A hybrid substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB0914251D0 true GB0914251D0 (en) | 2009-09-30 |
Family
ID=41171415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GBGB0914251.4A Ceased GB0914251D0 (en) | 2009-08-14 | 2009-08-14 | A hybrid substrate |
Country Status (2)
| Country | Link |
|---|---|
| GB (1) | GB0914251D0 (en) |
| WO (1) | WO2011018780A1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2971885A1 (en) | 2011-02-18 | 2012-08-24 | Commissariat Energie Atomique | METHOD FOR MAKING A SUBSTRATE SUPPORT |
| CN113066749A (en) * | 2020-01-02 | 2021-07-02 | 中国科学院上海微系统与信息技术研究所 | Multi-material coplanar heterogeneous integrated structure and preparation method thereof |
| FR3144389B1 (en) * | 2022-12-22 | 2025-06-20 | Soitec Silicon On Insulator | METHOD FOR MANUFACTURING A STRUCTURE COMPRISING AT LEAST TWO PANELS ON A SUBSTRATE |
| FR3156984A1 (en) * | 2023-12-14 | 2025-06-20 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | CHIP TRANSFER PROCESS |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2681472B1 (en) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | PROCESS FOR PRODUCING THIN FILMS OF SEMICONDUCTOR MATERIAL. |
| US5545291A (en) * | 1993-12-17 | 1996-08-13 | The Regents Of The University Of California | Method for fabricating self-assembling microstructures |
| US6616854B2 (en) * | 2001-12-17 | 2003-09-09 | Motorola, Inc. | Method of bonding and transferring a material to form a semiconductor device |
| US7119365B2 (en) * | 2002-03-26 | 2006-10-10 | Sharp Kabushiki Kaisha | Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate |
| KR20080080833A (en) | 2007-03-02 | 2008-09-05 | 삼성전자주식회사 | Manufacturing Method of Semiconductor Wafer |
| KR101443580B1 (en) | 2007-05-11 | 2014-10-30 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method for manufacturing semiconductor device |
| JP5507063B2 (en) * | 2007-07-09 | 2014-05-28 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
-
2009
- 2009-08-14 GB GBGB0914251.4A patent/GB0914251D0/en not_active Ceased
-
2010
- 2010-08-16 WO PCT/IE2010/000049 patent/WO2011018780A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011018780A1 (en) | 2011-02-17 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AT | Applications terminated before publication under section 16(1) |