JP2000021782A - Method of forming single crystal silicon layer and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformly epitaxially grow an Si layer at low temps. to make semiconductor elements of a high current density at a high rate by forming steps on a substrate and forming a single crystal Si layer of specified thickness on the substrate including the steps by the catalytic CVD method. SOLUTION: A photo resist 2 is formed in specified pattern on one main surface of an insulation substrate 1 of quartz glass, crystallized glass, etc., and irradiated with e.g. F+ ions 3 of a plasma of CF4 with this resist used as a mask to form a plurality of steps 4 on the substrate 1 by the reactive ion etching(RIE) where the steps 4 are seeds for the epitaxial growth of a single crystal Si and may have a depth d of 0.1 μm and width w of 1.5-1.9 μm, the photo resist 2 is removed and a single crystal Si film 7 is epitaxially grown at several microns to 0.005 μm thick on the entire surface including the steps 4 by the catalytic CVD method.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method of forming a single crystal silicon layer and a method of manufacturing a semiconductor device, and more particularly to an insulated gate field effect transistor using a single crystal silicon layer epitaxially grown on an insulating substrate as an active region. The present invention relates to a method suitable for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a MOSFET (Metal-oxide-semiconductor) using a single crystal silicon layer formed on a substrate.
It is known that a TFT (thin film transistor), which is a field effect transistor, has electron mobility several times larger than that using a polysilicon layer and is suitable for high-speed operation (literature, RPZingg). et al, "First MOSt
ransistors on Insulator by Silicon Saturated Liqui
d Solution Epitaxy ".IEEE ELECTRON DEVICE LETTERS.V
OL.13, NO.5, MAY 1992 p294-6., Japanese Patent Publication No. 4-57098, Masayoshi Matsumura, "Thin Film Transistor" Applied Physics, No. 65
Volume 8 (1996) pp842-848).

In such a semiconductor device, the following various film forming techniques (1) to (5) are known for forming a single crystal silicon layer on a substrate.

(1) Silane, dichlorosilane, trichlorosilane and silicon tetrachloride are decomposed at a temperature of about 800 to 1200 ° C. in a hydrogen atmosphere at 100 to 760 Torr to grow single crystal silicon.

(2) Using a single crystal silicon substrate as a seed, an indium silicon solution or an indium gallium silicon solution heated to 920 to 930 ° C.
A silicon epitaxy layer is formed by a cooling process, and a silicon semiconductor layer is formed on this layer. (Reference 1, Soo
Hong Lee, "VERY-LOW-TEMPERATURE LIQUID-PHASE EPITAX
IAL GROWTH OF SILICON ".MATERIALS LETTERS. Vol.9.N
o.2,3 (Jan., 1990) pp53-56. Reference 2, R. Bergmann et al, "M
OS transistors with epitaxial Si, laterally grown o
ver SiO / Sub 2 / by liquid phase epitaxy. "J.Applied
Physics A, vol.A54, no.1 p.103-5.Reference 3, RPZingg et
al, "First MOS transistors on Insulatorby Silicon S
aturated Liquid Solution Epitaxy. "IEEE ELECTRON DE
(VICE LETTERS.VOL.13, NO.5, MAY 1992 p294-6.)

(3) Silicon is epitaxially grown on a sapphire substrate. (Reference 4, GAGarcia, REReed
y, and MLBurger, "High-quality CMOS in thin (100n
m) silicon on sapphire, "IEEE ELECTRON DEVICE LETTER
(S.VOL.9, pp32-34, Jan.1988.)

(4) A silicon layer is formed on an insulating substrate by an oxygen ion implantation method. (Reference 5, K. Izumi, M. Doken,
and H. Ariyoshtl, "CMOS device fabrication on buried
SiO ₂ layers formed by oxygen implantation into si
licon, "Electron.Lett., vol.14, no.18, pp593-594, Aug.1
978.)

(5) forming steps on a quartz substrate,
A polysilicon layer is formed thereon, and this is heated to 1400 ° C. or higher by a laser beam or a strip heater. The heated polysilicon layer forms an epitaxial growth layer with the steps formed on the quartz substrate as nuclei.
(Reference 6, Seijiro Furukawa, "Graphoepitaxy", IEICE Journal, Vol.66, No.5, pp486-489. (1983.May).
7, Geis, MW, et al.:"Crystallographic orientation o
f silicon on an amorphous substrate usingan artifi
cial-relief grating and laser crystallization ", App
l.Phys.Letter, 35,1, pp71-74 (July 1979).
MW, et al .: "Silicon graphoepitaxy", Jpn.J.Appl.Phy
s., Suppl. 20-1, pp. 39-42 (1981).)

[0009]

However, in the prior art, the energy required for the chemical reaction / single crystal growth is all supplied in the form of thermal energy (heating). It cannot be lowered significantly from 800 ° C. Therefore, there is no technique capable of forming a silicon epitaxy layer on a large glass plate having a relatively low strain point. Further, in a technique of forming a step on a glass plate and using the step as a nucleus of epitaxial growth to grow silicon, it is impossible to grow silicon epitaxially at low temperature and uniformly.

An object of the present invention is to provide a method capable of uniformly growing a silicon layer at a low temperature even on a large-sized glass substrate having a relatively low strain point, thereby producing a semiconductor device having a high current density at a high speed. Is to do.

[0011]

That is, the present invention comprises a step of forming a step on a substrate, and a step of forming a single-crystal silicon layer to a predetermined thickness on the substrate including the step by a catalytic CVD method. And a method for forming a single crystal silicon layer.

In addition, the present invention provides a semiconductor device further comprising, in addition to the above-described step of forming the single-crystal silicon layer, a step of thereafter performing a predetermined process on the single-crystal silicon layer to manufacture a semiconductor element. Is also provided.

According to the method of the present invention, the single crystal silicon is deposited (epitaxially grown) by the catalytic CVD method using the step formed on the substrate as a seed, so that the following (A) to (C) are remarkable. Various operational effects can be obtained.

(A) The above-mentioned step is used as a nucleus of silicon epitaxy, and a catalytic CVD method (chemical vapor deposition using a catalyst: substrate temperature of 200 to 80) is formed on this step.
Since it can be formed by a low-temperature film forming technique of 0 ° C., particularly 200 to 600 ° C.), a silicon single crystal film can be uniformly formed on a substrate at a low temperature.

(B) Therefore, not only quartz glass, but also a glass substrate or a ceramic substrate having a relatively low strain point, which is easily available, can be used at a low cost, and has good physical properties, can be used. It can be made longer (100 m or more) and larger (1 m ² or more).

(C) The electron mobility of a silicon single crystal thin film formed on a glass substrate or the like at a low temperature is 540 cm ² / v
· Sec (Reference 3 mentioned above), and since a value as large as that of a silicon substrate can be obtained, a high-speed, high-current-density top-gate, bottom-gate, or dual-gate LCD
(Liquid Crystal Display) TFT, EL (Electro Luminescence Element), FED (Field Emission Type Display Element) Transistor, High-Performance Diode, Solar Cell, Capacitor, Resistor and Other Semiconductor Elements An integrated electronic circuit can be formed on a glass substrate or the like.

[0017]

In the method of the present invention, the steps are formed on an insulating substrate by dry etching such as reactive ion etching, and the single-crystal silicon layer is formed by catalytic CVD (substrate temperature of about 200 to 800 ° C.). Can be formed.

In forming the single-crystal silicon layer by the catalytic CVD method, a gas containing silicon hydride as a main component is brought into contact with a catalyst heated to, for example, 800 to 2000 ° C. (less than the melting point) to decompose it. The single crystal silicon layer can be deposited on the substrate.

In this case, silane is used as the silicon hydride, and the catalyst is made of tungsten, tungsten containing thorium oxide, molybdenum, platinum, palladium, silicon, alumina, a ceramic to which a metal is attached, and silicon carbide. At least one material selected from the group may be used.

In the method of the present invention, an insulating substrate, in particular, a glass substrate having a low strain point can be used as the substrate, so that a semiconductor crystal layer can be formed on a large-sized glass substrate (1 m ² or more). Since the substrate temperature during catalytic CVD is low as described above, the glass substrate has a strain point of 470.
Glass as low as ６670 ° C. can be used. This is inexpensive, easy to thin, and can produce a long rolled glass sheet. Using this, a thin epitaxy layer can be produced continuously or discontinuously on a long rolled glass plate using the above technique.

As described above, the constituent elements are easily diffused from the glass to the upper layer of the glass having a low strain point.
For the purpose of suppressing this, it is preferable to form a thin film of the diffusion barrier layer (for example, silicon nitride: thickness of about 10 to 1000 °).

After depositing the single-crystal silicon layer using the above-described steps as a seed, a predetermined process is performed on the single-crystal silicon layer to manufacture a semiconductor device.

It should be noted that, during the above-mentioned single-crystal silicon film formation, 3
Group or group V element (B, P, Sb, As, etc.) B ₂ H ₆
And PH ₃ was supplied as such, if appropriate amount dope, it is possible to arbitrarily control the P-type / N-type and / or the carrier concentration of the growing silicon epitaxial layer.

As described above, the single crystal silicon layer epitaxially grown on the substrate is applied to the channel region, the source region, and the drain region of the insulated gate field effect transistor, and the impurity species and / or the concentration of each of these regions are controlled. can do.

Next, preferred embodiments of the present invention will be described in more detail.

This embodiment will be described with reference to FIGS.

First, as shown in FIG. 1A, an insulating substrate 1 made of quartz glass, crystallized glass or the like (in particular, having a strain point of about 470 to 1400 ° C., further 470 to 670 ° C., and a thickness of 5 to 5 ° C.)
On one main surface of a glass substrate (0 μm to several mm), a photoresist 2 is formed in a predetermined pattern, and using this as a mask, for example, F ⁺ ions 3 of CF ₄ plasma are irradiated, and the substrate is subjected to reactive ion etching (RIE). A plurality of steps 4 are formed in one. In this case, the step 4 serves as a seed at the time of epitaxial growth of single-crystal silicon described later, and has a depth d of 0.1 μm and a width w of 1.5 to 1.9 μm.
It may be.

Next, as shown in FIG. 1 (2), after the photoresist 2 is removed, a catalytic CVD method (substrate temperature of 200) disclosed in JP-A-63-40314 or the like is used.
Up to 800 ° C., the single-crystal silicon film 7 is formed on the entire surface including the step 4 by several μm to 0.005 μm (for example, 0.1 μm).
m) is epitaxially grown to a thickness of m).

In this case, the catalytic CVD may be performed using the apparatus shown in FIG. According to this catalytic CVD apparatus,
The silicon hydride (e.g., monosilane) gas 40 (and optionally the doping gas such as B ₂ H ₆ and PH ₃₎ is introduced from the supply conduit to the deposition chamber 41. Inside the deposition chamber 41, a susceptor 42 for supporting the substrate 1 and a coil-shaped catalyst body 43 arranged opposite to the susceptor are arranged. Then, the substrate 1 is heated by an external heating means 44 (for example, an electric heating means), and the catalyst body 43 is formed, for example, as a resistance wire at a melting point or lower (especially 800 to 2000).
C., and about 1700 ° C. in the case of tungsten).

In the deposition chamber 41, the atmosphere is vented from nitrogen to hydrogen (about 15 to 20 minutes),
The temperature is raised to 800 ° C., and the silane gas comes into contact with the catalyst body 43 to be catalytically decomposed and deposited on the substrate 1 maintained at a low temperature (for example, 300 ° C.). The deposition time is determined from the thickness of the epitaxial layer to be grown. After the growth is completed, the temperature is lowered, hydrogen is ventilated to nitrogen, and the substrate 1 is taken out. In this manner, a silicon atom or a group of atoms having high energy is formed by the catalytic reaction or the thermal decomposition reaction by the catalyst body 43 and is deposited on the step 4 serving as a seed. The silicon film can be deposited in a low temperature region that is significantly lower than the possible temperature.

Furthermore, the deposited single-crystal silicon layer 7 has a (100) plane epitaxially grown on a substrate, which is caused by a known phenomenon called graphoepitaxy (see the above-mentioned document 6). , 7, 8). As shown in FIG. 6, when a vertical wall such as the above-described step 4 is formed on an amorphous substrate (glass) 1 and an epitaxy layer is formed thereon, as shown in FIG. 6B, the (100) plane grows along the plane of the step 4 as shown in FIG. The size of the single crystal grain increases in proportion to the temperature and time. However, when the temperature and time are reduced or shortened, the interval between the steps must be shortened. Also, by changing the shape of the above-described steps variously as shown in FIGS.
The crystal orientation of the growth layer can be controlled. When fabricating MOS transistors, the (100) plane is most often employed.

After the single-crystal silicon layer 7 is deposited on the substrate 1 by the catalytic CVD method and the graphoepitaxy, an MO having the single-crystal silicon layer 7 as a channel region is formed.
An S transistor (TFT) is manufactured.

That is, as shown in FIG. 2C, a gate oxide film 8 having a thickness of 350.degree. Is formed on the surface of the single crystal silicon layer 7 by oxidation treatment (950.degree. C.).

Next, as shown in FIG. 2D, in order to control the impurity concentration in the channel region for the N-channel MOS transistor, the P-channel MOS transistor is masked with a photoresist 9 and the P-type impurity ions ( For example, B ⁺ ) 10 is 2.7 × 10 ^{11 at} 10 kV, for example.
ms / cm ² and a single crystal silicon layer 7
Is a silicon layer 11 having a P-type conductivity.

Next, as shown in (5) of FIG. 2, in order to control the impurity concentration in the channel region for the P-channel MOS transistor, the N-channel MOS transistor portion is masked with a photoresist 12 this time, and the N-type impurity is removed. The ions (for example, P ⁺ ) 13 are converted to 1 × 10 ¹¹ at, for example, 10 kV.
The single crystal silicon layer 7 is implanted at a dose of oms / cm ² to form the P-type compensated silicon layer 14.

Next, as shown in FIG. 3 (6), a phosphorus-doped polysilicon layer 15 as a gate electrode material is formed to a thickness of 4000 ° C. by, for example, a CVD method (620 ° C.).
To be deposited.

Next, as shown in FIG. 3 (7), a photoresist 16 is formed in a predetermined pattern, the polysilicon layer 15 is patterned into a gate electrode shape using the photoresist 16 as a mask, and the photoresist 16 is removed. Later, as shown in FIG. 3 (8), for example, O ₂ at 900 ° C. for 60 minutes.
Oxide film 17 is formed on the surface of gate polysilicon 15 by oxidation treatment in the inside.

Next, as shown in FIG. 3 (9), the P-channel MOS transistor portion is masked with a photoresist 18, and for example, As ⁺ ions 19, which are N-type impurities, are subjected to 5 × 10 ¹⁵ atoms / cm at, eg, 20 kV. implanted with ² dose, 40 minutes at 950 ° C., by annealing in N _2, the N-channel MOS transistor N ⁺
Form source region 20 and drain region 21 are formed respectively.

Next, as shown in FIG.
The channel MOS transistor portion is masked with a photoresist 22 and, for example, B ⁺ ions 23 as P-type impurities are ion-implanted at, for example, 10 kV at a dose of 5 × 10 ¹⁵ atoms / cm ² , and N _{2 is applied} at 900 ° C. for 5 minutes. By annealing in the inside, a P ⁺ type source region 24 and a drain region 25 of the P channel MOS transistor are formed, respectively.

Next, as shown in FIG. 4 (11), an SiO ₂ film 26 is formed on the entire surface by CVD, for example, at 750.
The thickness of the SiN film 27 is set to, for example, 420.degree.
Then, a boron and phosphorus-doped silicate glass (BPSG) film 28 is formed as a reflow film to a thickness of 6000 ° at 450 ° C.
The BPSG film 28 is reflowed at 900 ° C. in N ₂ , for example.

Next, as shown in FIG. 4 (12), a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is applied to the entire surface including each hole by sputtering or the like at 150 ° C. to a thickness of 1 μm. And a P-channel MOSFET and an N-channel MOS
The source or drain electrode 29 (S or D) and the gate extraction electrode or wiring 30 (G) of each FET are formed to complete each MOS transistor.

As described above, according to the present embodiment, the following remarkable functions and effects can be obtained.

(A) The silicon single crystal thin film 7 can be uniformly formed on the glass substrate 1 at a low temperature of 200 to 600 ° C. by using the step 4 as a seed by the catalytic CVD method.

(B) Therefore, since a silicon single crystal thin film can be formed not only on a glass substrate having a low strain point but also on an insulating substrate such as a ceramic substrate, a substrate material having a low strain point, low cost and good physical properties can be obtained. It can be arbitrarily selected, and the size of the substrate can be increased.

(C) The electron mobility of the silicon single crystal thin film 7 formed on a glass substrate or the like is 540 cm ² / v · s
Since ec and a value as large as that of a silicon substrate can be obtained, a transistor with high speed and high current density can be manufactured.
In addition to transistors, diodes, capacitors, resistors, and the like, and electronic circuits in which these are integrated can be formed over a glass substrate. The process of forming a silicon semiconductor device such as a MOS transistor is almost the same as the conventionally known process of fabricating a polysilicon TFT.

The embodiments of the present invention described above can be variously modified based on the technical idea of the present invention.

[0047]

According to the method of the present invention, single-crystal silicon is deposited by the catalytic CVD method using the step formed on the substrate as a seed, so that a silicon single-crystal film can be uniformly formed on the substrate at a low temperature. Can be formed.

Accordingly, a glass substrate or a ceramic substrate having a relatively low strain point can be easily obtained, a low-cost substrate having good physical properties can be used, the substrate can be made large, and a silicon single crystal can be obtained. The electron mobility of the thin film is 5
40 cm ² / v · sec, a value as large as that of a silicon substrate can be obtained. Therefore, high-speed, high-current-density transistors, high-performance semiconductor devices such as diodes, capacitors, resistors, and the like, or electronic devices in which these are integrated. The circuit can be formed on a glass substrate or the like.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention in the order of steps;

FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the embodiment of the present invention in the order of steps;

FIG. 4 is a sectional view illustrating a manufacturing process of the semiconductor device according to the embodiment of the present invention in the order of steps;

FIG. 5 is a schematic view of a catalytic CVD apparatus used for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a schematic perspective view for explaining the state of silicon crystal growth on an amorphous substrate.

FIG. 7 is a schematic sectional view showing various step shapes and a silicon growth crystal orientation in the graphoepitaxy technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Glass (or quartz) substrate, 4 ... Step, 7 ... Single-crystal silicon layer, 8 ... Gate oxide film, 10, 23 ... P-type impurity ion, 11 ... P-type impurity implantation layer, 13, 19 ... N-type impurity Ion, 14 N-type impurity implanted layer, 15 gate electrode (material), 17 oxide film, 20, 21 N ⁺ source or drain region, 24, 25 P ⁺ source or drain region, 26, 27 , 28 ... insulating film, 29, 30 ... electrodes or wiring

Continued on the front page (72) Inventor Yuichi Sato 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (72) Inventor Hajime Yagi 6-35-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Sony Stock In-house F-term (reference) 5F045 AA03 AB02 AC01 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AE29 AF07 AF12 BB07 CA15 DP04 EB02 EK06 EK26 5F052 CA04 EA11 FA13 JA04 KA10

Claims (15)

[Claims] 1. A method for forming a single-crystal silicon layer, comprising: forming a step on a substrate; and forming a single-crystal silicon layer to a predetermined thickness on the substrate including the step by catalytic CVD. . 2. The method according to claim 1, wherein the step is formed on the insulating substrate by dry etching, and
The method for forming a single-crystal silicon layer according to claim 1, wherein the single-crystal silicon layer is formed at 0 ° C. 3. When forming the single-crystal silicon layer by the catalytic CVD method, a gas containing silicon hydride as a main component is brought into contact with a heated catalyst to decompose the gas, and the single-crystal silicon layer is formed on the substrate. The method for forming a single-crystal silicon layer according to claim 1, wherein: 4. Use of silane as the silicon hydride, tungsten as the catalyst, tungsten containing thorium oxide, molybdenum, platinum, palladium,
4. The method for forming a single-crystal silicon layer according to claim 3, wherein at least one material selected from the group consisting of silicon, alumina, ceramics to which a metal is attached, and silicon carbide is used. 5. The method according to claim 2, wherein a glass substrate is used as the insulating substrate. 6. The method for forming a single crystal silicon layer according to claim 5, wherein a diffusion barrier layer is formed on the glass substrate, and the single crystal silicon layer is formed thereon. 7. The single crystal silicon layer according to claim 1, wherein an impurity element belonging to Group 3 or Group 5 is mixed during the formation of the single crystal silicon layer, thereby controlling the impurity species and / or concentration of the single crystal silicon layer. Forming a single crystal silicon layer. 8. A step of forming a step on the substrate, a step of forming a single-crystal silicon layer to a predetermined thickness on the substrate including the step by a catalytic CVD method, and a predetermined process on the single-crystal silicon layer. Forming a semiconductor element by performing the following. 9. The single crystal silicon layer is applied to a channel region, a source region, and a drain region of an insulated gate field effect transistor, and controls the impurity species and / or concentration of Group 3 or 5 of each of these regions. A method for manufacturing a semiconductor device according to claim 8. 10. The step is formed on an insulating substrate by dry etching, and the single crystal silicon layer is
The method for manufacturing a semiconductor device according to claim 8, wherein the method is performed at 00 ° C. 11. When forming the single-crystal silicon layer by the catalytic CVD method, a gas containing silicon hydride as a main component is brought into contact with a heated catalyst to be decomposed, and the single-crystal silicon layer is formed on the substrate. The method of manufacturing a semiconductor device according to claim 8, wherein is deposited. 12. A group consisting of silane as said silicon hydride, tungsten, thorium-containing tungsten, molybdenum, platinum, palladium, silicon, alumina, metal-adhered ceramics and silicon carbide as said catalyst. The method for manufacturing a semiconductor device according to claim 11, wherein at least one material selected from the group consisting of: 13. The method for manufacturing a semiconductor device according to claim 10, wherein a glass substrate is used as said insulating substrate. 14. The method according to claim 13, wherein a diffusion barrier layer is formed on the glass substrate, and the single crystal silicon layer is formed thereon. 15. The method according to claim 8, wherein an impurity element belonging to Group 3 or Group 5 is mixed during the formation of the single crystal silicon layer, thereby controlling the impurity species and / or concentration of the single crystal silicon layer. Of manufacturing a semiconductor device.