JP2867402B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for growing a semiconductor thin film having excellent crystallinity on an amorphous insulating substrate such as a quartz substrate or a glass substrate.

[Prior Art] A method of forming a polycrystalline silicon thin film or a single crystal silicon thin film having a uniform crystal orientation and a large crystal grain size on an amorphous insulating substrate or an amorphous insulating film is known as SOI (Silicon).
On Insulator) technology. ｛SOI structure formation technology, industrial books｝. When roughly classified, there are a recrystallization method, an epitaxial method, an insulating filling method, and a bonding method. Recrystallization methods are classified into two methods: a method in which silicon is melted and recrystallized by laser annealing or electron beam annealing; and a solid phase growth method in which solid phase growth is performed without raising the temperature to the melting temperature. The solid phase growth method is superior in that it can be recrystallized at a relatively low temperature. It has also been reported that despite the low-temperature heat treatment at 550 ° C., the crystal grains of the silicon thin film grew. ｛IEEE
Electron Device Letters, vol.EDL-8, No.8, p361, A
ugust 1987｝.

[Problem to be Solved by the Invention] In the solid phase growth method, a single crystal silicon seed which is a starting point of crystal growth is required. In the absence of the single crystal silicon seed, the activation energy for solid phase growth is small, but the activation energy for the formation is large. Processing time is required. Many crystal grains grow due to nuclei randomly present in the silicon film, and each of the crystal grains does not grow significantly. Further, since the growth of the crystal grains is random, it is not known at all where the crystal grain boundaries exist in the obtained re-recrystallized silicon thin film. Furthermore, the crystal orientation is not uniform. Therefore, when a thin-film semiconductor device such as a thin-film transistor is manufactured using such a recrystallized silicon thin film, the characteristics vary greatly within the same substrate, making it impractical.

In a conventional method in which an energy beam such as a laser beam or an electron beam is scanned over the entire surface of a substrate to grow a crystal, non-uniform crystal growth occurs by scanning the irradiation of the energy beam. The surface shape has large irregularities. Also, the warpage of the amorphous insulating substrate poses a problem. This problem is particularly serious when a glass substrate having a low softening temperature is used. In addition, an expensive device for scanning the energy beam for controllability is required.

The present invention solves the problem of random nucleation in the SOI method, especially in the solid phase growth method, and grows a flat silicon thin film having a uniform crystal surface with a large crystal grain size over the entire surface of the substrate. The purpose is to control the position of the grain boundaries. In addition, a method for manufacturing a thin film semiconductor device such as a thin film transistor having excellent characteristics on an amorphous insulating substrate such as a quartz substrate or a glass substrate by a simple method which does not require a complicated and expensive device is provided. Things.

[Means for Solving the Problems] The present invention relates to a method for manufacturing a semiconductor device having a semiconductor thin film on a substrate, comprising the steps of: forming an amorphous semiconductor thin film on the substrate; and performing heat treatment in a predetermined gas atmosphere. Recrystallizing the amorphous semiconductor thin film, wherein in the recrystallizing step, graphite having a higher thermal conductivity than a gas used in the predetermined gas atmosphere is brought into contact with the amorphous semiconductor thin film. Then, the amorphous semiconductor is recrystallized from the contact portion of the amorphous semiconductor thin film with the graphite.

The present invention relates to a method for manufacturing a semiconductor device having a semiconductor thin film on a substrate, comprising the steps of: forming an amorphous semiconductor thin film on the substrate; and heat-treating the amorphous semiconductor thin film at 400 ° C. to 700 ° C. Crystallizing, wherein in the re-crystallizing step, the projection is brought into contact with the amorphous semiconductor thin film, and the amorphous semiconductor thin film is contacted with the amorphous semiconductor thin film from the contact point with the projection. Is recrystallized.

The present invention provides a method for manufacturing a semiconductor device having a semiconductor thin film on a substrate, comprising the steps of: forming an amorphous semiconductor thin film on the substrate; and re-crystallizing the amorphous semiconductor thin film by heat treatment. In the step of recrystallizing, a graphite jig is brought into contact with the amorphous semiconductor thin film, and the amorphous semiconductor thin film is re-formed from a contact portion of the amorphous semiconductor thin film with the graphite jig. It is characterized by being crystallized.

Example In FIG. 1A, 1-1 is an amorphous insulating substrate. A quartz substrate or a glass substrate is used. Si
In some cases, a Si substrate covered with O ₂ may be used. When using a quartz substrate or a Si substrate covered with SiO ₂ , it can withstand a high-temperature process of 1200 ° C, but when using a glass substrate, it is limited to low-temperature processes of about 600 ° C or less due to its low softening temperature. Is done. First, an amorphous silicon thin film 1-2 is deposited on an amorphous insulating substrate 1-1. It is desirable that the amorphous silicon thin film 1-2 is uniform, does not contain fine crystallites, and has no crystal growth nucleus at all.
In the case of the LPCVD method, conditions where the deposition temperature is as low as possible and the deposition rate is high are suitable. Decomposition and deposition are possible at a deposition temperature of about 500 ° C. to 560 ° C. when using silane gas (SiH ₄ ) and about 300 ° C. to 500 ° C. when using disilane gas (Si ₂ H ₆ ). Trisilane gas (Si ₃ H ₈ ) has a lower decomposition temperature. If the deposition temperature is increased, the deposited film becomes polycrystalline, and there is also a method in which the film is made amorphous once by implanting Si ions. In the case of the plasma CVD method, the substrate temperature is from room temperature to 500
A film can be formed even at a low temperature of not more than ℃. Further, if hydrogen plasma or argon plasma treatment is performed immediately before deposition, cleaning and film formation of the substrate surface can be continuously performed. Light excitation
The CVD method is also effective in that the low-temperature deposition at 500 ° C. or lower and the substrate surface can be continuously cleaned and formed into a film. In the case of a high vacuum evaporation method such as EB evaporation method, it is easy to take in atmospheric oxygen into the film because the film is porous,
It hinders crystal growth. In order to prevent this, it is useful to perform a low-temperature heat treatment at about 300 ° C. to 500 ° C. before the film is taken out of the vacuum atmosphere to densify the film. The case of the sputtering method is the same as the case of the high vacuum evaporation method.

Next, as shown in FIG. 1 (b), the amorphous silicon thin film 1-2 is brought into contact with a flat graphite jig 1-3 having a dot-like projection structure 1-4. Then, the amorphous silicon thin film 1-2 is solid-phase grown. It is desirable that the size of the tip of the protrusion structure 1-4 be as small as possible. The interval L between the projection structures 1-4 is set to about twice the solid phase growth distance. For example, when solid phase growth advances 5 μm from the seed, L is set to 10 μm. FIG. 1 (f) shows the plane of the flat graphite jig 1-3.
Although the jig is described as being made of graphite, it may be used as a jig as long as it has no problem of impurity contamination and has high thermal conductivity. Incidentally, the thermal conductivity of graphite at 700 ° C. is 35 to 70 (W / m · K), which is about an order of magnitude smaller for a quartz substrate.

Next, the amorphous silicon thin film placed on the flat graphite jig was placed in a quartz annealing furnace.
A low-temperature heat treatment at 500 ° C. to 700 ° C. is performed to grow the amorphous silicon thin film in a solid phase. As an annealing atmosphere, a nitrogen gas, a hydrogen gas, an argon gas, a helium gas, or the like is used. Annealing may be performed in a high vacuum atmosphere of 1 × 10 ⁻⁶ to 1 × 10 ⁻¹⁰ Torr. The thermal conductivity of the atmospheric gas at 1000 ° C is about 7.4 × 10 ^-2 (W / m · K) for nitrogen gas, about 5.0 × 10 ^-2 (W / m · K) for argon gas, and about 4 × 10 for helium gas.
1.9 × 10 ^-2 (W / m · K), about the same for hydrogen gas. The previously mentioned values of the thermal conductivity of graphite are a few orders of magnitude higher. Therefore, the contact point 1- 1 with the dot-like projection structure 1-4 of the flat graphite jig 1-3 is formed.
6 serves as a seed, and the amorphous silicon thin film 1-2 starts to grow in a solid phase radially around the sheet. This is shown in FIG. 1 (c). Reference numeral 1-5 denotes a crystal phase that has been solid-phase grown using a contact point 1-6 between the dot projection structure 1-4 and the amorphous silicon thin film 1-2 as a seed. In this way, the seed, which is the starting point of solid phase growth, is generated by contacting a substance with higher thermal conductivity than the annealing atmosphere gas, so that the heat treatment temperature for solid phase growth can be lower. become. Until now, the heat treatment temperature was 500
Although it has been described as 更 に 700 ° C., a lower temperature such as 400 ° C. to 50 ° C.
Solid phase growth may occur even with a heat treatment at 0 ° C. In the low-temperature annealing, only crystal grains having a crystal orientation with a small activation energy for crystal growth selectively grow, and slowly grow larger.

FIG. 1 (c) is a diagram showing a stage in the middle of the solid phase growth process. Solid phase growth proceeds, and the two adjacent contact points 1-
FIG. 1D shows a state in which the crystal grains grown from both directions collide with each other at an intermediate point of No. 6 to form a crystal grain boundary 1-7. The space between a certain grain boundary 1-7 and the next grain boundary 1-7 is a crystal phase. As described above, if the interval L between the dot-like projection structures 1-4 is set to, for example, 20 μm, the crystal phase 1-5 becomes a center of the contact point 1-6 on a side 20
It is a μm crystal region. In this way, a large-grain polycrystalline silicon thin film in which the locations of crystal grain boundaries are controlled is produced.
FIG. 1 (e) shows the large grain polycrystalline silicon thin film.

An example in which a large-diameter polycrystalline silicon thin film manufactured using the present invention is applied to a thin film transistor will be described with reference to FIG. As shown in FIG.
Since the position of -7 is known, a thin film transistor is manufactured by avoiding this position and making the crystal phase 1-5 a channel region. FIG. 2 (a) shows the large-grain polycrystalline silicon thin film substrate produced as described above. 2-1 is an amorphous insulating substrate. 2-2 is a crystal phase formed by solid phase growth. 2-3 is a crystal grain boundary. Next, the silicon thin film is patterned by photolithography to form an island shape as shown in FIG. 2 (b). At this time, patterning is performed so that the crystal phase 2-2 is located at the center of the island pattern. Next, as shown in FIG. 2C, a gate oxide film 2-4 is formed. As a method of forming the gate oxide film, LPCVD method, or photo-excitation CVD method, or plasma CVD method, ECR plasma CVD method, or high vacuum deposition method, or plasma oxidation method, or 500 ℃ or less such as high-pressure oxidation method There is a low temperature method. The gate oxide film formed by the low-temperature method becomes an excellent film which is denser and has less interface states by heat treatment. When a quartz substrate is used as the amorphous insulating substrate 2-1, a thermal oxidation method can be used. The thermal oxidation method includes a dry oxidation method and a wet oxidation method. The oxidation temperature is as high as 1000 ° C. or more, but the dry oxidation method is more suitable because the thin film is excellent.

Next, as shown in FIG. 2 (d), the gate electrode 2-
5 is formed. At this time, the gate electrode 2-5 is formed so as not to overlap the crystal grain boundaries 2-3. Therefore, the silicon under the gate electrode 2-5 becomes a crystal phase.
As the gate electrode material, a polycrystalline silicon thin film, molybdenum silicon side, a metal film such as aluminum or chromium, or a transparent conductive film such as ITO or SnO ₂ can be used. As a film forming method, there are a CVD method, a sputtering method, a vacuum evaporation method, and the like, but a detailed description thereof is omitted here.

Subsequently, as shown in FIG.
Using -5 as a mask, impurities are ion-implanted to form a source region 2-6 and a drain region 2-7 in a self-aligned manner. In the figure, reference numeral 2-2 denotes a pure crystal region, which is a channel region of the MOS type thin film transistor.
Since the crystal grain boundary 2-3 is buried in the drain region 2-7, there is no adverse effect on the transistor characteristics. As an impurity, when manufacturing an Nch transistor, P ⁺
Or when using As ⁺ to make a Pch transistor
Use B ⁺ or the like. As a method for adding impurities, there is a method such as a laser doping method or a plasma doping method in addition to the ion implantation method. Arrows indicated by 2-8 indicate ion beams of impurities. The amorphous insulating substrate 2
When a quartz substrate is used as -1, a thermal diffusion method can be used. The impurity concentration is about 1 × 10 ¹⁵ to 1 × 10 ²⁰ cm ⁻³ .

Subsequently, as shown in FIG.
-9 is laminated. As the material of the interlayer insulating film, an oxide film or nitriding is used. The film thickness may be any as long as the insulating property is good, but is usually about several thousand to several μm.
As a method for forming a nitride film, LPCVD or plasma C
VD method is simple. For the reaction, ammonia gas (NH
3) Use a mixed gas of silane gas and nitrogen gas, or a mixed gas of silane gas and nitrogen gas.

Here, when hydrogen ions are introduced by a hydrogen plasma method, a hydrogen ion implantation method, or a hydrogen diffusion method from a plasma nitride film, defects such as dangling bonds existing at the gate oxide film interface and the like are inactivated. Is done. Such a hydrogenation step may be performed before stacking the interlayer insulating film 2-9.

Next, as shown in FIG. 2G, a contact hole is formed in the interlayer insulating film and the gate insulating film, a contact electrode is formed, and a source electrode 2-10 and a drain electrode 2-10 are formed.
11 is assumed. The source electrode and the drain electrode are formed of a metal material such as aluminum. Thus, a thin film transistor is formed.

Conventionally, it has not been known how many grain boundaries exist in the channel region of a thin film transistor. It was not possible to know where the grain boundaries existed or how large the crystal grain size was. However, according to the present invention, a large crystal grain size can be obtained, and the location of the crystal grain boundary can be controlled. Since only the crystal region excluding the crystal grain boundary portion can be used as the channel region, the ON current of the thin film transistor increases and the OFF current decreases as compared with the related art. Also, the threshold voltage is reduced, and the transistor characteristics are greatly improved. The variation in transistor characteristics is very small.

This makes it possible to produce a silicon thin film having excellent crystallinity with controlled locations of crystal grain boundaries on an amorphous insulating substrate, which greatly contributes to the development of SOI technology. Since the seed is formed by using a jig made of a material with high thermal conductivity such as graphite, the photo process, etc.
The number of steps does not increase at all. Since it can be manufactured even in a low-temperature process of 600 ° C. or less, a glass substrate that is inexpensive and has a low heat-resistant temperature can be used. Although an excellent silicon thin film can be obtained, the cost does not increase.

In the solid phase growth method, a jig made of a material having a thermal conductivity much larger than the atmosphere gas for heat treatment is used.
By performing the heat treatment in contact with the amorphous silicon thin film, a temperature difference occurs on the amorphous silicon thin film, and this contact point has a higher temperature than the atmospheric gas. In this way, a seed is formed. Therefore, the heat treatment temperature for solid phase growth can be further reduced.

Since a thin film transistor having excellent characteristics can be formed on an amorphous insulating substrate, a sufficiently high-speed operation can be realized even when the driver circuit is applied to an active matrix substrate integrated on the same substrate. Furthermore, there is a great effect on reduction of power supply voltage, reduction of current consumption, and improvement of reliability. Further, since it can be manufactured by a low-temperature process of 600 ° C. or less, the effect is large even when the active matrix substrate is reduced in cost and its area is increased.

When the present invention is applied to a contact type image sensor in which a photoelectric conversion element and its scanning circuit are integrated in the same chip, a very large reading speed, a high resolution, and a very large gradation are required. Produce effects. When a higher resolution is achieved, application to a contact image sensor for color reading becomes easier. Of course, the effect is great also for reduction of power supply voltage, reduction of current consumption, and improvement of reliability.
Also, since it can be manufactured by a low temperature process,
The length of the contact type image sensor chip can be increased,
A single chip can realize a reading device for large facsimile such as A4 size or A3 size. Therefore, it is possible to avoid troublesome techniques such as double splicing of sensor chips and unreliable technology, and the mounting yield is improved.

Not only quartz substrate or a glass substrate, a sapphire substrate (Al ₂ O ₃₎ or _{MgO · Al 2 O 3, BP} , can be used crystalline insulating substrate CaF ₂ and the like.

[Effects of the Invention] By satisfying the above-mentioned constitutional requirements, the present invention has remarkable effects as described below.

(A) Since a substance having a high thermal conductivity is brought into contact with the amorphous semiconductor thin film to perform solid phase growth, a large crystal grain size can be obtained, and the mobility of the semiconductor device can be improved.

(B) In the heat treatment, a substance having a high thermal conductivity is brought into contact with the amorphous semiconductor thin film, and the amorphous semiconductor thin film is solid-phase grown from the contact portion, so that the heat treatment temperature can be lowered. .

Although the above description has been made by taking a thin film transistor as an example, the present invention can be applied to an element using a thin film such as a bipolar transistor or a heterojunction bipolar transistor. Also, SO such as 3D devices
The present invention can be applied to a device using the I technology.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 (a) to 1 (e) are sectional views showing steps of a method for growing a semiconductor thin film according to the present invention. FIG. 1 (f) is a plan view of the flat graphite jig. 2 (a) to 2 (g) are process diagrams of a thin film transistor showing an example in which the present invention is applied to a thin film transistor. 1-1; amorphous insulating substrate 1-2; amorphous semiconductor thin film 1-3; planar graphite jig 1-4; dot-like projection structure 1-5; crystal phase 1-7; crystal grain boundary 2-2 ; Crystal phase

Claims (3)

(57) [Claims] In a method of manufacturing a semiconductor device having a semiconductor thin film on a substrate, a step of forming an amorphous semiconductor thin film on the substrate and a step of heat-treating the amorphous semiconductor thin film in a predetermined gas atmosphere to recycle the amorphous semiconductor thin film. Crystallizing, wherein in the recrystallizing step, graphite having a higher thermal conductivity than a gas used in the predetermined gas atmosphere is brought into contact with the amorphous semiconductor thin film to form the amorphous semiconductor. A method for manufacturing a semiconductor device, comprising recrystallizing the amorphous semiconductor thin film from a contact portion of the thin film with the graphite. 2. A method of manufacturing a semiconductor device having a semiconductor thin film on a substrate, the method comprising: forming an amorphous semiconductor thin film on the substrate; and heat-treating the amorphous semiconductor thin film at 400 ° C. to 700 ° C. Recrystallizing, wherein in the recrystallizing step, the projection is brought into contact with the amorphous semiconductor thin film, and the amorphous semiconductor thin film is formed from a contact portion of the amorphous semiconductor thin film with the projection. A method for manufacturing a semiconductor device, comprising recrystallizing a thin film. 3. A method of manufacturing a semiconductor device having a semiconductor thin film on a substrate, comprising: forming an amorphous semiconductor thin film on the substrate; and recrystallizing the amorphous semiconductor thin film by heat treatment. In the step of recrystallizing, a graphite jig is brought into contact with the amorphous semiconductor thin film, and the amorphous semiconductor thin film is formed from a contact portion of the amorphous semiconductor thin film with the graphite jig. A method for manufacturing a semiconductor device, comprising recrystallizing.