KR20130115625A - Method for crystallizing amorphous silicon thin film and method for fabricating poly crystalline thin film transistor using the same - Google Patents

Method for crystallizing amorphous silicon thin film and method for fabricating poly crystalline thin film transistor using the same Download PDF

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KR20130115625A
KR20130115625A KR1020120038103A KR20120038103A KR20130115625A KR 20130115625 A KR20130115625 A KR 20130115625A KR 1020120038103 A KR1020120038103 A KR 1020120038103A KR 20120038103 A KR20120038103 A KR 20120038103A KR 20130115625 A KR20130115625 A KR 20130115625A
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amorphous silicon
crystallization
thin film
layer
silicon layer
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KR1020120038103A
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Korean (ko)
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주승기
변창우
손세완
이용우
강현모
박설아
임우창
이도
윤승재
이상주
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주승기
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Priority to KR1020120038103A priority Critical patent/KR20130115625A/en
Priority to US13/630,148 priority patent/US8716112B2/en
Publication of KR20130115625A publication Critical patent/KR20130115625A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02672—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation enhancing elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst

Abstract

PURPOSE: A method for crystallizing an amorphous silicon thin film and a method for fabricating a poly crystalline thin film transistor using the same are provided to prevent the deformation of a glass substrate by performing a crystallization annealing process before deposited amorphous silicon is patterned in an active region. CONSTITUTION: A crystallization induction metal layer is formed on an amorphous silicon layer (20). The crystallization induction metal layer is removed. A metal silicide seed (40) is formed on the amorphous silicon layer. A thermal process is performed on the substrate including the metal silicide seed. The amorphous silicon layer is crystallized.

Description

Method for Crystallizing Amorphous Silicon Thin Film and Method for Fabricating Poly Crystalline Thin Film Transistor Using the Same}

  The present invention relates to a method of crystallizing an amorphous silicon thin film and a method of manufacturing a polycrystalline thin film transistor using the same, and more particularly, when the metal is removed after depositing a crystallization induction metal to amorphous silicon at room temperature, Using amorphous metal silicide Seed Induced Crystallization (SIC) that can crystallize an amorphous silicon thin film without metal contamination by using a dot-type metal silicide as a nucleus during crystallization heat treatment. A crystallization method of a silicon thin film and a method of manufacturing a polycrystalline thin film transistor using the same.

Thin film transistors (TFTs) used to select pixels in display devices such as liquid crystal displays (LCDs) and active matrix organic light emitting diodes (AMOLEDs) typically deposit amorphous silicon on transparent substrates such as glass and quartz, The gate electrode is formed, an impurity is implanted into the source region and the drain region, and annealing is performed to activate the gate electrode, thereby forming an insulating layer.

An active layer forming a source region, a drain region, and a channel region of a thin film transistor is usually formed by depositing an amorphous silicon layer on a transparent substrate such as glass by using a chemical vapor deposition (CVD) method.

However, an amorphous silicon layer deposited directly on a substrate by a method such as chemical vapor deposition (CVD) has a low electron mobility. As display devices using thin film transistors require fast operation speeds and are miniaturized, the integration degree of the driving integrated circuit (IC) is increased and the aperture ratio of the pixel area is reduced. Therefore, the driving circuit is increased by increasing the electron mobility of the silicon film. At the same time, the individual pixel aperture ratio needs to be increased.

In addition, the display market is changing from LCD to AMOLED. AMOLED display devices require switching transistors that can operate at high speed to select and drive pixels at high speed. Such a high speed switching transistor may be implemented using a thin film transistor using polycrystalline silicon having high electron mobility.

Therefore, polycrystalline silicon thin film transistors having high electron mobility in AMOLED display devices are an essential element, which requires a method for crystallizing an amorphous silicon thin film. Currently known crystallization methods include solid state crystallization and excimer laser. Excimer laser crystallization, metal induced crystallization, and the like.

First, solid phase crystallization (SPC) is a method of annealing an amorphous silicon layer over several hours to several tens of hours at a temperature of 600 ° C. or less, which is a deformation temperature of glass forming a substrate. Since the SPC method requires a long time for heat treatment, when the productivity is low and the area of the substrate is large, there is a problem that deformation of the substrate may occur during a long heat treatment process even at a temperature of 600 ° C. or less.

Excimer Laser Crystallization (ELC) is a method in which an excimer laser is injected into an amorphous silicon layer to generate a local high temperature for a very short time to crystallize the amorphous silicon layer instantaneously. The ELC method has a technical difficulty in precisely controlling the scanning of the laser light, and since only one substrate can be processed at a time, there is a problem that productivity is lowered than when batch processing of several substrates at the same time in a furnace. .

In order to overcome the disadvantages of the conventional amorphous silicon layer crystallization method, when a metal such as nickel, gold, aluminum, or the like is contacted with or injected into the silicon, the silicon is induced to undergo phase change at low temperature. The phenomenon is used. This phenomenon is called metal induced crystallization (MIC). When a thin film transistor is manufactured using the MIC phenomenon, a metal remains in crystalline silicon constituting the active layer of the thin film transistor, and in particular, a channel region of the thin film transistor. A problem occurs that causes current leakage.

Recently, metal induced side crystallization (Metal Induced Lateral) does not directly induce a phase change of silicon, but the silicide generated by the reaction between metal and silicon continues to propagate to the side, thereby inducing the crystallization of amorphous silicon. A method of crystallizing a silicon layer using a crystallization (MILC) phenomenon has been proposed (see SW Lee & SK Joo, IEEE Electron Device Letter, 17 (4), p. 160, (1996)).

Nickel and palladium are known as metals that cause such a MILC phenomenon. When the amorphous silicon layer is crystallized using the MILC phenomenon, the silicide interface including the metal moves to the side surface as the phase change of the amorphous silicon layer propagates. Therefore, almost no metal component is used to induce crystallization in the polycrystalline silicon layer crystallized using the MILC phenomenon. As a result, there is an advantage that the influence on the current leakage and other operating characteristics of a transistor having an activation layer made of a polycrystalline silicon layer is not large. In addition, when the MILC phenomenon is used, crystallization of silicon may be induced at a relatively low temperature of 550 ° C. or less, and thus, multiple furnaces may be simultaneously crystallized without damaging the substrate by using a furnace.

Referring to the method of manufacturing a polycrystalline thin film transistor using a conventional MILC as follows. First, amorphous silicon is deposited on a transparent insulating substrate and patterned into an active layer pattern. A gate insulating film and a gate electrode are formed on the active layer region, ion implantation is performed using the gate electrode as a mask, and then a source / drain region. The source / drain regions are crystallized by MIC, and the channel regions are crystallized by MILC, by depositing a crystallization inducing metal and then annealing to fabricate a polycrystalline thin film transistor.

However, in the conventional crystallization method using MILC as described above, MIC / MILC crystallization is performed through a heat treatment process after the crystallization-induced metal deposition in the source / drain region, the metal having a high channel region due to the continuous influx of catalyst metal during the crystallization heat treatment. There is a problem that the electrical properties are degraded due to contamination.

Moreover, the metal side induced crystallization (MILC) method is deposited in the source / drain region after the crystallization heat treatment, so that the remaining metal may not be used as a crystallization catalyst, and the remaining metal may be oxidized.

In addition, there are significant limitations in commercializing MILC technology. This causes crystallization inducing metals such as nickel and palladium to be formed on the active layer through an additional photo / etch process and shrinkage of the glass substrate during the crystallization heat treatment, which makes manufacturing difficult in subsequent gate and wiring formation processes. do. In order to overcome this problem, conventionally, the first treatment process is a process of first compressing the glass substrate. However, the compression process of the glass substrate is applicable to small displays, but not applicable to large area substrates due to the deformation of the glass substrate. As a result, the above-described prior art has no problem in the manufacture of small AMOLEDs, but has a problem that is difficult to apply to the production of large-area AMOLEDs.

Moreover, the metal side induced crystallization (MILC) method has a problem in that the crystallization time is long because crystallization of the channel region is performed by side crystallization.

A conventional amorphous semiconductor thin film crystallization method is disclosed in Korean Patent Publication No. 10-0653853 (November 28, 2006).

The conventional amorphous semiconductor thin film crystallization method disclosed in Korean Patent Publication No. 10-0653853 includes the steps of forming a pair of nonmetal seeds for inducing crystallization of an amorphous semiconductor thin film at a predetermined distance on a transparent insulating substrate; And depositing an amorphous semiconductor thin film on the entire surface, and crystallizing the amorphous semiconductor thin film by epitaxially growing a polycrystalline semiconductor thin film from the nonmetal seed by heat treating the substrate.

The forming of the pair of nonmetal seeds may include depositing an amorphous silicon thin film on an insulating substrate, and using a pair of crystallization inducing metals on the amorphous silicon thin film at a position corresponding to the pair of nonmetal seeds. Selectively forming an island metal pattern, patterning an amorphous silicon thin film using the pair of island metal patterns as an etching mask, and forming a pair of amorphous silicon patterns; and heat treating the substrate to metal silicide. Forming a pair of non-metal seeds, and removing residual metal remaining without silicide in the heat treatment step.

As described above, in the conventional amorphous semiconductor crystallization method disclosed in Korean Patent Publication No. 10-0653853, in order to obtain a metal silicide seed, the first amorphous silicon is patterned only in the source / drain region and crystallized through the crystallization inducing metal, and then, Since the second amorphous silicon is deposited and crystallized, an additional etching process, two processes of depositing amorphous silicon, and two heat treatment processes must be performed, thereby increasing the complexity and manufacturing cost.

In addition, Korean Patent Publication No. 10-0534585 discloses forming an amorphous silicon film on a substrate, forming a sacrificial organic film on the amorphous silicon film, forming a crystallization inducing material film on the sacrificial organic film, and removing the sacrificial organic film. A method of crystallizing an amorphous silicon film has been proposed which includes dropping the crystallization inducing material onto the amorphous silicon film and heat treating the substrate on which the crystallization inducing material is dropped.

In Korean Patent Publication No. 10-0534585, a photoresist is formed with a thickness of 0.2 to 1.5 μm using a sacrificial organic film, and then crystallization is performed by removing the sacrificial organic film using an ashing method, a strip method, a dry etching method or a wet etching method. An inducer is dropped onto an amorphous silicon film and used as a crystallization seed.

When the thin film transistor is formed of a polycrystalline silicon film obtained using such a crystallization seed, it is less contaminated by the crystallization inducing material and the grain size increases as compared with the case where the crystallization inducing material is directly deposited on the amorphous silicon film. In addition, it is disclosed that a polycrystalline silicon film having improved uniformity of crystal grains is obtained, and as a result, leakage current of the thin film transistor is reduced.

However, Korean Patent Publication No. 10-0534585 discloses that the gas used for the dry etching method or the solution used for the wet etching method directly affects the lower polycrystalline silicon thin film to etch the sacrificial organic film, thereby causing the active layer and the gate insulating layer to be etched. There is a disadvantage that the film quality between the non-uniform.

Korean Patent Publication No. 10-0653853 Korean Patent Publication No. 10-0534585

The present invention has been made to solve the above problems of the prior art, the object is to remove the crystallization-inducing metal before the crystallization heat treatment to form a dot-shaped metal silicide on the surface of the amorphous silicon layer, a dot-shaped metal silicide Crystallization method of amorphous silicon thin film by using metal silicide seed induced crystallization (SIC) which can crystallize amorphous silicon thin film without metal contamination by minimizing metal contamination by acting as seed during crystallization heat treatment The present invention provides a method of manufacturing a polycrystalline thin film transistor.

Another object of the present invention is to remove the crystallization-inducing metal on the amorphous silicon thin film immediately after formation to form a dot-shaped metal silicide seed, thereby preventing oxidation of the crystallization-inducing metal and preventing the continuous contamination of the crystallization-inducing metal that could not be removed. The present invention provides a crystallization method of an amorphous silicon thin film and a method of manufacturing a polycrystalline thin film transistor using the same, which can be prevented and can reduce manufacturing cost by simplifying a manufacturing process.

It is still another object of the present invention to prevent the deformation of a glass substrate by performing a crystallization heat treatment after depositing amorphous silicon and before patterning into an active region, and as a result, a method of crystallizing an amorphous silicon thin film capable of producing a display of a large area substrate and The present invention provides a method of manufacturing a polycrystalline thin film transistor using the same.

Another object of the present invention is to produce a polycrystalline silicon thin film using only low-cost sputters and furnaces without using expensive laser equipment, thereby reducing the manufacturing cost of AMOLED panels manufactured by laser crystallization methods. The method of crystallizing an amorphous silicon thin film which can be applied to the crystallization process of a large-area substrate more effectively than the metal induced side crystallization method (MILC) by eliminating the need for compression heat treatment of a glass substrate before forming the activation region, It is to provide a manufacturing method.

Another object of the present invention is to eliminate the crystallization induced metal mask process because the crystal growth in the vertical direction instead of the metal induced side crystallization, it is possible to significantly reduce the heat treatment temperature and time compared to the metal side induced crystallization (MILC) method The present invention provides a method for crystallizing an amorphous silicon thin film.

It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. .

In order to achieve the above object, the crystallization method of the amorphous silicon thin film according to the present invention comprises the steps of forming an amorphous silicon layer on the substrate; Forming a crystallization inducing metal layer on the amorphous silicon layer; Removing the crystallization inducing metal layer to form a metal silicide seed on an amorphous silicon layer; And crystallizing the amorphous silicon layer by heat-treating the substrate on which the metal silicide seed is formed.

The crystallization-inducing metal layer is deposited on the surface of the amorphous silicon layer by a sputtering method, and preferably formed to a thickness of 50 kPa to 100 kPa. In addition, the crystallization induction metal layer may be any one or two or more alloys of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt. .

The crystallization-inducing metal layer may be removed using an acid solution including sulfuric acid (H 2 SO 4 ).

The metal silicide seed is formed in a dot form on the surface of the amorphous silicon layer. In addition, the distribution density of the metal silicide seed may be controlled by the thickness of the crystallization inducing metal layer formed in the amorphous silicon layer.

Method of manufacturing a polycrystalline thin film transistor according to the present invention comprises the steps of forming an amorphous silicon layer on the substrate; Forming a crystallization inducing metal layer on the amorphous silicon layer; Removing the crystallization inducing metal layer to form a plurality of metal silicide seeds in an amorphous silicon layer; Heat-treating the substrate on which the metal silicide seed is formed to crystallize an amorphous silicon layer; Patterning the crystallized polycrystalline silicon layer into an active region; Sequentially forming a gate insulating film and a gate electrode on the polycrystalline silicon layer; And forming a source region and a drain region by implanting N-type or P-type dopant ions into the active region of the polycrystalline silicon layer.

The forming of the gate insulating film and the gate electrode may include depositing an insulating film for forming a gate insulating film and a metal film for forming a gate electrode, forming an etching mask with a photoresist on the insulating film and the metal film, and sequentially etching the same using the same. Steps.

In this case, the gate insulating film may be formed of a silicon oxide film or a silicon nitride film, and the gate electrode may be a conductive material including W, Pt, Ti, Al, Ni, and Mo.

As described above, in the method of crystallizing an amorphous silicon thin film using the metal silicide seed induced crystallization (SIC) according to the present invention, the crystallization-inducing metal is removed before the crystallization heat treatment so that a dot-shaped metal silicide is formed on the surface of the amorphous silicon layer. In this case, the amorphous silicon thin film could be crystallized without metal contamination by using a dot-shaped metal silicide as a seed during crystallization heat treatment.

In addition, in the present invention, since the crystallization-inducing metal is deposited on the amorphous silicon thin film immediately after removal, it forms a dot-shaped metal silicide seed, thereby preventing oxidation of the crystallization-inducing metal and preventing continuous contamination of the crystallization-inducing metal that could not be removed. The manufacturing cost can be reduced by simplifying the manufacturing process.

Furthermore, in the present invention, the crystallization heat treatment is performed after the deposition of the amorphous silicon and before the patterning into the active region, thereby preventing deformation of the glass substrate, and as a result, display manufacturing of a large area substrate is possible.

In addition, in the present invention, a polycrystalline silicon thin film can be manufactured using only low-cost sputters and furnaces without using expensive laser equipment, thereby reducing manufacturing costs of AMOLED panels manufactured by laser crystallization methods. It can be applied to the crystallization process of a large area substrate more effectively than the metal induced side crystallization method (MILC) as it does not require compression heat treatment of the glass substrate before forming the activation region.

Furthermore, in the present invention, since crystal growth is performed in the vertical direction instead of metal-induced side crystallization, a mask process of crystallization-induced metal is not necessary, and heat treatment temperature and time can be greatly reduced as compared to metal side induction crystallization (MILC) method.

1 to 10 are process cross-sectional views sequentially illustrating a method of manufacturing a polycrystalline thin film transistor according to an exemplary embodiment of the present invention.
11 (a) and 11 (b) are graphs showing changes in X-ray photoelectron spectroscopy (XPS) spectra of Si and Ni before and after removing Ni deposited on amorphous silicon, respectively.
FIG. 12 is a graph of Raman spectroscopy of nickel silicide induced crystallized silicon (SIC). FIG.
FIG. 13 is a graph of AES (Auger electron spectroscopy) analysis of the amount of oxygen, nickel and silicon atoms remaining on the surface of polycrystalline silicon after crystallization by two methods, MIC and SIC.
14A and 14B are micrographs of Secoo-etched polycrystalline silicon crystallized by the MIC method and the SIC method, respectively;
14C is an enlarged photograph of a portion of FIG. 14B, and FIG. 14D is an enlarged photograph of a portion of FIG. 14C.
FIG. 15 is a graph showing electrical characteristics of p-channel polycrystalline silicon thin film transistors fabricated by MIC, MILC, and SIC methods, respectively.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The sizes and shapes of the components shown in the drawings may be exaggerated for clarity and convenience. In addition, terms defined in consideration of the configuration and operation of the present invention may be changed according to the intention or custom of the user, the operator. Definitions of these terms should be based on the content of this specification.

1 to 10 are sectional views sequentially illustrating a method of manufacturing a polycrystalline thin film transistor according to an exemplary embodiment of the present invention.

Hereinafter, a method of crystallizing an amorphous silicon thin film according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4.

First, as shown in FIG. 1, an amorphous silicon layer 20 is deposited on the substrate 10.

The substrate 10 may use a transparent insulating substrate such as a glass substrate.

The deposition method of the amorphous silicon layer 20 may be performed using Low Pressure Chemical Vapor Deposition (LPCVD) or Plasma Enhanced Chemical Vapor Deposition (PECVD).

On the other hand, the amorphous silicon layer 20 is preferably deposited to a thickness of 400 kPa to 1000 kPa, preferably 800 kPa.

In this case, after the amorphous silicon layer 20 is formed, the amorphous silicon layer may be patterned as an activation region as needed, and then the subsequent process may be performed.

That is, in the subsequent process illustrated in FIG. 5, the polycrystalline silicon layer obtained by crystallizing the amorphous silicon layer 20 is patterned into an activation region. The amorphous silicon layer 20 is previously patterned into an activation region, and then the process is performed. It is also possible.

A photolithography process may be used as a method of patterning the amorphous silicon layer 20 as an active region, and dry etching and wet etching may be used as the etching process. For dry etching, reactive ion etching (RIE) may be used by mixing SF 6 gas and O 2 gas, and a mixed solution of HNO 3 solution and HF may be used for wet etching.

Thereafter, as shown in FIG. 2, the crystallization induction metal layer 30 is formed on the surface of the amorphous silicon layer 20. Here, the crystallization inducing metal layer 30 is a metal capable of inducing crystallization of the amorphous silicon layer 20 by reacting with the amorphous silicon layer 20, Ni, Pd, Ti, Ag, Au, Al, Sn, Sb One or two or more alloys of Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, and Pt may be used.

The crystallization induction metal layer 30 is preferably formed by vapor deposition by, for example, a sputtering method. The crystallization induction metal layer 30 may be formed by a sputtering method at room temperature to 200 ° C with a thickness of 50 kPa to 100 kPa.

3, the crystallization induction metal layer 30 is removed. That is, when the crystallization induction metal layer 30 that has been deposited on the amorphous silicon layer 20 is removed, a dot-shaped metal silicide seed 40 may be formed on the surface of the amorphous silicon layer 20. Will remain at a constant density.

The crystallization induction metal layer 30 may be removed using an acidic solution such as sulfuric acid (H 2 SO 4 ) at room temperature to 100 ℃. In this case, it is preferable to use a solution of sulfuric acid and hydrogen peroxide mixed at a ratio of 3: 2 by heating to a temperature of 70 ° C., which can remove all metals except lead (Pb) and mercury (Ag). have.

The method of removing the crystallization-inducing metal layer 30 may be used as long as it can remove the crystallization-inducing metal layer 30 by leaving a metal silicide on the amorphous silicon layer 20.

As described above, when the crystallization-inducing metal layer 30 is removed, the crystallization-inducing metal is bonded to silicon atoms in the sputtering process of the crystallization-inducing metal and silicided in the form of dots on the surface of the amorphous silicon layer 20. The silicide remains without being removed. The remaining dot-type metal silicide acts as a seed for crystallizing amorphous silicon during crystallization heat treatment, that is, a nuclei of grain growth, thereby crystallizing amorphous silicon into poly-Si. Allows crystallization to occur at lower temperatures below 600 ° C.

Here, the distribution density of the metal silicide seed 40 may be adjusted by adjusting the thickness of the crystallization inducing metal layer 30. That is, by controlling the thickness of the crystallization induction metal layer 30 can be controlled so that the metal silicide seed 40 is distributed at an appropriate density.

As shown in FIG. 4, when the metal silicide seed 40 is formed on the amorphous silicon layer 20 by removing the crystallization inducing metal layer 30 immediately after deposition, the entire amorphous silicon layer 20 is crystallized in this state. At this time, the heat treatment is preferably, for example, performed for 2 hours to 6 hours at 500 ℃ ~ 600 ℃. That is, the polysilicon layer 50 is formed by crystallizing the amorphous silicon layer 20 by the above metal silicide seed induced crystallization (SIC) method.

In this case, when the amorphous silicon layer 20 is heat-treated, as shown in FIG. 14B, crystalline growth occurs in the vertical and circumferential directions from each of the metal silicide seeds 40 in the form of dots, thereby forming the amorphous silicon layer 20. The whole is crystallized with the polycrystalline silicon layer 50.

As described above, in the crystallization method of the amorphous silicon thin film according to the present invention, the crystallization induction metal layer 30 is deposited on the surface of the amorphous silicon layer 20 by the sputtering method, and then removed by using an acidic solution to induce crystallization. When depositing the metal layer 30 by the sputtering method, the silicide bound by the plasma energy is not removed and remains in the form of dots on the surface of the amorphous silicon layer 20, and the metal silicide acts as a seed during the crystallization heat treatment to lower the temperature. The amorphous silicon thin film can be crystallized at.

In addition, when the metal silicide seed 40 is formed by sputtering the crystallization induction metal layer 30, the metal silicide seed 40 is formed in the form of dots by probably combining with silicon due to plasma energy to obtain a polycrystalline silicon thin film having improved uniformity of crystal grains. In the polycrystalline silicon layer 50, the metal silicide seed 40 having a dot shape serves as a nuclei of grain growth, and thus the grains grown are enlarged. As a result, the thin film transistor manufactured using such a polycrystalline silicon thin film is to reduce the leakage current as described later.

Furthermore, when the amorphous silicon thin film is crystallized by the SILC crystallization method of the present invention, metal contamination, which is the biggest problem of metal induced crystallization, can be minimized. As described below, a high performance polycrystalline silicon thin film having a reduced leakage current is described below. The transistor can be manufactured.

Hereinafter, a method of manufacturing a thin film transistor using a polycrystalline silicon layer obtained by the crystallization method using SIC according to the present invention will be described with reference to FIGS. 5 to 10.

First, as shown in FIG. 5, the activation region 52 is formed by patterning the crystallized polycrystalline silicon layer 50 through the photolithography process through the SIC process described above.

For patterning using a photolithography process, an etch mask corresponding to the active region 52 may be formed using, for example, photoresist PR, and the etching process may be performed using the photoresist. For the etching process, dry etching and wet etching may be used. In the dry etching method, reactive ion etching (RIE) may be performed by mixing SF 6 gas and O 2 gas. In the wet etching method, a mixed solution of HNO 3 solution and HF may be used.

Next, as shown in FIG. 6, an insulating film 60 for forming a gate insulating film is formed on the surface of the activation region 52, and then a metal film for forming a gate electrode on the surface of the insulating film 60 ( 70). Here, the insulating film 60 may be a silicon oxide film (SiO 2 ) or a silicon nitride film (Si 3 N 4 ), and the metal film 70 for forming a gate electrode may be formed of W, Pt, Ti, Al, Ni, Mo, or the like. Conductive material may be used.

After depositing the insulating film 60 and the metal film 70, as shown in FIG. 7, an etching mask is formed of a photoresist thereon, and the gate electrode forming metal film 70 and the gate insulating film are formed thereon. The insulating film 60 for etching is sequentially etched to form the gate electrode 72 and the gate insulating film 62.

Subsequently, as shown in FIG. 8, N-type or P-type dopant ions are implanted into the activation region 52 made of polycrystalline silicon crystallized by the SIC method using the etching mask as an ion implantation mask. 52a and the drain region 52b are defined.

In this case, the dopant to be injected may be, for example, P, PH 3 or As in the case of N-type, and B, B 2 H 6 or BH 3 in the case of P-type. As a result, the region where the dopant is not injected between the source region 52a and the drain region 52b becomes the channel region 52c.

When the doping of the source region 52a and the drain region 52b is completed, the substrate is heat-treated under a hydrogen atmosphere at a temperature between 400 ° C. and 600 ° C., for example, at 550 ° C. for 1 hour to 5 hours. At 52a and at the same time, the dopant implanted in the drain region 52b is activated and the dangling bond is removed to reduce the leakage current of the manufactured thin film transistor.

Finally, as shown in FIGS. 9 and 10, an interlayer insulating film 90 is formed on a substrate according to a conventional process, and a portion of the interlayer insulating film 90 is etched to etch the source region 52a and the drain region 52b. ) And the contact windows 102, 106, 104 for the gate region 100 of the gate electrode 72, and then the source electrode 94, the drain electrode 96, and the gate electrode 98 are formed using a conductive material. The thin film transistor is completed.

(Example)

As an embodiment of the present invention, a polysilicon thin film transistor using metal silicide seed induced crystallization (SIC) was fabricated, and then the characteristics of the polycrystalline silicon thin film and the thin film transistor were measured.

First, SiH 4 gas was used at 500 ° C. using Low Pressure Chemical Vapor Deposition (LPCVD) on a glass substrate for flat panel display (eg, Corning eagle XG) on which 300 nm buffer oxide was deposited. 100 nm amorphous silicon thin film was deposited.

Thereafter, the native oxide formed on the surface of the amorphous silicon was removed using an HF solution diluted to 1%, and nickel (Ni) of about 5 nm was deposited at room temperature by a DC magnetron sputter method. The deposited nickel (Ni) was immersed for 30 minutes in a solution of sulfuric acid (H 2 SO 4 ) at 70 degrees to remove immediately before the crystallization heat treatment. In this process, the silicided nickel (Ni) silicides were not removed by reacting with the amorphous silicon surface and the unsilicided nickel (Ni) was removed.

11 (a) and 11 (b) show changes in X-ray photoelectron spectroscopy (XPS) spectra of Si and Ni before and after removing Ni deposited in amorphous silicon, respectively.

In FIG. 11 (a), the Si peak shows 99.5 eV of binding energy before and after removing Ni, whereas the widely oxidized Si (Oxidized Si) peak appears to be different. The oxidized Si peak before Ni removal is lower than after Ni removal, indicating that Si exposed to the surface is chemically oxidized during the removal of Ni from sulfuric acid.

Only Ni silicide phase is present when oxidized Ni (a mixture of NiO, NiO 2 ) and deposited Ni on amorphous silicon are removed by dipping for 30 minutes in a 70 degree sulfuric acid solution as shown in FIG. 11 (b) In this case, the binding energy (Binding Energy) was 853.6 eV. It was found that the binding energy of Ni 2p was shifted. This change in bond energy reflects the charge transfer from Ni to Si at the time of Ni-Si bond formation. Thus, the presence of Ni-Si bonds as silicide seeds formed nuclei for crystallization during the heat treatment process.

XPS is an analytical method that gives information on what atoms are present and how they are bonded. As shown in the graph of FIG. 11 (b), it can be seen that the silicide phase remains after removing Ni. This is because when sulfuric acid etches Ni, Ni, which is combined with silicon to form a silicide phase, has a stronger bonding strength with silicon and is not removed.

FIG. 12 is a graph illustrating Raman spectra of an amorphous silicon (a-Si) thin film, a MIC polycrystalline silicon (poly-Si) thin film, and an SIC polycrystalline silicon (poly-Si) thin film that have been subjected to crystallization heat treatment.

An amorphous silicon (a-Si) film heat-treated without a Ni layer for analysis of a thin film by Raman spectroscopy, a metal-induced crystallized silicon (MIC) film having a Ni layer, and nickel silicide induction crystallization according to the present invention The prepared silicon (SIC) film was prepared, and Raman spectra of three samples were measured and shown in a graph of FIG. 12. The SIC polycrystalline silicon of the present invention was subjected to crystallization heat treatment at 500 ° C. for 1 hour after removing Ni from the 100 nm thick amorphous silicon surface.

As shown in the graph of FIG. 12, the results of Raman spectroscopy showed that the spectrum of the amorphous silicon (a-Si) film showed a wide structure near 480 cm −1 , which is amorphous silicon (a-Si). Indicates. The polycrystalline silicon peak appears around 520 cm -1 , and its intensity (Relative Intensity) is the highest SIC, indicating that the crystallinity is higher than that of MIC. In this case, the absence of a broad peak centered at 480 cm −1 indicates that MIC and SIC are generated, and that the amorphous silicon thin film is crystallized as a whole after heat treatment at 500 ° C. for 1 hour.

In addition, to investigate the contamination of Ni, the amount of oxygen (O), nickel (Ni), and silicon (Si) atoms remaining on the surface of the polycrystalline silicon after crystallization by two methods, MIC and SIC, is determined by Auger electron spectroscopy (AES). Analyzed. AES spectra of MIC and SIC polycrystalline silicon (poly-Si) were measured and shown in FIG. 13.

Referring to the graph of FIG. 13, the polycrystalline silicon crystallized by MIC showed a Ni peak at 770 eV, whereas the polycrystalline silicon crystallized by SIC did not show a Ni peak. It can be seen that the nickel contamination is minimized.

Relative atomic percentage of each element on the surface of MIC and SIC poly-Si [%] MIC poly-Si SIC poly-Si O 60.90 84.77 Si 4.22 5.63 Ni 16.26 1.79

The ratios of nickel, silicon, and oxygen in the polycrystalline silicon are summarized in Table 1 above.

As shown in Table 1, the nickel content of the polycrystalline silicon crystallized by MIC is 16.26%, it can be seen that the nickel content of the polycrystalline silicon crystallized by the SIC method is extremely reduced to 1.79%.

Samples were Secco etched to examine the surface of MIC and SIC poly-Si using an optical microscope and SEM. Secco etchant can selectively etch amorphous silicon and Ni silicide from crystalline Si.

14 (a) is a micrograph of Secco-etched polycrystalline silicon crystallized by the MIC method, which shows that the MIC polycrystalline silicon has a very porous structure and grains cannot be observed due to the etching of the crystallized region as a whole. In view of the above, it can be seen that most of the polycrystalline silicon is silicided to have a very high nickel content.

In the SIC of FIG. 14B, it can be seen that certain grains are formed. It can be seen that the crystallization of amorphous silicon was performed by grain growth as a nucleus during the crystallization heat treatment of a dot-type silicide seed formed by reacting silicon with silicon in the process of depositing nickel at room temperature through a sputtering method.

14 (c) is an enlarged photograph of a portion of FIG. 14 (b), and FIG. 14 (d) is an enlarged photograph of a portion of FIG. 14 (c). In the photograph of FIG. 14C, it can be seen that silicides present at the crystallization growth tip are segregated at the grain boundaries.

In order to confirm the electrical properties of the polycrystalline silicon formed through the MIC and SIC method, a thin film polycrystalline silicon transistor was fabricated. The MIC and SIC polycrystalline silicon thin films obtained above were used.

First, two thin film polycrystalline silicon was patterned by photolithography in the form of an active region, and etching was performed by using a reactive ion etching (RIE) method using SF 6 and O 2 gases.

Subsequently, 100 nm SiO 2 of the gate insulating layer and 200 nm MoW of the gate electrode were deposited by plasma enhanced chemical vapor deposition (PECVD) and sputtering, respectively.

After deposition for patterning to form the gate electrode were a photolithography step, was to the etching of the gate electrode using an etchant H 3 PO 4 + CH 3 COOH + HNO 3 + H 2 O, the gate insulating film is CHF 4, It was etched by the RIE method using Ar, SF 6 gas.

In order to form the source / drain, impurities of B 2 H 6 were injected at an intensity of RF 150 W and DC 17 keV through an ion mass doping (IMD) device, and a protective film was deposited on the entire specimen with an insulator (SiO 2 ). Afterwards, the impurities were activated by heat treatment at 550 ° C. for 1 hour in a hydrogen atmosphere, and a metal wiring process was performed by making contact windows at gates, sources, and drains for electrode contact.

All this was done in a 1000-class clean room and the Keythley 2636 system was used for electrical characterization.

The electrical characteristics of the p-channel polycrystalline silicon thin film transistors made by the MIC, MILC, and SIC methods, respectively, are shown in the graph and table 2 of FIG. 15.

Device Parameters of Three Crystallized Polycrystalline Silicon TFTs parameter MIC MILC SIC Field-effect mobility
μFE (㎠ / Vs) 29.86 ± 4.0 57.6 ± 3.5 62.08 ± 3.8 Threshold voltage
V th (V) 10.11 ± 1.04 7.52 ± 0.86 7.42 ± 0.98 Subthreshold slope
SS (V / dec) 1.56 ± 0.23 0.9 ± 0.11 0.73 ± 0.08 Minimum leakage current
I min (× 10 -10 A) 63.7 ± 3.41 2.76 ± 3.51 1.17 ± 3.55 Maximum on current
I ON (× 10 -4 A) 1.40 ± 1.12 3.10 ± 1.11 3.07 ± 0.85 Maximum on / off ratio
(× 10 5 ) 0.21 11.23 17.87

As shown in Table 2, when comparing the electrical characteristics of MIC-TFT and SIC-TFT, the field-effect mobility is 29.86 ± 4.0 (cm2 / Vs) when using the MIC method. It can be seen that it is significantly higher to 62.08 ± 3.8 (cm 2 / Vs).

In addition, the minimum leakage current is 63.7 ± 3.41 (× 10 -10 A) for the MIC method, but it is 1.17 ± 3.55 (× 10 -10 A) for the SIC method. .

Moreover, the maximum on / off ratio is 0.21 (× 10 5 ) for the MIC method, but is significantly increased to 17.87 (× 10 5 ) for the SIC method.

In addition, comparing the electrical characteristics of the MILC-TFT and SIC-TFT, it can be seen that the characteristics of the SIC-TFT is similar or better than the MILC-TFT. In particular, the minimum leakage current is 2.76 ± 3.51 (× 10 -10 A) for the MILC method, whereas it is 1.17 ± 3.55 (× 10 -10 A) for the SIC method, which is smaller than 1/2.

This improvement in leakage current is due to the reduction of Ni concentration in the polycrystalline silicon thin film. As the Ni concentration decreases, the grain size increases, which leads to an improvement in electrical properties. Grain size affects electrical properties such as on-state current.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limited to the embodiments set forth herein. Various changes and modifications may be made by those skilled in the art.

10: substrate 20: amorphous silicon layer
30: crystallization induction metal layer 40: metal silicide seed
50 polycrystalline silicon layer 52 active region
52a: source region 52b: drain region
52c: channel region 60: insulating film
62: gate insulating film 70: metal film
72: gate electrode 90: interlayer insulating film
94: source electrode 96: drain electrode
98: gate electrode 100: gate region
102,104,106: contact window

Claims (16)

Forming an amorphous silicon layer on the substrate;
Forming a crystallization inducing metal layer on the amorphous silicon layer;
Removing the crystallization inducing metal layer to form a metal silicide seed on an amorphous silicon layer; And
And heat-treating the substrate on which the metal silicide seed is formed to crystallize an amorphous silicon layer. The method of claim 1,
The crystallization induction metal layer is a crystallization method of an amorphous silicon thin film, characterized in that deposited on the surface of the amorphous silicon layer by the sputtering method. The method of claim 1,
The crystallization induction metal layer is a crystallization method of an amorphous silicon thin film, characterized in that formed in a thickness of 50 ~ 100Å. The method of claim 1,
The crystallization induction metal layer is any one or two or more alloys of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Cr, Mo, Tr, Ru, Rh, Cd, Pt Crystallization method of amorphous silicon thin film. The method of claim 1,
The removal of the crystallization-inducing metal layer is a crystallization method of an amorphous silicon thin film, characterized in that using an acidic solution containing sulfuric acid (H 2 SO 4 ). The method of claim 1,
Removing the crystallization-inducing metal layer is a crystallization method of an amorphous silicon thin film, characterized in that using a sulfuric acid or sulfuric acid mixed solution heated to room temperature ~ 100 ℃. The method of claim 1,
The metal silicide seed is a crystallization method of an amorphous silicon thin film, characterized in that formed in the form of a dot (dot) on the surface of the amorphous silicon layer. The method of claim 1,
The distribution density of the metal silicide seed is controlled by the thickness of the crystallization-inducing metal layer formed in the amorphous silicon layer crystallization method of the amorphous silicon thin film. The method of claim 1,
The heat treatment is a crystallization method of an amorphous silicon thin film, characterized in that performed for 2 hours to 6 hours at 500 ℃ ~ 600 ℃. The method of claim 1,
And forming an active region by patterning the amorphous silicon layer after forming the amorphous silicon layer. Forming an amorphous silicon layer on the substrate;
Forming a crystallization inducing metal layer on the amorphous silicon layer;
Removing the crystallization inducing metal layer to form a plurality of metal silicide seeds in an amorphous silicon layer;
Heat-treating the substrate on which the metal silicide seed is formed to crystallize an amorphous silicon layer;
Patterning the crystallized polycrystalline silicon layer into an active region;
Sequentially forming a gate insulating film and a gate electrode on the polycrystalline silicon layer; And
And forming a source region and a drain region by implanting N-type or P-type dopant ions into an active region of the polycrystalline silicon layer. 12. The method of claim 11,
And the crystallization inducing metal layer is deposited on the surface of the amorphous silicon layer by a sputtering method. 12. The method of claim 11,
The crystallization induction metal layer is a method of manufacturing a polycrystalline thin film transistor, characterized in that formed in a thickness of 50 ~ 100Å. 12. The method of claim 11,
The removal of the crystallization-inducing metal layer is a method of manufacturing a polycrystalline thin film transistor, characterized in that using an acidic solution containing sulfuric acid (H 2 SO 4 ). 12. The method of claim 11,
The metal silicide seed is a crystallization method of an amorphous silicon thin film, characterized in that formed on the surface of the amorphous silicon layer (dot). 12. The method of claim 11,
The distribution density of the metal silicide seed is controlled by the thickness of the crystallization-inducing metal layer formed in the amorphous silicon layer.
KR1020120038103A 2012-04-12 2012-04-12 Method for crystallizing amorphous silicon thin film and method for fabricating poly crystalline thin film transistor using the same KR20130115625A (en)

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Publication number Priority date Publication date Assignee Title
KR20190042988A (en) * 2017-10-17 2019-04-25 한국과학기술연구원 Thin film transistor channel and thin film transistor using the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190042988A (en) * 2017-10-17 2019-04-25 한국과학기술연구원 Thin film transistor channel and thin film transistor using the same

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