JP3925085B2 - Manufacturing method of semiconductor device, manufacturing method of light modulation element, and manufacturing method of display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a method for manufacturing a semiconductor device, a method for manufacturing a light modulation element, and a method for manufacturing a display device.
[0002]
[Prior art]
Semiconductor films such as polycrystalline silicon are widely used for thin film transistors (hereinafter referred to as TFTs in the present specification) and solar cells. In particular, polycrystalline silicon (poly-Si) TFTs can be made on a transparent and insulating substrate such as a glass substrate while being capable of high mobility, making it possible to make liquid crystal display devices (LCD) and liquid crystal projectors. It is widely used as a component of light modulation elements such as built-in drivers for driving liquid crystals, and has succeeded in creating new markets.
[0003]
As a method for producing a high-performance TFT on a glass substrate, a manufacturing method called a high-temperature process has already been put into practical use. A process using a high temperature with a maximum process temperature of about 1000 ° C. as a TFT manufacturing method is generally called a high temperature process. The characteristics of the high-temperature process are that a relatively high-quality poly-Si can be produced by solid phase growth of silicon, a high-quality gate insulating film (generally silicon dioxide) and a clean poly-Si and gate by thermal oxidation. That is, the interface of the insulating film can be formed. Due to these characteristics, a high-performance TFT having high mobility and high reliability can be stably manufactured in a high-temperature process. However, in order to use a high temperature process, it is necessary that the substrate on which the TFT is formed can withstand a high temperature heat process of 1000 ° C. or higher. The only transparent substrate that satisfies this condition is currently quartz glass. For this reason, poly-Si TFTs of recent years are all manufactured on a small and expensive quartz glass substrate, and are not suitable for enlargement due to cost problems. In addition, the solid phase growth method requires a heat treatment for a long time of ten and several hours, and there is a problem that productivity is extremely low. In addition, this method has caused a problem that the thermal deformation of the substrate becomes a big problem due to the whole substrate being heated for a long time, and it is impossible to use a substantially inexpensive large glass substrate. This also hinders cost reduction.
[0004]
On the other hand, a technique called a low-temperature process is intended to solve the above-mentioned drawbacks of a high-temperature process and to realize a poly-Si TFT with high mobility. In order to use a relatively inexpensive heat-resistant glass substrate, a poly-Si TFT manufacturing process having a maximum process temperature of approximately 600 ° C. or lower is generally called a low-temperature process. In a low temperature process, a laser crystallization technique for crystallizing a silicon film by using a pulse laser having an extremely short oscillation time is widely used. Laser crystallization is a technique that utilizes the property of crystallizing in the process of solidifying instantaneously by irradiating a silicon thin film on a substrate with high-power pulsed laser light. Recently, a technique for forming a poly-Si film having a large area by scanning an amorphous silicon film on a glass substrate while repeatedly irradiating it with an excimer laser beam has been widely used. In addition, as a gate insulating film, silicon dioxide (SiO 2) is formed by a film forming method using plasma CVD.₂) The film can be formed, and the prospects for practical use have been obtained. With these technologies, poly-Si TFTs can be created on a large glass substrate that is currently several tens of centimeters on a side.
[0005]
However, the problem in this low-temperature process is that a high-density trap level is generated inside the semiconductor layer (poly-Si) that becomes the active layer and at the interface between the semiconductor layer surface and the gate insulating film (hereinafter referred to as MOS interface). This causes a decrease in TFT mobility and an increase in threshold voltage. In addition, there is a serious problem that these mobility and threshold values vary between elements, substrates, and lots. When single crystal silicon is used as the active layer, the trap level density in the crystal is 10¹⁵(Cm^-3) Although the value is extremely low as follows, in the case of a polycrystalline silicon film, 10% is included in the film.¹⁷-10¹⁸(Cm^-3) There is a trap level at a high density. In the case of a polycrystalline silicon film, there are many structural disturbances such as crystal grain boundaries and crystal defects in the semiconductor layer, and these form a level in the semiconductor band gap, which adversely affects the trap level. It affects. Yet another problem is the MOS interface formed by a low temperature process. The interface order density at a good MOS interface formed by thermal oxidation at 1000 ° C. or higher is 2 × 10¹⁰(Cm^-2eV^-1However, when the insulating film is formed at a low temperature of 400 ° C. or lower by plasma CVD or the like, the MOS interface state density is 10¹¹-10¹²(Cm^-2eV^-1) Is a high value. Since the energy of these interface levels is also located in the band gap of the semiconductor, these also act as trap levels, which also hinders the improvement of TFT characteristics.
[0006]
In the case of a TFT, when a voltage is applied to the gate electrode, carriers determined by the MOS capacitor capacitance are induced on the semiconductor layer side. However, if there are trap levels on the semiconductor layer side, that is, on the active layer and the MOS interface, the induced carriers are trapped in these trap levels and cannot contribute to conduction. As a result, a drain current cannot be obtained unless a higher gate voltage is applied and more carriers than the trap level density are induced. This is the reason why the threshold voltage of the TFT is increased. At present, there is no effective means for positively controlling the above trapping levels, which results in low TFT mobility, high threshold voltage, and large variations in TFT characteristics. This is the maximum in the current manufacturing process. It has become a problem. At present, the threshold voltage of the low-temperature poly-Si TFT is about 3 to 4V. If the threshold voltage can be lowered to, for example, about 1 V, the driving voltage of a circuit made of TFTs can be lowered to one third or less. Since the power consumption of the circuit is proportional to the square of the drive voltage, if the drive voltage can be lowered to 1/3 or less, the power consumption can be drastically reduced to 1/10. By doing so, an ultra-low power consumption liquid crystal display suitable for a display for portable information devices, for example, can be realized. In order to achieve such an object, both the trap level density at the poly-Si and MOS interfaces are 10¹⁰(Cm^-2eV^-1) To a certain extent.
[0007]
[Problems to be solved by the invention]
In view of the above-described problems, the present invention provides a method of manufacturing a thin film transistor that reduces the trap level of a semiconductor layer and a MOS interface formed by a low-temperature process and realizes improvement in characteristics of a poly-Si TFT and a circuit.
[0008]
[Means for Solving the Problems]
  In order to solve the above-described problem, a method of manufacturing a semiconductor device according to the present invention does not heat a substrate, and irradiates a semiconductor layer on the substrate with laser light under a condition where the temperature of the substrate is 100 ° C. or less. A crystallization step of crystallizing the semiconductor layer; and after the crystallization step, the substrate is not heated, and the semiconductor layer is subjected to hydrogen plasma treatment under a condition that the temperature of the substrate is 100 ° C. A hydrogen plasma treatment step for diffusing in the semiconductor film; and after the hydrogen plasma treatment step, the substrate is not heated, and the temperature of the substrate is 100 ° C. or lower using a plasma CVD method on the semiconductor layer. After the first gate insulating film forming step for forming the first gate insulating film and the first gate insulating film forming step, the substrate is heated and subjected to heat treatment under the condition that the temperature of the substrate is 100 ° C. or higher. The half A heat treatment step for activating the hydrogen atoms diffusing in the body film and terminating dangling bonds in the semiconductor film; and after the heat treatment step, etching the first gate insulating film and the semiconductor film. An etching process for forming an island-shaped first gate insulating film and an island-shaped semiconductor film, and after the etching process, a second gate insulating film is formed on the island-shaped first gate insulating film using a plasma CVD method. A second gate insulating film forming step to be formed; and a gate electrode forming step of forming a gate electrode on the second gate insulating film after the second gate insulating film forming step.
[0009]
  Further, in the method for manufacturing a semiconductor device according to the present invention, the semiconductor layer on the substrate is irradiated with light without heating the substrate to crystallize the semiconductor layer, and after the crystallization step, Plasma processing is performed on the semiconductor layer without heating the substrate, and first atoms are diffused into the semiconductor film, and plasma CVD is performed without heating the substrate after the plasma processing step. A gate insulating film forming step for forming a gate insulating film on the semiconductor layer using a method, and after the gate insulating film forming step, heat treatment is performed without heating the substrate, and diffusion into the semiconductor film is performed. A heat treatment step of activating the first atoms and terminating dangling bonds in the semiconductor film. Thereby, the interface between the semiconductor film and the gate insulating film can be kept good. Here, “not heating the substrate” means that no positive heating is performed using a heater, a lamp, or the like, and includes a state where the substrate is naturally heated by the process.
[0011]
  In the semiconductor device manufacturing method, the plasma CVD method in the first gate insulating film forming step is preferably performed using microwave discharge plasma.
[0012]
  In the semiconductor device manufacturing method, the heat treatment is preferably performed in a hydrogen mixed gas atmosphere at 250 ° C. or higher.
[0013]
  In the semiconductor device manufacturing method, the heat treatment is preferably performed in a moisture atmosphere of 200 ° C. or higher.
[0014]
  The method for manufacturing a semiconductor device includes an etching step for etching the semiconductor film and the gate insulating film, and a gate electrode forming step for forming a gate electrode on the gate insulating film after the heat treatment step. Furthermore, it is preferable to include.
[0015]
  According to another aspect of the present invention, there is provided a method for manufacturing a light modulation element including the above-described method for manufacturing a semiconductor device.
[0016]
  A method for manufacturing a display device includes the method for manufacturing the semiconductor device.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 illustrates the structure of a poly-Si TFT for each step.
[0024]
(1. Formation of semiconductor thin film) (FIG. 1A)
In order to carry out the present invention, usually, a base protective film (102) is formed on a substrate (101) and a semiconductor thin film (103) is formed thereon, and this series of forming methods will be described.
[0025]
The substrate (101) to which the present invention can be applied is a conductive material such as metal, silicon carbide (SiC), alumina (Al₂O₃) And aluminum nitride (AlN), a transparent or non-transparent insulating material such as fused quartz or glass, a semiconductor material such as a silicon wafer, and an LSI substrate processed therewith. The semiconductor film is deposited directly on the substrate or via a base protective film, a lower electrode, or the like. A single crystal substrate such as a silicon wafer is used as it is as a semiconductor layer (103) which becomes an active layer.
[0026]
As the base protective film (102), a silicon oxide film (SiO_X: 0 <x ≦ 2) or silicon nitride film (Si₃N_x: Insulating substances such as 0 <x ≦ 4). When it is important to control impurities in a semiconductor film as in the case where a thin film semiconductor device such as a TFT is formed on a normal glass substrate, movable ions such as sodium (Na) contained in the glass substrate are transferred to the semiconductor film. It is preferable to deposit the semiconductor film after forming the base protective film so as not to be mixed therein. The same is true when various ceramic materials are used as the substrate. The base protective film prevents impurities such as a sintering aid material added to the ceramic from diffusing and mixing into the semiconductor portion. In the case where a conductive material such as a metal material is used as a substrate and the semiconductor film must be electrically insulated from the metal substrate, a base protective film is naturally indispensable to ensure insulation. Further, when a semiconductor film is formed on a semiconductor substrate or an LSI element, an interlayer insulating film between transistors or wirings is also a base protective film.
[0027]
For the base protective film, the substrate is first cleaned with an organic solvent such as pure water or alcohol, and then an atmospheric pressure chemical vapor deposition method (APCVD method), a low pressure chemical vapor deposition method (LPCVD method), or a plasma chemical vapor phase is formed on the substrate. It is formed by a CVD method such as a deposition method (PECVD method) or a sputtering method. When a silicon oxide film is used as an undercoat protective film, monosilane (SiH) is used with atmospheric pressure chemical vapor deposition with a substrate temperature of about 250 ° C. to 450 ° C.₄) Or oxygen as a raw material. In the plasma chemical vapor deposition method or the sputtering method, the substrate temperature is about room temperature to 400 ° C. The film thickness of the base protective film needs to be sufficient to prevent the impurity element from diffusing and mixing from the substrate, and its value is at least about 100 nm. Considering the variation between lots and substrates, the thickness is preferably about 200 nm or more, and if it is about 300 nm, the function as a protective film can be sufficiently achieved. In the case where the base protective film also serves as an interlayer insulating film such as a wiring connecting IC elements or wirings between them, the film thickness is usually about 400 nm to 600 nm. If the insulating film becomes too thick, cracks due to the stress of the insulating film occur. Therefore, the maximum film thickness is preferably about 2 μm. When it is necessary to consider productivity, the upper limit of the insulating film thickness is about 1 μm.
[0028]
Next, the semiconductor thin film (103) will be described. As a semiconductor film to which the present invention is applied, a silicon-germanium (Si) in addition to a group 4 simple semiconductor film such as silicon (Si) or germanium (Ge)._xGe_1-x: 0 <x <1) and silicon carbide (Si_xC_1-x: 0 <x <1) and germanium carbide (Ge_xC_1-x: Group 4 element composite semiconductor film such as 0 <x <1), a compound compound semiconductor film of a group 3 element and a group 5 element such as gallium / arsenic (GaAs) or indium / antimony (InSb), or cadmium A composite compound semiconductor film of a group 2 element and a group 6 element such as selenium (CdSe) is available. Or silicon, germanium, gallium, arsenic (Si_xGe_yGa_zAs_z: X + y + z = 1), further compound compound semiconductor films, N-type semiconductor films in which donor elements such as phosphorus (P), arsenic (As), and antimony (Sb) are added to these semiconductor films, or boron (B ), Aluminum (Al), gallium (Ga), indium (In) and the like, the present invention can be applied to a P-type semiconductor film to which an acceptor element is added. These semiconductor films are formed by a CVD method such as an APCVD method, an LPCVD method, or a PECVD method, or a PVD method such as a sputtering method or a vapor deposition method. When a silicon film is used as the semiconductor film, the LPCVD method sets the substrate temperature to about 400 ° C. to 700 ° C. and disilane (Si₂H₆) Or the like as a raw material. In the PECVD method, monosilane (SiH₄) Or the like as a raw material, and can be deposited at a substrate temperature of about 100 ° C. to 500 ° C. When using the sputtering method, the substrate temperature is about room temperature to 400 ° C. There are various states, such as amorphous, mixed crystal, microcrystalline, and polycrystalline, as the initial state (as-deposited state) of the semiconductor film deposited in this way. May be in any state. In the present specification, not only amorphous crystallization but also polycrystalline and microcrystalline recrystallization are all called crystallization. The thickness of the semiconductor film is suitably about 20 nm to 100 nm when it is used for a TFT.
[0029]
(2. Laser crystallization of semiconductor thin film) (FIG. 1B)
After a base insulating film and a semiconductor film are formed on the substrate, the semiconductor film is crystallized by laser irradiation by the laser light irradiation means 104. Usually, the surface of a silicon film deposited by a CVD method such as an LPCVD method or a PECVD method is often covered with a natural oxide film. Therefore, it is necessary to remove this natural oxide film before irradiating the laser beam. For this purpose, there are a method of wet etching by dipping in a hydrofluoric acid solution, dry etching in a plasma containing fluorine, and the like.
[0030]
Next, the substrate with the semiconductor film is set in a laser irradiation chamber. A part of the laser irradiation chamber is made of a quartz window, and after the chamber is evacuated to vacuum, laser light is irradiated from the quartz window.
[0031]
Here, laser light will be described. It is desired that the laser light is strongly absorbed on the surface of the semiconductor thin film (103) and hardly absorbed by the insulating film (102) and the substrate (101) immediately below the laser light. Therefore, excimer laser, argon ion laser, YAG laser harmonic, etc. having a wavelength in the ultraviolet region or the vicinity thereof are preferable as this laser light. Further, in order to heat the semiconductor thin film to a high temperature and simultaneously prevent damage to the substrate, it is necessary to have a pulse output with a large output and a very short time. Therefore, excimer lasers such as a xenon chloride (XeCl) laser (wavelength 308 nm) and a krypton fluoride (KrF) laser (wavelength 248 nm) are most suitable among the above laser beams. Next, the laser light irradiation method will be described with reference to FIG. The half width of the intensity of the laser pulse is an extremely short time of about 10 ns to about 500 ns. In the laser irradiation, the substrate (200) is set between room temperature (25 ° C.) and about 400 ° C., and the background vacuum is 10 °.^-4About 10 Torr^-9It is performed in a vacuum of about Torr. The single irradiation area of the laser irradiation is a square or rectangular shape with a diagonal of about 5 mm □ to about 60 mm □. A case where a beam capable of crystallizing, for example, a square area of 8 mm □ by one irradiation of laser irradiation will be described. After one laser irradiation (201) is performed at one place, the position of the substrate and the laser is slightly shifted in the horizontal direction relatively (203). Thereafter, one laser irradiation (202) is performed again. By repeating this shot and scan continuously, it is possible to cope with a large area substrate. More specifically, the irradiation region is shifted from about 1% to about 99% for each irradiation (for example, 50%: 4 mm in the previous example). After scanning in the horizontal direction (X direction) first, the scanning is then shifted by an appropriate amount (204) in the vertical direction (Y direction) and again by a predetermined amount (203) in the horizontal direction, and this scanning is repeated thereafter. The first laser irradiation is performed on the entire surface of the substrate. The first laser irradiation energy density is 50 mJ / cm.²About 600mJ / cm²Between about is preferred. After the first laser irradiation is completed, the second laser irradiation is performed on the entire surface as necessary. When performing the second laser irradiation, the energy density is preferably higher than that of the first, and 100 mJ / cm.²About 1000mJ / cm²It may be between degrees. The scanning method is the same as the first laser irradiation, and the square irradiation region is scanned by shifting an appropriate amount in the Y direction and the X direction. Furthermore, it is possible to perform the third or fourth laser irradiation with a higher energy density as required. When such a multi-stage laser irradiation method is used, it is possible to completely eliminate variations caused by the end of the laser irradiation region. The laser irradiation is performed at an energy density that does not damage the semiconductor film, not only in the multi-stage laser irradiation but also in the normal one-step irradiation. In addition to this, as shown in FIG. 3, the irradiation region shape may be a line shape (301) having a width of about 100 μm or more and a length of several tens of centimeters, and crystallization may be advanced by scanning this line-shaped laser beam. . In this case, the overlap in the beam width direction for each irradiation is about 5% to 95% of the beam width. If the beam width is 100 μm and the overlap amount for each beam is 90%, the beam advances 10 μm for each irradiation, so that the same point receives 10 laser irradiations. Usually, in order to crystallize the semiconductor film uniformly over the entire substrate, at least about 5 times of laser irradiation is desired. Therefore, the overlap amount of the beam for each irradiation is required to be about 80% or more. In order to reliably obtain a highly crystalline polycrystalline film, it is preferable to adjust the overlap amount from about 90% to about 97% so that the same point is irradiated about 10 to 30 times. By using a line beam, it is possible to crystallize a wide area by scanning in one direction, so that an advantage can be obtained that the throughput can be increased as compared with the square beam described above.
[0032]
Here, the substrate heating in the laser crystallization process will be described. As described above, the semiconductor thin film is melted and crystallized by laser irradiation, so that the temperature of the silicon film rises to 1400 ° C. or higher, and then the thermal diffusion to the substrate causes¹⁰It is rapidly cooled at a rate of about (K / s). That is, melting and crystal growth are completed at most after 100 ns after laser irradiation. As can be easily inferred from this, the formation time of the crystal grain boundary is extremely short, so that silicon atoms cannot form a good bond with each other, resulting in a large amount of dangling bonds occurring at the crystal grain boundary. . These dangling bonds form trap levels. As a result, in high-speed crystal growth such as laser crystallization, 10¹⁸(Cm^-3) The above capture levels are generated. This high trap level density is hardly reduced even when the substrate is heated to about 400 ° C. This is because the crystal grain boundary formation time does not change with substrate heating. Thus, almost no substrate heating is required for controlling the laser crystallization process. In other words, it can be said that there is no particular limitation on the substrate temperature in the course of laser crystallization.
[0033]
In order to improve the characteristics of the TFT or reduce variations, it is rather important to perform the process following the laser crystallization process continuously in a vacuum. This is because the process in vacuum is overwhelmingly advantageous for controlling the trap level. In particular, it is desired that laser crystallization, plasma treatment, and gate insulating film formation, which are important for variation control, be performed at least in a continuous process in a vacuum. When performing continuous processes, it is extremely important that the substrate temperature be constant between the processes. This is because raising or lowering the temperature of the substrate in a vacuum extremely reduces the process throughput. From this point of view, it is effective to adjust the substrate temperature when laser crystallization is performed to a process that is easily influenced by other temperatures, assuming a continuous process in vacuum. As will be described later, in particular, since the interface state density of the MOS interface formed by the gate insulating film forming process is strongly influenced by the substrate temperature, the laser crystallization is preferably matched with the temperature of the gate insulating film forming process. Specifically, 100 ° C. or lower is desirable.
[0034]
(3. Plasma treatment of semiconductor thin film)
10 in the poly-Si film immediately after laser crystallization.¹⁸(Cm^-3) There are trap levels at a high density. This is because laser crystallization is an extremely fast crystal growth, and many trap levels are localized particularly at the crystal grain boundaries. The identity of these trap levels is a dangling bond of silicon, which is normally neutral, but has the property of trapping carriers and charging. If these trap levels exist at a high density in the poly-Si film, carriers induced by the electric field effect are all trapped in the trap level when the TFT is operated, and therefore, between the source and drain electrodes. Current will not flow. As a result, it is necessary to apply a higher gate voltage, leading to an increase in threshold voltage. In order to prevent this, after the entire crystallization is completed by the laser crystallization process, the substrate is transferred to a plasma processing chamber by a vacuum robot, and hydrogen, oxygen, and nitrogen gas are introduced into the chamber through a mass flow controller, and a parallel plate RF Plasma discharge is performed on the entire surface of the sample by the electrodes. Here, the gas pressure is adjusted to be, for example, about 1 Torr. Plasma generation can also be generated by ionization using thermoelectrons by inductively coupled RF discharge, ECR discharge, DC discharge, or hot filament. Hydrogen plasma treatment is performed on the poly-Si film immediately after laser crystallization at a substrate temperature of 100 ° C. for 5 to 300 seconds. Since hydrogen has a very high diffusion rate in the silicon film, a processing time of about 160 seconds is sufficient for poly-Si having a film thickness of about 50 nm, for example. Hydrogen has a small atomic radius and can be efficiently trapped in a short time to a deep position in the poly-Si film, that is, to the interface with the underlying layer.
[0035]
Conventional trapping level passivation by hydrogen plasma is performed at a substrate temperature of 200 ° C. or higher. This is to accelerate the diffusion of hydrogen into the film and to help the hydrogen react efficiently with the dangling bond that causes the trap level. However, as described above, when a continuous process in vacuum is assumed, the process temperature is preferably 100 ° C. or lower. However, the process disclosed by the present invention can reduce dangling bonds in the poly-Si film by performing heat treatment in a later step even if plasma treatment is performed at a low temperature. That is, if plasma treatment is performed with the substrate temperature raised to 200 ° C. or higher, the dangling bonds are immediately hydrogen terminated, but are not immediately hydrogen terminated at the substrate temperature of 100 ° C. or lower. However, even with plasma treatment at a substrate temperature of about 100 ° C., a sufficient concentration of hydrogen is diffused in the poly-Si film, so that heat treatment at about 250 ° C. or higher is performed in the subsequent step to form a poly-Si film. Hydrogen atoms react with diffusion and dangling bonds, and as a result, efficient hydrogen termination of dangling bonds can be realized. As described above, in order to achieve both the objective of efficiently reducing the trap level in the poly-Si film while ensuring the throughput in the continuous process in vacuum, The most ideal process is to perform the plasma treatment at a substrate temperature of 100 ° C. or lower and then perform the heat treatment.
[0036]
Hydrogen plasma is suitable as a process for reducing the trap level. However, the trap level can also be obtained by performing a plasma treatment such as oxygen plasma, nitrogen plasma, or fluorine plasma at a substrate temperature of 100 ° C. or lower, followed by heat treatment. Can be sufficiently reduced.
[0037]
(4. Formation of gate insulating film) (FIG. 1C)
Although it is possible to achieve high quality of the poly-Si film in this way, a more important process is a step of forming a high quality MOS interface. It is necessary to bond oxygen atoms to silicon atoms existing on the poly-Si surface to reduce the interface order density. Approximately 10 on the silicon film surface¹⁵(Cm^-2Most of these are SiO₂It is important to form clean chemical bonds. In order to improve the transistor characteristics of the TFT, the interface order density is 10¹⁰(Cm^-2) It is necessary to suppress to a degree. That is, only about one defect is allowed for 100,000 silicon bonds, and the remaining bonds must be in order with oxygen atoms. In conventional plasma CVD processes, this interfacial order density is at most 10¹²(Cm^-2eV^-1) Could only be controlled to a certain extent. The technique disclosed in the present invention is characterized in that the step of forming a gate insulating film over a semiconductor layer is performed at a substrate temperature of 100 ° C. or lower. At the same time, since the substrate temperature is absolutely important in forming the MOS interface, it is necessary to unify the substrate temperature of the continuous process in vacuum, that is, the laser crystallization and plasma processing, before that to the substrate temperature of the gate insulating film formation process. It is a feature.
[0038]
Plasma CVD uses SiH by active oxygen radicals in the plasma.₄Gas is decomposed and SiO in the gas phase₂Is formed and deposited on the substrate. SiO deposited in such a reactive atmosphere₂Can form a chemical bond with silicon on the semiconductor surface to form a good interface. However, due to the active species of oxygen present in the film formation atmosphere, SiO₂Simultaneously with the deposition of the semiconductor, the oxidation of the semiconductor surface proceeds. Oxidation is a phenomenon below the atomic layer level. When silicon is oxidized, the volume increases by a factor of 1.5. Therefore, oxidized Si-SiO₂Bonding is accompanied by local stress generation. This is the main cause of the interface order. Therefore, SiO₂Better Si-SiO due to the deposition of₂Si-SiO formed by oxidation relative to the rate at which bonds are formed₂As the coupling ratio increases, a MOS interface having a high interface order is formed as a result. Quantitatively speaking, there are approximately 10 silicon bonds present at the interface.¹⁵(Cm^-2) Is mostly SiO₂A good bond is formed by the deposition of. But 10 of these¹⁰(Cm^-2) When the above Si-O bond is formed by oxidation of silicon, this becomes an interface state. In other words, we are discussing 10⁵One-hundred probability, that is, an interface state of a level that cannot be ignored when oxidation occurs even with one Si-O bond per 100,000. Such an interface formation mechanism naturally occurs at the initial stage of film formation. That is, SiO on the semiconductor₂At the same time as the deposition starts, the oxidation process occurs. The present invention discloses this interface formation mechanism and also discloses that the activation energy of the interface order density formed by the oxidation described above is extremely large. In other words, the interface state density can be controlled by the substrate temperature. FIG. 4 shows the substrate temperature and the interface order density during the formation of the insulating film: Dit (cm^-2eV^-1) Shows the experimental result of the thermal annealing time dependence in a water atmosphere. As can be seen from this result, a considerable amount of interfacial order can be reduced by thermal annealing in a water atmosphere, but this treatment cannot repair the bond once oxidized. However, the probability of oxidation occurring on the silicon surface can be dramatically reduced by lowering the substrate temperature during film formation. This indicates that the oxidation occurring at the interface strongly depends on the substrate temperature, that is, the higher the substrate temperature, the easier the oxidation occurs. As can be seen from the graph, the interface order density is 1 × 10 5 by setting the substrate temperature to 100 ° C. or lower.¹¹(Cm^-2eV^-1). Further, if the substrate temperature is set to about 100 ° C., it is possible to reduce the occurrence of OH bonds, which are reaction byproducts of plasma CVD, in the insulating film, so that the shift of flat band voltage and the reliability of the insulating film are improved. Since it can be secured, practically favorable conditions are given. Also in the above-described plasma treatment of the poly-Si film, diffusion of hydrogen atoms is promoted when the substrate temperature is as high as possible, which is advantageous in increasing the process throughput. For this reason, it is very effective to perform laser crystallization, plasma treatment, and gate insulating film formation in a continuous process in a vacuum under the condition that the substrate temperature is unified at 100 ° C. Alternatively, the film may be formed under conditions where the substrate is not heated. This is very advantageous in terms of manufacturing cost because the structure of the apparatus is simple, and it is not necessary to adjust the substrate temperature, so that extremely high throughput can be secured even in a continuous process in vacuum. In addition, by not heating the substrate, 8 × 10¹⁰(Cm^-2eV^-1It is possible to form an excellent MOS interface that provides a good interface order density. In film formation by plasma CVD, heat transfer from the plasma to the substrate occurs and the substrate temperature naturally rises. Therefore, it is also effective to positively control the substrate to a low temperature. That is, a better interface state density can be obtained by cooling the substrate temperature to about room temperature or below room temperature. As seen in FIG. 4, 3 × 10 at room temperature.¹⁰(Cm^-2eV^-1) Interface state density of 1 × 10 by further cooling the substrate to −50 ° C.¹⁰(Cm^-2eV^-1) Interface state density can be obtained. These interface state values are approximately the same as the interface state density obtained when an insulating film is formed of a thermal oxide film. That is, by reducing the substrate temperature when forming the insulating film, a very excellent MOS interface can be formed even at a low temperature. By using such an ultra-high quality MOS interface, the threshold voltage of the thin film transistor can be lowered to about 1V. As a result, an ultra-low power consumption circuit can be realized.
[0039]
The interface control technique as described above is particularly important when an insulating film is formed by plasma. This is because a large amount of oxygen active species is generated under reduced pressure. In other words, controlling the oxidation process occurring at a very small probability on the semiconductor surface by these oxygen active species is essential in forming the MOS interface using plasma. Furthermore, the effect of the technique disclosed in the present invention is remarkable in plasma CVD using microwave discharge. This is because microwave discharge plasma generally has an advantage of high plasma density, but 10^-3This is because it is generated under a relatively low pressure of (Torr), so that the mean free path of electrons in plasma is long, and higher-order decomposition is promoted. That is, atomic oxygen and oxygen radicals are the main components of reaction rather than oxygen molecular radicals, and these are extremely active with respect to interface oxidation. Therefore, in forming an insulating film using microwave discharge plasma, the interface state density can be dramatically reduced by forming the film at a lower substrate temperature.
[0040]
As a specific process, the poly-Si film formed by laser crystallization is continuously subjected to a hydrogen plasma treatment in a vacuum, and then transferred to an insulating film forming chamber without breaking the vacuum. The temperature of the substrate is adjusted to 100 ° C. or lower in a vacuum chamber, and the background vacuum is 10^-6(Torr) Evacuate until it reaches the stage. In this state, oxygen gas and silane gas (SiH) are placed in the vacuum chamber.₄). In order to stabilize discharge, a method of diluting with He gas is also effective. In general, the oxygen gas flow rate is at least five times the silane gas flow rate. In this state, plasma discharge is performed and SiO₂A film (105) is formed. There are parallel plate type RF discharge, ICP discharge, ECR discharge, and the like as discharge forms, and RF power supply, VHF, UHF power supply, and microwave source can be used as the power supply. The above is the gate insulating film formation step.
[0041]
As described repeatedly, a continuous process in vacuum is important for improving TFT characteristics and reducing variations. However, in order to increase the throughput of the process, it is required to unify the substrate temperature in the continuous process. As described in the foregoing description, in order to control the interface state density in the gate insulating film forming step, it is absolutely required to set the substrate temperature to 100 ° C. or lower. Therefore, a series of vacuum continuous processes of laser crystallization, plasma treatment, and gate insulating film formation are performed at a unified temperature of 100 ° C. or less. The temperature at this time is set to 100 ° C., no heating, or below room temperature depending on the temperature of the gate insulating film formation step.
[0042]
(5. Annealing process)
After the insulating film formation step, the substrate is taken out of the vacuum apparatus and heat-treated in a gas atmosphere containing hydrogen gas at a substrate temperature of 250 ° C. or higher. As described above, this is because the trap level in the poly-Si film is not reduced when low-temperature plasma treatment at 100 ° C. or less is performed after laser crystallization. However, in the present invention, hydrogen atoms having a sufficiently high density compared to the density of dangling bonds are already introduced into the poly-Si film exposed to hydrogen plasma, and these hydrogen atoms are activated and diffused by heat treatment. Further, it is disclosed that the termination of the dangling bond is possible by promoting the reaction with the dangling bond. In particular, in the case of hydrogen, heat treatment at 400 ° C., which is slightly lower than the desorption temperature of 420 ° C., is effective for activation in the poly-Si film. Alternatively, it is also effective to perform heat treatment at a temperature of 200 ° C. or higher in an atmosphere containing moisture. In addition to being able to reduce the trap level in the poly-Si film by heat treatment in a moisture atmosphere, the insulating film (105) formed at a low substrate temperature in the above step is a reaction byproduct, Si-OH. The purpose is to improve this because it contains many bonds and has poor bulk insulating film characteristics. In particular, defects in the insulating film existing in the vicinity of the MOS interface to the extent that carriers can be exchanged with the semiconductor surface also affect the MOS interface state. FIG. 5 shows CV characteristics immediately after the insulating film is formed and after the annealing. If many OH bonds exist in the vicinity of the interface of the insulating film, this adversely affects the interface characteristics. In addition, the breakdown voltage of the bulk insulating film is reduced. However, this Si—OH bond can be dramatically reduced by performing a heat treatment in a steam atmosphere at 100 ° C. or higher. It is clear from FIG. 5 that this effect is enormous. As a result, it is possible to dramatically reduce the interface order and to ensure the withstand voltage and reliability. In particular, a processing temperature of about 300 ° C. is effective for realizing improvement of the insulating film in a short time. As described above, the heat treatment in the moisture atmosphere is extremely effective for reducing the trap level in the poly-Si film and at the MOS interface. However, in order to realize this effect at a lower temperature and in a shorter time, the atmospheric pressure or higher is used. It is effective to perform the heat treatment in a pressurized moisture atmosphere of 100 ° C. or higher. This is because the diffusion of hydrogen atoms and oxygen atoms into the insulating film and the poly-Si film can be accelerated and the reaction rate can be increased. Specifically, heat treatment may be performed in a saturated moisture atmosphere at 190 ° C. under a pressure of about 40 atmospheres.
[0043]
As described above, the trap levels in the poly-Si film, MOS interface, and further in the insulating film are dramatically improved by performing heat treatment following the previous laser crystallization, plasma processing, and gate insulating film formation. It can be reduced. In this embodiment, the case where the heat treatment is performed immediately after the continuous process in vacuum is described. However, even if this heat treatment is performed in a later process, the same effect can be obtained.
[0044]
(6. Element isolation step) (FIG. 1D)
A very high quality MOS structure was formed by laser crystallization, plasma treatment, continuous process in vacuum of MOS interface formation and heat treatment. Next, an element isolation step is performed to electrically insulate the TFT elements from each other. Here, as shown in FIG. 1, the insulating film and the poly-Si film are continuously etched. After a pattern is formed on the insulating film (105) by photolithography, SiO or SiO2 is formed by wet or dry etching.₂Etch. Subsequently, the poly-Si film is etched by dry etching. Here, SiO₂Since the two layers of the poly-Si film and the poly-Si film are etched, care must be taken so that the edge shape after the etching does not become wrinkled.
[0045]
(7. Formation of second stage gate insulating film) (FIG. 1E)
Island-like SiO₂After the poly-Si film is formed, a gate insulating film (106) is further formed on the entire surface of the substrate. Examples of the method for forming the gate insulating film include an ECR plasma CVD method and a parallel plate RF discharge plasma CVD method. Alternatively, the insulating film may be formed by again depositing SiO in oxygen radicals. However, if the second-stage insulating film does not have a good step coverage, it may cause an electrical short circuit at the step portion or a decrease in breakdown voltage. For this reason, plasma CVD using TEOS and oxygen having excellent step coverage as raw material gas is effective. In addition, since the first stage insulating film is formed at a low temperature, the withstand voltage tends to be low. However, by forming the insulating film at a substrate temperature of 100 ° C. or higher as the second stage, the withstand voltage of the entire insulating film can be improved. FIG. 6 shows a case where the breakdown voltage of the insulating film is examined only by forming the first stage insulating film (substrate temperature 100 ° C.) (single layer), and the second stage insulating film forming (substrate temperature 300 ° C., TEOS + O₂This is a result of investigating the breakdown voltage of the double-layer insulating film (double layer). As is clear from this, it is possible to improve the breakdown voltage of the insulating film to about 7 (MV / cm), which is practically sufficient, by the two-stage insulating film forming method disclosed in the present invention. Thus, by using different insulating film formation methods for MOS interface formation and bulk insulating film formation, it is possible to realize both excellent MOS interface characteristics and bulk insulating film characteristics that could not be realized by conventional low-temperature processes. It can be done.
[0046]
(8. Subsequent steps) (FIGS. 1F and 1G)
Subsequently, a thin film to be the gate electrode (107) is deposited by the PVD method or the CVD method. This material has a low electric resistance and is desired to be stable to a heat process of about 350 ° C., and a high melting point metal such as tantalum, tungsten, or chromium is suitable. Further, when the source and drain are formed by ion doping, the thickness of the gate electrode needs to be about 700 nm in order to prevent hydrogen channeling. Among the refractory metals, tantalum is most suitable when it becomes a material that does not cause cracks due to film stress even if it has a film thickness of 700 nm. After depositing a thin film to be a gate electrode, patterning is performed, and subsequently impurity ion implantation is performed on the semiconductor film to form source / drain regions (108, 109). At this time, since the gate electrode is a mask for ion implantation, the channel has a self-aligned structure formed only under the gate electrode. Impurity ion implantation uses an ion doping method in which hydride and hydrogen of an implanted impurity element are implanted using a mass non-separable ion implanter, and ion implantation in which only a desired impurity element is implanted using a mass separated ion implanter. Two types of law can be applied. The source gas for the ion doping method is phosphine (PH) having a concentration of about 0.1% to about 10% diluted in hydrogen.₃) And diborane (B₂H₆) Of the implanted impurity element such as In the ion implantation method, only a desired impurity element is implanted, and then hydrogen ions (protons and hydrogen molecular ions) are implanted. As described above, in order to keep the MOS interface and the gate insulating film stable, it is preferable that the substrate temperature at the time of ion implantation is 350 ° C. or lower, regardless of the ion doping method or the ion implantation method. On the other hand, in order to always stably activate the implanted impurities at a low temperature of 350 ° C. or lower (this is referred to as low-temperature activation in the present application), the substrate temperature at the time of ion implantation is desirably 200 ° C. or higher. In order to reliably activate impurity ions implanted at a low concentration at a low temperature, such as channel doping to adjust the threshold voltage of the transistor or creation of an LDD structure, it is necessary to The substrate temperature must be 250 ° C. or higher. When ion implantation is performed in such a state where the substrate temperature is high, recrystallization occurs at the same time as crystal breakage accompanying ion implantation of the semiconductor film, and as a result, it is possible to prevent the ion implantation portion from becoming amorphous. It is. That is, the ion-implanted region remains as crystalline after the implantation, and the implanted ions can be activated even if the subsequent activation temperature is as low as about 350 ° C. or less. When a CMOS TFT is formed, one of NMOS and PMOS is alternately covered with a mask using an appropriate mask material such as polyimide resin, and each ion implantation is performed by the method described above.
[0047]
Further, there is laser activation that irradiates an excimer laser or the like as an efficient method for activating impurities. This is a method of activating impurities by melting and solidifying doped poly-Si in the source and drain portions by laser irradiation through an insulating film.
[0048]
Next, contact holes are formed on the source / drain, and source / drain extraction electrodes (110, 111) and wirings are formed by a PVD method, a CVD method, or the like to complete the thin film transistor.
[0049]
【Example】
An embodiment of the present invention will be described with reference to FIG. The substrate and the base protective film used in the present invention conform to the above description, but here, as an example of the substrate, a 300 mm × 300 mm square general-purpose non-alkali glass (101) is used. First, a base protective film (102) which is an insulating material is formed on the substrate 101. Here, a silicon oxide film having a thickness of about 200 nm is deposited by ECR-PECVD at a substrate temperature of 150 ° C. Next, a semiconductor film (103) such as an intrinsic silicon film to be an active layer of the thin film transistor later is deposited. The thickness of the semiconductor film is about 50 nm. In this example, using a high vacuum type LPCVD apparatus, disilane (Si₂H₆) At 200 SCCM, and an amorphous silicon film 103 is deposited at a deposition temperature of 425 ° C. First, in a state where the reaction chamber of the high vacuum LPCVD apparatus is set to 250 ° C., a plurality of (for example, 17) substrates are arranged inside the reaction chamber with the front side facing downward. After this, the operation of the turbo molecular pump is started. After the turbomolecular pump reaches steady rotation, the temperature in the reaction chamber is increased from 250 ° C. to a deposition temperature of 425 ° C. over about 1 hour. During the first 10 minutes after the start of temperature increase, no gas is introduced into the reaction chamber and the temperature is increased in vacuum, and then nitrogen gas having a purity of 99.9999% or more is continuously supplied at 300 SCCM. The equilibrium pressure in the reaction chamber at this time is 3.0 × 10^-3It is Torr. After reaching the deposition temperature, the source gas disilane (Si₂H₆) At 200 SCCM and 1000 SCCM of dilution helium (He) having a purity of 99.9999% or more. The pressure in the reaction chamber immediately after the start of deposition is about 0.85 Torr. As the deposition proceeds, the pressure in the reaction chamber gradually increases, and the pressure immediately before the end of the deposition is approximately 1.25 Torr. The silicon film (103) thus deposited has a film thickness variation within ± 5% within a 286 mm square area excluding the peripheral part of the substrate of about 7 mm.
[0050]
Next, laser crystallization is performed. Prior to this, the amorphous silicon film is immersed in a hydrofluoric acid solution, and the natural oxide film on the semiconductor film (103) is etched. In general, the surface on which the silicon film is exposed is very unstable, and easily reacts with the atmospheric substance holding the silicon thin film. Therefore, it is necessary to stabilize not only the natural oxide film but also the exposed silicon film surface in the pretreatment with laser irradiation. For this purpose, treatment with a hydrofluoric acid solution is desirable. The mixing ratio of hydrofluoric acid with pure water is 1:30. After being immersed in the hydrofluoric acid solution for about 20 to 30 seconds, pure water washing is immediately performed for 10 to 20 minutes. After this, pure water is removed with a spinner. As a result, the surface of the silicon film becomes a stabilized surface terminated with hydrogen atoms.
[0051]
Next, laser light is irradiated. In this example, xenon chloride (XeCl) excimer laser (wavelength: 308 nm) is irradiated. The intensity half width (half width with respect to time) of the laser pulse is 25 ns. After setting the substrate in the laser crystallization chamber, evacuation is performed. After evacuation, the substrate temperature is raised to 250 ° C. The laser irradiation area is a square of 10 mm square, and the energy density on the irradiated surface is 160 mJ / cm.²It is. Irradiation is repeated while overlapping the laser light by 90% (that is, by 1 mm for each irradiation) (see FIG. 2). In this way, the amorphous silicon of the entire substrate having a side of 300 mm is crystallized. A second laser irradiation is performed using the same irradiation method. The second energy density is 180 mJ / cm²It is. Repeat this for the third and fourth times and about 20 mJ / cm.²While gradually increasing the irradiation energy density, the final energy density is 440 mJ / cm.²The laser irradiation is terminated. 450 mJ / cm here²When high energy exceeding the irradiation laser energy density was irradiated, the p-Si grains were microcrystallized, so that further energy irradiation was avoided. In laser crystallization, the substrate was not heated positively, but was processed at a substrate temperature of about room temperature.
[0052]
Next, the substrate is transferred to a plasma processing chamber while maintaining a vacuum, and hydrogen gas is introduced into the chamber. In this example, 99.999% hydrogen gas was introduced from the mass flow controller, and the pressure in the chamber was adjusted to 1 (torr). In this state, discharge was performed by applying RF of 13.56 MHz to the parallel plate electrodes, and the trap level termination in the laser-crystallized poly-Si film by hydrogen was performed. Since the substrate was not heated, the substrate temperature was about room temperature and the input RF power was 3 W / cm.²It was. With this level of RF power, the substrate temperature rise due to heat inflow from the plasma is almost negligible. Since hydrogen can diffuse into the film in a sufficiently short time, it is efficiently diffused to a deep position of the poly-Si film and to the vicinity of the interface with the underlayer in a treatment of 160 seconds.
[0053]
Next, the substrate (100) is transferred to the insulating film forming chamber while maintaining the vacuum. After substrate transfer is completed, the inside of the chamber is 10^-6(Torr) Exhaust to a degree of vacuum. The substrate is not actively heated here, and the substrate temperature is about room temperature. During this time, silane gas and oxygen gas were introduced into the chamber at a flow ratio of 1: 6, and the chamber pressure was 2 × 10.^-3Adjust to (Torr). When the gas pressure in the chamber is stabilized, ECR discharge is started and film formation of the insulating film is started. The input microwave power was 1 kW, and the microwave was introduced from the introduction window parallel to the magnetic field lines. There is an ECR point at a position 14 cm from the introduction window. The film formation was performed at a film formation rate of 100 (nm / min.). As a result, a first-layer gate insulating film (105) was formed to a thickness of 30 nm.
[0054]
Next, the substrate was taken out of the vacuum chamber, set in a saturated steam atmosphere at 330 ° C., and heat-treated for 90 minutes. As a result, the hydrogen introduced into the poly-Si film by the previous hydrogen plasma treatment efficiently terminates the trap levels in the poly-Si film, and a good MOS interface can be simultaneously formed. Next, continuous etching of the poly-Si film and the first layer insulating film was performed. Subsequently, in the present example, the second layer insulating film (106) was deposited to a thickness of 70 nm at a substrate temperature of 350 ° C. by a parallel plate type rf discharge PECVD method. As the source gas, TEOS (Si- (O-CH₂-CH₃)₄) And oxygen (O₂) Was used. Subsequently, a thin film to be the gate electrode (107) is deposited by the PVD method or the CVD method. Usually, since the gate electrode and the gate wiring are made of the same material and in the same process, it is desirable that this material has a low electric resistance and is stable to a heat process of about 350 ° C. In this example, a tantalum thin film having a thickness of 600 nm is formed by sputtering. The substrate temperature when forming the tantalum thin film is 180 ° C., and an argon gas containing 6.7% nitrogen gas is used as the sputtering gas. The tantalum thin film thus formed has an α structure in crystal structure and a specific resistance of approximately 40 μΩcm. After depositing a thin film to be a gate electrode, patterning is performed, and subsequently impurity ion implantation is performed on the semiconductor film to form source / drain regions (108, 109) and a channel region. At this time, since the gate electrode is a mask for ion implantation, the channel has a self-aligned structure formed only under the gate electrode. The source gas for the ion doping method is phosphine (PH) having a concentration of about 0.1% to about 10% diluted in hydrogen.₃) And diborane (B₂H₆) Of the implanted impurity element such as In this example, aiming at NMOS formation, an ion doping apparatus is used to dilute 5% phosphine (PH₃) At an acceleration voltage of 100 keV. PH₃ ⁺And H₂ ⁺The total ion implantation amount including ions is 1 × 10¹⁶cm^-2It is.
[0055]
Next, contact holes are formed on the source / drain, and source / drain extraction electrodes (110, 111) and wirings are formed by a PVD method, a CVD method, or the like to complete the thin film transistor.
[0056]
In the prior art, an effective process for forming a high-quality poly-Si film and a MOS interface at a low temperature and with a high throughput has not been clarified. However, as described above, extremely high quality poly-Si and MOS interface can be formed by using the thin film transistor manufacturing method of the present invention. As a result, a thin film transistor with high mobility, low threshold voltage, and extremely small variation can be manufactured, and an ultra-low power consumption circuit can be realized.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an embodiment of a method of manufacturing a thin film transistor according to the present invention along the process.
FIG. 2 is a diagram schematically showing a laser beam irradiation method during laser crystallization.
FIG. 3 is a diagram schematically showing a laser beam irradiation method during laser crystallization.
FIG. 4 is a diagram showing the substrate temperature dependence of the interface order density at the MOS interface.
FIG. 5 is a diagram showing a high-frequency CV characteristic of a MOS structure manufactured by a MOS interface forming process.
FIG. 6 is a graph showing the withstand voltage characteristics of a MOS structure formed by a two-step insulating film forming process of the present invention and a MOS structure formed by a single layer.
[Explanation of symbols]
101. . . substrate
102. . . Base insulation film
103. . . Semiconductor film
104. . . Laser light irradiation means
105. . . First layer gate insulating film
106. . . Second layer gate insulating film
107. . . Gate electrode
108. . . Source
109. . . drain
110. . . Source electrode
111. . . Drain electrode
201. . . Laser irradiation area
203. . . Move in x direction
204. . . y-direction movement
301. . . Line laser beam

Claims (7)

Without heating the substrate, the semiconductor layer on the substrate is irradiated with laser light under the condition that the temperature of the substrate is 100 ° C. or less, and the semiconductor layer is crystallized. After the crystallization step, A hydrogen plasma treatment step in which the semiconductor layer is subjected to hydrogen plasma treatment without heating the substrate and the temperature of the substrate is 100 ° C. or less, and hydrogen atoms are diffused into the semiconductor film;
After the hydrogen plasma treatment step, a first gate insulation film is formed on the semiconductor layer using a plasma CVD method without heating the substrate and under a condition that the substrate temperature is 100 ° C. or less. A film forming step;
After the first gate insulating film formation step, the substrate is heated, heat treatment is performed under a condition where the temperature of the substrate is 100 ° C. or more, and the hydrogen atoms diffused in the semiconductor film are activated, A heat treatment step for terminating dangling bonds in the semiconductor film;
An etching step of etching the first gate insulating film and the semiconductor film to form an island-shaped first gate insulating film and an island-shaped semiconductor film after the heat treatment step;
A second gate insulating film forming step of forming a second gate insulating film on the island-shaped first gate insulating film using the plasma CVD method after the etching step;
And a gate electrode forming step of forming a gate electrode on the second gate insulating film after the second gate insulating film forming step. In the manufacturing method of the semiconductor device according to claim 1,
A method for manufacturing a semiconductor device, wherein the crystallization step and the plasma treatment step are performed by continuous treatment in a vacuum. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method of manufacturing a semiconductor device, wherein the plasma CVD method in the first gate insulating film forming step is performed using microwave discharge plasma. In the manufacturing method of the semiconductor device in any one of Claims 1 thru | or 3,
A method of manufacturing a semiconductor device, wherein the heat treatment is performed in a hydrogen mixed gas atmosphere at 250 ° C. or higher. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein the heat treatment is performed in a moisture atmosphere of 200 ° C. or higher.   A method for manufacturing a light modulation element, comprising the method for manufacturing a semiconductor device according to claim 1.   A method for manufacturing a display device, comprising the method for manufacturing a semiconductor device according to claim 1.

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