JP2002289862A - Method for manufacturing semiconductor thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformly manufacture a high-performance thin-film transistor in the surface of a substrate. SOLUTION: In a method of manufacturing the thin-film transistor, steps from a base protective layer depositing step to a gate wiring layer depositing step are conducted continuously in a state works are isolated from the external atmosphere of equipment. Thereafter, gate wiring, a gate insulating film, and a semiconductor layer are patterned.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor thin film transistor.

[0002]

2. Description of the Related Art A conventional method for manufacturing a semiconductor thin film transistor will be described with reference to FIG. FIG. 2 is a cross-sectional view in the order of steps showing up to the step of forming a gate insulating film in the conventional method of manufacturing a semiconductor thin film transistor.

First, an insulating film 2-2 is formed as a base protective layer on a substrate 2-1 (FIG. 2A). Next, the semiconductor layer 2-3 is deposited on the substrate by a CVD apparatus, a sputtering apparatus, or the like. In the case where a crystal such as polysilicon is used as the semiconductor layer, the substrate is transferred to a crystallization apparatus, and the semiconductor layer is crystallized (FIG. 2B). Next, a photoresist 2-4 is applied on the semiconductor layer 2-3, and the photoresist is patterned by exposure and development (FIG. 2C). Next, the semiconductor layer is etched using the photoresist as a mask to perform element isolation of the semiconductor layer (FIG. 2D). Next, the photoresist is removed by ashing or washing (FIG. 2).
(E)). Next, an insulator layer 2-5 is formed on the entire surface of the substrate as a gate insulating film (FIG. 2F). Next, a gate wiring layer is formed and patterned to form a gate wiring (FIG. 2G). After this, an impurity implantation step,
A semiconductor thin film transistor is completed through an impurity activation step, an interlayer insulating film forming step, a contact hole forming step, a metal wiring forming step, etc. (not shown after the impurity implantation step).

[0004]

In the above prior art, the substrate is exposed to the atmosphere outside the device after the formation of the base protective layer and before the formation of the semiconductor layer and before the crystallization of the semiconductor layer after the formation of the semiconductor layer. May be contaminated, and seriously affect the performance of the thin film transistor. In the element isolation process, a photoresist is applied directly to the surface of the semiconductor layer in the air, so that components of the photoresist that cannot be completely removed by ashing or cleaning, or contaminants from the atmosphere, cause the gate insulating film to be removed. An interface with a semiconductor (hereinafter, referred to as a MOS interface) is contaminated, which may seriously affect the performance of the thin film transistor. Also,
Since there is already a step on the substrate at the time of patterning the gate wiring layer, unevenness in the thickness of the photoresist and unevenness in the wiring width due to irregular reflection of light occur in the photolithography process.

An object of the present invention is to prevent deterioration of characteristics due to contamination in a semiconductor layer, a MOS interface, and a gate insulating film, and to prevent characteristics deterioration due to uneven width of a gate wiring over the entire surface of a substrate. An object of the present invention is to provide a method of manufacturing a semiconductor thin film transistor device having high uniformity without uniformity over the entire surface of a substrate.

[0006]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor thin film transistor, comprising: forming a first insulating film as a base protective layer on a substrate; and forming a semiconductor layer on the base protective layer. Forming, crystallizing the semiconductor layer in a non-oxidizing atmosphere, forming a second insulating film as a gate insulating layer on the semiconductor layer, and forming on the gate insulating layer Depositing a gate wiring layer;
Patterning the gate wiring layer to form a gate wiring; and patterning a gate insulating layer and a semiconductor layer to separate elements, and these steps are performed in this order. This is a method for manufacturing a semiconductor thin film transistor.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor thin film transistor, the process is continuously performed from the step of forming the base protective layer to the step of depositing the gate wiring layer without exposing the substrate to an atmosphere outside the device. A method of manufacturing a semiconductor thin film transistor according to claim 1.

The method of manufacturing a semiconductor thin film transistor according to claim 3 is characterized in that the crystallization of the semiconductor layer is performed by irradiating a laser. .

In the method of manufacturing a semiconductor thin film transistor according to claim 4, the crystallization of the semiconductor layer is performed by selectively crystallizing only a portion which will later become an active layer of the transistor. 3. A method for manufacturing a semiconductor thin film transistor according to item 2.

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor thin film transistor, the crystallization of the semiconductor layer is performed by irradiating a laser.

A method of manufacturing an electro-optical device according to the present invention includes a step of using the method of manufacturing a thin film transistor according to any one of claims 1 to 5.

According to the present invention, there is provided an electro-optical device.
And a thin film transistor manufactured by the method for manufacturing a thin film transistor according to any one of the above.

Note that the electro-optical device is, for example, a liquid crystal display device, an organic electroluminescence element, and an electrophoretic display device.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings and FIG. FIG. 1 is a cross-sectional view of a method of manufacturing a semiconductor thin film transistor according to the present invention in the order of steps, up to an element isolation step.

(1. Formation of Semiconductor Thin Film) In order to carry out the present invention, usually, a base protective layer 2 is formed on a substrate 1 (FIG. 1A), and a semiconductor thin film 3 is formed thereon (FIG. 1A). FIG.
(B)) This series of forming methods will be described.

The substrate 1 to which the present invention can be applied includes conductive materials such as metals, ceramic materials such as silicon carbide (SiC), alumina (Al ₂ O ₃ ) and aluminum nitride (AlN), fused quartz and glass. And the like, a transparent or non-transparent insulating material, a semiconductor material such as a silicon wafer, and an LSI substrate obtained by processing the same. The semiconductor film is deposited directly on the substrate or via a lower protective layer, a lower electrode, and the like.

A silicon oxide film (SiO 2)
_X : 0 <x ≦ 2 or a silicon nitride film (Si ₃ N _x : 0 <x ≦
4) and the like. When a semiconductor thin film transistor is formed on a normal glass substrate, it is important to control impurities in the semiconductor film, so that mobile ions such as sodium (Na) contained in the glass substrate should not be mixed into the semiconductor film. It is preferable to deposit a semiconductor film after forming the base protective layer. The same situation applies when various ceramic materials are used as the substrate. The undercoat protective layer prevents impurities such as a sintering aid material added to the ceramic from diffusing and mixing into the semiconductor portion. In the case where a conductive material such as a metal material is used as the substrate and the semiconductor film must be electrically insulated from the metal substrate, the underlying protective layer is indispensable to ensure insulation. Further, when a semiconductor film is formed on a semiconductor substrate or an LSI element, an interlayer insulating film between transistors and wirings is also a base protective layer.

The undercoat protective layer is formed by first cleaning the substrate with an organic solvent such as pure water or alcohol, and then depositing the substrate on the substrate by atmospheric pressure chemical vapor deposition (APCVD) or low pressure chemical vapor deposition (LPCV).
D method), a CVD method such as a plasma enhanced chemical vapor deposition method (PECVD method), or a sputtering method. In the case where a silicon oxide film is used as the base protective layer, the atmospheric pressure chemical vapor deposition method can deposit monosilane (SiH ₄ ) or oxygen as a raw material at a substrate temperature of about 250 ° C. to about 450 ° C. In the plasma chemical vapor deposition method and the sputtering method, the substrate temperature is from room temperature to about 400 ° C. The thickness of the undercoat protective layer must be sufficient to prevent diffusion and mixing of the impurity element from the substrate, and the value is at least about 100 nm or more. Considering the variation between lots and substrates, the thickness is preferably about 200 nm or more, and if it is about 300 nm, it can sufficiently function as a protective film. When the underlayer protective layer also serves as an interlayer insulating film between IC elements and wiring connecting these, usually 4
The thickness is about 00 to 600 nm. If the insulating film is too thick, cracks occur due to stress in the insulating film. Therefore, the maximum thickness is preferably about 2 μm. When it is strongly necessary to consider productivity, the upper limit of the insulating film thickness is about 1 μm.

Next, the semiconductor thin film 3 will be described. In addition to the group IV single semiconductor film such as a semiconductor film to which the present invention is applied silicon (Si) or germanium (Ge), silicon germanium _{(Si x Ge 1-x:} 0 <x <
1) and silicon carbide _{(Si x C 1-x:} 0 <x
<1) and germanium carbide _{(Ge x C 1-x:}
Semiconductor film of a group 4 element complex such as 0 <x <1), gallium arsenide (GaAs), indium antimony (InS
b) or a composite compound semiconductor film of a Group III element and a Group V element, or a composite compound semiconductor film of a Group II element and a Group 6 element such as cadmium selenium (CdSe). Alternatively, silicon, germanium, gallium, arsenic (Si _x G
_{e y Ga z As z: x} + y + z = 1) and the further complex compound semiconductor film say and phosphorus in these semiconductor films (P), arsenic (As), N-type semiconductor obtained by adding a donor element such as antimony (Sb) The present invention is applicable to a film or a P-type semiconductor film to which an acceptor element such as boron (B), aluminum (Al), gallium (Ga), or indium (In) is added. These semiconductor films are formed by APCVD.
It is formed by a CVD method such as an LPCVD method or a PECVD method, or a PVD method such as a sputtering method or an evaporation method. In the case where a silicon film is used as a semiconductor film, disilane (Si ₂ H ₆ ) or the like can be deposited by using LPCVD at a substrate temperature of about 400 ° C. to about 700 ° C. PEC
In the VD method, deposition can be performed at a substrate temperature of about 100 ° C. to about 500 ° C. using monosilane (SiH ₄ ) as a raw material. When using the sputter method, the substrate temperature should be between room temperature and 4
It is about 00 ° C. The initial state of the semiconductor film deposited in this manner has various states such as amorphous, mixed crystal, microcrystalline, and polycrystalline. In the present invention, the initial state is any state. It does not matter. In the specification of the present application, not only amorphous crystallization but also polycrystalline or microcrystalline recrystallization is referred to as crystallization. When the semiconductor film is used for a semiconductor thin film transistor, the thickness is preferably about 20 nm to about 100 nm.

(2. Crystallization of Semiconductor Thin Film) After forming a base insulating film and a semiconductor film on a substrate, the semiconductor film is crystallized. The crystallization may be performed by any method such as crystallization by laser irradiation or crystallization in a solid phase by heating the substrate. Here, a method of crystallization by laser irradiation, which is usually performed, will be described.

Usually, C such as LPCVD, PECVD, etc.
The surface of a silicon film deposited by the VD method is often covered with a natural oxide film. Therefore, it is necessary to remove the natural oxide film before irradiating the laser beam. For this purpose, there are a method of wet etching by immersion in a hydrofluoric acid solution, a dry etching in a plasma containing fluorine, and the like.

Next, the substrate provided with the semiconductor film is set in a laser irradiation chamber. A part of the laser irradiation chamber is made of a quartz window, and after evacuating the chamber to vacuum and replacing the atmosphere in the chamber with a vacuum or a non-oxidizing gas, a laser beam is irradiated from the quartz window.

Here, the laser beam will be described. It is desired that the laser light is strongly absorbed on the surface of the semiconductor film 3 and hardly absorbed by the underlying insulating film 2 and the substrate 1 immediately below. Therefore, as the laser light, an excimer laser, an argon ion laser, a YAG laser harmonic, or the like having a wavelength in or near the ultraviolet region is preferable. Also,
In order to heat the semiconductor thin film to a high temperature and at the same time prevent damage to the substrate, it is necessary to have a large output and pulse oscillation for an extremely short time. Therefore, among the above laser beams, an excimer laser such as a xenon chloride (XeCl) laser (wavelength 308 nm) or a krypton fluoride (KrF) laser (wavelength 248 nm) is most suitable.

Next, a method for irradiating these laser beams will be described. The half width of the laser pulse intensity is very short, about 10 ns to about 500 ns. Laser irradiation is performed on the substrate between room temperature (about 25 ° C.) and about 400 ° C., and the degree of background vacuum is about 10 ⁻⁴ Torr to about 10 ⁻⁹ T.
This is performed after the atmosphere is evacuated to about orr or after the air is evacuated to the degree of vacuum and replaced with a non-oxidizing atmosphere gas. The irradiation area for one laser irradiation is from about 5 mm square to 60 mm diagonal.
□ The shape is square or rectangular. A case where a beam that can crystallize a square area of, for example, 8 mm square by one irradiation of laser is described. After one laser irradiation to one place, the position of the substrate and the laser is slightly shifted in the horizontal direction relatively.

Thereafter, one laser irradiation is performed again. By continuously repeating the shot and scan, it is possible to cope with a substrate having a large area. More specifically, the irradiation area is shifted from about 1% to about 99% for each irradiation (for example, 50%: 4 mm in the above example). After first scanning in the horizontal direction (X direction), then shifting in the vertical direction (Y direction) by an appropriate amount, scanning again in the horizontal direction by a predetermined amount, and then repeating this scanning to cover the entire surface of the substrate The second laser irradiation is performed. The first laser irradiation energy density is about 50 mJ / cm ² to 6
It is preferably between about 00 mJ / cm ² . After the first laser irradiation is completed, a second laser irradiation is performed on the entire surface as necessary. In the case of performing the second laser irradiation, the energy density is preferably higher than that of the first laser irradiation, and is about 100 mJ / cm ² to 1000 mJ / cm ^2.
It may be between degrees. The scanning method is the same as that of the first laser irradiation, and scans the square irradiation area by shifting it by an appropriate amount in the Y direction and the X direction. Further, if necessary, the third or fourth laser irradiation with a higher energy density can be performed. When such a multi-step laser irradiation method is used, it is possible to completely eliminate the variation caused by the end portion of the laser irradiation area. Not only in each of the multi-stage laser irradiations, but also in the ordinary single-stage irradiation, all the laser irradiations are performed at an energy about 5% lower than the energy density at which the semiconductor film is completely melted. Once the silicon film is completely melted, the liquid silicon film falls into a supercooled state, and as a result, high density crystal nuclei are generated. The poly-Si film formed by such a phenomenon has a form of so-called microcrystal in which extremely small crystal grains exist at a high density. Since such a poly-Si film has many crystal grain boundaries, a large amount of defects (mainly dangling bonds) are present in the film, and the film cannot be used as a TFT.

The laser crystallization method using a square laser beam has been described above.
A line with a length of several tens cm or more with a length of about μm or more,
The crystallization may be advanced by scanning this linear laser light. In this case, the overlap in the width direction of the beam for each irradiation is about 5% to about 95% of the beam width. 10 beam width
If the overlap amount of each beam is 90% at 0 μm, the beam advances by 10 μm for each irradiation, so that the same point receives 10 laser irradiations. Normally, at least about five times of laser irradiation is desired to uniformly crystallize the semiconductor film over the entire substrate, so that the beam overlap amount for each irradiation needs to be about 80% or more. In order to reliably obtain a polycrystalline film having high crystallinity, it is preferable to adjust the overlap amount from about 90% to about 97% so that the same point is irradiated about 10 to 30 times. By using a line beam, crystallization of a large area can be performed by scanning in one direction, so that there is an advantage that the throughput can be increased as compared with the above-described square beam. The maximum irradiation energy density at this time follows the above-mentioned condition.

Here, substrate heating in the laser crystallization step will be described. As described above, since the semiconductor thin film is melted and crystallized by laser irradiation, the temperature of the silicon film rises to 1400 ° C. or higher, and then is rapidly cooled at a rate of about 10 ¹⁰ (K / s) by thermal diffusion to the substrate. Is done. That is, melting and crystal growth are completed at most 100 ns after laser irradiation. As can be easily inferred from this, the formation time of the crystal grain boundaries is extremely short, so that good bonding between silicon atoms cannot be formed, and a large amount of dangling bonds is generated at the crystal grain boundaries. . These dangling bonds form trap levels. As a result, in high-speed crystal growth such as laser crystallization, a trap level of 10 ¹² (cm ⁻² ) or more is generated at a crystal grain boundary. This means that the crystal grain size is 50n, for example.
In the case of a poly-Si film having a thickness of 50 nm and a thickness of 50 nm, the poly-Si film has a capture level of 10 ¹² (cm ⁻² ) or more per unit volume. This high trap level density is hardly reduced even when the substrate is heated to about 400 ° C. This is because the crystal grain boundary formation time is not changed by heating the substrate. As described above, almost no substrate heating is required for controlling the laser crystallization process. In other words, it can be said that there is no particular limitation on the substrate temperature during the laser crystallization process.

In order to improve the characteristics of the semiconductor thin film transistor or to reduce the variation, it is preferable that the step following the laser crystallization step is performed in a state where the substrate is not exposed to the atmosphere outside the apparatus, specifically, in a continuous state in a vacuum. More effective. This is because performing the process in a vacuum is overwhelmingly advantageous for controlling the trap level. In particular, it is desired that laser crystallization, plasma treatment, and gate insulating film formation, which are important for variation control, be performed at least in a continuous process without being exposed to an atmosphere outside the apparatus. When performing continuous processes, it is extremely important that the substrate temperature be constant between those processes or that the substrate temperature be lower in later steps. This is because raising or lowering the temperature of the substrate in a vacuum significantly reduces the throughput of the process.
In a continuous process in a vacuum, the substrate temperature always drops during the transfer of the substrate by the vacuum robot, and therefore, a process in which the processing temperature decreases as the process proceeds is effective. From this viewpoint, it is effective to adjust the substrate temperature in the case of performing laser crystallization to a process that is easily affected by temperature, assuming a continuous process in a vacuum. As will be described later, in particular, since the interface state density at the MOS interface formed by the plasma treatment or the gate insulating film forming process is strongly affected by the substrate temperature, laser crystallization is equivalent to the temperature of the gate insulating film forming process. Alternatively, it is better to adjust to a high temperature. Specifically, about 300 ° C. is desirable.

Although the method of crystallization of a semiconductor film by irradiating a laser to the entire surface of a substrate, which has been generally performed, has been described above, the crystallization of the semiconductor film is performed only in a portion which will later become an active layer of a transistor. You may. Because
This is because portions other than the active layer portion of the transistor are removed in a later element isolation step. The advantage of performing laser irradiation only on the active layer portion of the transistor without scanning the entire surface of the substrate is that, in addition to the improvement of the throughput in the laser irradiation step, the subsequent element separation step becomes easier. The ease of this element isolation step will be described later.

(3. Formation of Gate Insulating Film) poly-Si
An important process at the same time as film formation is a step of forming a high quality MOS interface. It is necessary to reduce the interface order density by successfully bonding oxygen atoms to silicon atoms existing on the poly-Si surface. About 1 on the silicon film surface
Since there are 0 ¹⁵ (cm ⁻² ) bonds, it is important that most of them form a clean chemical bond with SiO ₂ . In order to improve the transistor characteristics of the TFT, it is necessary to suppress the interface order density to about 10 ¹⁰ (cm ⁻² ). That is, only about one defect is allowed for 100,000 silicon bonds, and the other bonds must be bonded to oxygen atoms in an orderly manner, which is very severe.

Therefore, in order to satisfy the above strict requirements, an insulating film 4 is formed as a gate insulating layer on the semiconductor layer 3 after the crystallization of the semiconductor layer and before element isolation ( FIG. 1 (c)). As a method for forming the insulating film, a CVD method such as an atmospheric pressure chemical vapor deposition method (APCVD method), a low pressure chemical vapor deposition method (LPCVD method), a plasma chemical vapor deposition method (PECVD method), or a sputtering method on a substrate. Etc., and any method may be used. Normally, element isolation is performed before the gate insulating film forming step, but in the present invention, it is important to form the gate insulating film first without performing element isolation. This is because if element isolation is performed before the gate insulating film is formed, a photoresist is directly applied to the crystallized semiconductor surface, and after the element is isolated by etching using the photoresist as a mask, it cannot be removed by ashing or the like. This is because the organic components of the photoresist may cause the formation of interface states. Further, it is desirable that the substrate in which the semiconductor layer is crystallized is not exposed to the atmosphere outside the device, and is moved to the insulating film forming step in a state of being isolated from the atmosphere outside the device. Due to contaminants from the atmosphere outside the device, specifically the air, M
This is because the OS interface is contaminated and may cause the formation of interface states.

Further, before the step of forming a gate insulating film, or
After the gate insulating film formation step or before and after the step, plasma treatment or heat treatment may be performed for the purpose of reducing defects in the semiconductor layer or the gate insulating film. As the plasma treatment, hydrogen plasma, oxygen plasma, or the like is often used.
In many cases, the heat treatment is performed in a nitrogen atmosphere, an oxygen atmosphere, a water vapor atmosphere, or a mixed gas atmosphere thereof.
This is performed for the purpose of reducing defects at the OS interface.

(4. Formation of Gate Wiring) Next, a gate wiring layer 5 is deposited (FIG. 1D). This material is desired to have a low electric resistance and to be stable to a heat process at about 350 ° C., for example, a high melting point metal such as tantalum, tungsten, and chromium is suitable. When the source and the drain are formed by ion doping, the thickness of the gate electrode is set to about 700 to prevent the channeling of hydrogen.
nm is required. 700 nm among the refractory metals
Tantalum is most suitable for a material that does not cause cracks due to film stress even when formed with a large film thickness. The gate wiring layer may be deposited by any method such as a sputtering method, a CVD method, and an evaporation method. What is important here is the order of the processing steps, and it is important that no patterning is performed once from the step of forming the base insulating layer on the substrate to the step of depositing the gate wiring layer. By not performing patterning until the gate wiring layer is deposited, it is possible to continuously perform processing up to this step without being exposed to an atmosphere outside the apparatus, and even when exposed to an atmosphere outside the apparatus, Processing can be performed without directly contaminating a portion of the semiconductor layer to be a channel with a photoresist or a by-product thereof. According to this method, contaminants do not enter the semiconductor layer of the semiconductor thin film transistor, the interface between the semiconductor and the gate insulating layer, in the gate insulating film, and at the interface between the gate insulating film and the gate wiring. Deterioration can be suppressed.

Next, the gate wiring layer 5 is patterned to form a gate wiring (FIG. 1E). The patterning at this time is performed by ordinary photolithography and etching. Since the substrate is patterned for the first time in this step, the substrate is completely flat at the stage of applying and exposing the photoresist. Therefore, it is extremely advantageous in a process such as a gate wiring in which accuracy of processing dimensions is required. Because, when a photoresist is applied on a substrate having a stepped shape due to patterning, local unevenness occurs in the thickness of the photoresist,
This is because, in the subsequent exposure step, insufficient exposure occurs in a portion where the photoresist is thick, and excessive exposure occurs in a portion where the photoresist is thin, resulting in a problem that the uniformity of the gate wiring width is reduced.
In addition, the material generally used for the gate wiring layer is a metal and has a high reflectance, so that when the substrate has a stepped shape,
At the time of exposure, irregular reflection occurs at a step portion on the substrate, and a portion where the exposure is excessively large occurs. This also becomes a factor of deteriorating the uniformity of the processing dimensions of the gate wiring. If the processing is performed in the order of the steps of the present invention, the wiring width uniformity in the gate wiring patterning step can be improved.

(5. Impurity Implantation Step) Subsequently, impurity ions are implanted into the semiconductor film to form source / drain regions. At this time, since the gate electrode serves as a mask for ion implantation, the channel has a self-aligned structure formed only under the gate electrode. Impurity ion implantation is an ion doping method in which hydride and hydrogen of an impurity element are implanted using a mass non-separable ion implanter, and an ion implantation method in which only a desired impurity element is implanted using a mass separable ion implanter. Two types of law can be applied. ion·
Phosphine (PH ₃ ) having a concentration of about 0.1% to about 10% diluted in hydrogen is used as a source gas for the doping method.
And a hydride of an implantation impurity element such as diborane (B ₂ H ₆ ) or the like. In the ion implantation method, only a desired impurity element is implanted, and then hydrogen ions (protons or hydrogen molecular ions) are implanted. In order to keep the MOS interface and the gate insulating film stable, it is preferable that the substrate temperature at the time of ion implantation be 350 ° C. or lower regardless of the ion doping method or the ion implantation method. On the other hand, the activation of the implanted impurity is 35
For stable operation at a low temperature of 0 ° C. or less, it is desirable that the substrate temperature at the time of ion implantation be 200 ° C. or more. In order to reliably activate low-concentration impurity ions at a low temperature such as channel doping to adjust the threshold voltage of a transistor or to form an LDD structure, the substrate at the time of ion implantation is required. The temperature needs to be 250 ° C. or higher. When the ion implantation is performed in such a state where the substrate temperature is high, recrystallization occurs at the same time as the crystal breakage accompanying the ion implantation of the semiconductor film, and as a result, it is possible to prevent the ion implantation portion from becoming amorphous. It is. That is, the ion-implanted region still remains crystalline after the implantation,
Even if the subsequent activation temperature is as low as about 350 ° C. or less, activation of the implanted ions becomes possible. When creating a CMOS TFT, one of NMOS or PMOS is alternately covered with a mask using an appropriate mask material such as polyimide resin,
Each ion implantation is performed by the above-described method.

(6. Element Isolation Step) Here, FIG.
As shown in FIG. 7, the insulating film 4 and the semiconductor film 3 are continuously etched. After a pattern is formed on the insulating film 4 and the gate wiring 5 by photolithography so that only a portion to be an active layer of the transistor remains, the gate insulating film is etched by wet or dry etching. At this time, since the portions other than the transistor portion of the gate wiring are not covered with the photoresist, it is necessary to perform the processing under the condition that the selection ratio of the gate wiring material and the etching of the gate insulating film is large. However, since the transistor portion is covered with the photoresist, the gate length, which is an important parameter that determines the performance of the transistor, is not affected.
Subsequently, the semiconductor film is etched by wet or dry etching. At this time, a semiconductor layer exists under a gate wiring with a gate insulating film interposed therebetween, except for a portion to be an active layer of the transistor. Therefore, the etching in this step must be an isotropic etching method in order to remove the semiconductor layer under the gate wiring. Also,
In the case where the semiconductor layer is crystallized by irradiating only a portion to be an active layer of the transistor with a laser in the crystallization step, the selectivity between the crystalline semiconductor and the amorphous semiconductor during etching of the semiconductor layer is increased. By etching under the condition that the value of is large, a portion of the semiconductor layer that does not become an active layer of the transistor can be easily removed. In addition, when the elements are sufficiently separated, the amorphous semiconductor has a sufficiently large electric resistance as compared with the crystalline semiconductor, so that the amorphous semiconductor layer under the gate wiring other than the portion that becomes the active layer of the transistor is removed. do not have to.

(7. Subsequent Steps) Since the isolation of the semiconductor layer and the formation of the gate wiring have been completed in the steps so far, the interlayer insulating film 6 is deposited on the substrate by CVD or the like. Contact holes are formed in the source and drain portions of the interlayer insulating film and the gate insulating film, and a source / drain extraction electrode 7 and a wiring are formed by a PVD method, a CVD method, or the like, thereby completing a thin film transistor (FIG. 1).
(G))

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIG. The substrate and the underlying protective film used in the present invention conform to the above description, but here, as an example of the substrate, 300 mm
A 300 mm square general-purpose non-alkali glass 1 is used. First, a base protective film 2 which is an insulating material is formed on a substrate 1. Here, 500 with a parallel plate type PECVD equipment
A silicon oxide film having a thickness of about nm is deposited. Next, a semiconductor film 3 such as an intrinsic silicon film to be an active layer of a thin film transistor is deposited later. The thickness of the semiconductor film is about 50 nm. In this example, disilane (Si ₂ H ₆ ) as a source gas was supplied at 200 SCCM using a high vacuum LPCVD apparatus.
The amorphous silicon film 103 is deposited at a deposition temperature of 425 ° C. First, the reaction chamber of the high vacuum LPCVD apparatus is 25
At a temperature of 0 ° C., a plurality of sheets (for example, 17
Are placed with their front sides facing downward. After this, the operation of the turbo-molecular pump is started. After the turbo-molecular pump reaches steady rotation, the temperature in the reaction chamber is raised from 250 ° C. to a deposition temperature of 425 ° C. over about one hour.
During the first 10 minutes after the start of the temperature rise, the temperature was raised in a vacuum without introducing any gas into the reaction chamber, and then the purity was 99.999.
The nitrogen gas of 9% or more is kept flowing at 300 SCCM. The equilibrium pressure in the reaction chamber at this time is 3.0 × 10 ⁻³ T
orr. After reaching the deposition temperature, disilane (Si ₂ H ₆ ) as a source gas is flowed at 200 SCCM,
Helium (He) for dilution with a purity of 99.9999% or more
At 1000 SCCM. The pressure in the reaction chamber immediately after the start of the deposition is about 0.85 Torr. As the deposition proceeds, the pressure in the reaction chamber gradually increases, and the pressure immediately before the end of the deposition becomes approximately 1.25 Torr. The silicon film (103) thus deposited has a thickness of 286 mm except for about 7 mm at the periphery of the substrate.
Within the corner region, the variation in the film thickness is within ± 5%.

Next, laser crystallization is performed. The substrate is transferred by a robot in a vacuum from a chamber for depositing amorphous silicon to a chamber for irradiating a laser. As a result, contamination of the silicon film surface from the environment can be minimized.

Next, laser light irradiation is performed. In this embodiment, an excimer laser (wavelength: 308 nm) of xenon chloride (XeCl) is applied. The half width of the laser pulse intensity (half width with respect to time) is 25 ns.
The substrate is set in the evacuated vacuum chamber, and the substrate temperature is raised to 300 ° C. One laser irradiation area has a line shape of 300 mm length × 300 μm width, and the energy density on the irradiation surface is 400 mJ / cm ² .
Irradiation is repeated while overlapping the laser beams by 90% in the width direction (that is, by 30 μm each time the laser beam is irradiated) (see FIG. 3). Thus, the amorphous silicon on the entire substrate having a side of 300 mm is crystallized. In order to minimize the occurrence of roughness due to crystallization, an edge region is formed in front and rear in the width direction of the line beam.
μm (ie the region of weak energy density)
Before laser irradiation with an energy density of 400 mJ / cm ² is performed on the a-Si film, laser irradiation with lower energy is performed. By gradually increasing the irradiation energy in this manner, crystallization is performed while suppressing the surface roughness.

Next, the substrate 1 is transferred to the plasma processing chamber while maintaining the vacuum. The substrate temperature decreases by about 50 ° C. during the transfer by the vacuum robot. In the plasma processing chamber, the substrate temperature was set to 250 ° C., hydrogen gas was flowed at 80 sccm, and plasma discharge was performed at a pressure of 1 Torr and a power of 1 kW using a parallel plate RF electrode. As a result, the trap level inactivation treatment of the laser-crystallized poly-Si film and the hydrogen termination treatment of the surface are performed for 160 seconds.

Next, the substrate 1 is transferred to the insulating film forming chamber while maintaining the vacuum. After the substrate transfer, the inside of the chamber is evacuated to a degree of vacuum of the order of 10 ⁻⁶ (torr). The temperature of the substrate further decreased during the vacuum transfer, and the temperature of the substrate was adjusted to room temperature in the insulating film forming chamber. During this time, silane gas and oxygen gas are introduced into the chamber at a flow ratio of 1: 6, and the chamber pressure is adjusted to 2 × 10 ⁻³ (Torr). When the gas pressure in the chamber is stabilized, the ECR discharge is started, and the formation of the insulating film is started. The applied microwave power was 1 kW, and the microwaves were introduced from the introduction window in parallel with the lines of magnetic force. There is an ECR point at a position 14 cm from the introduction window. The film was formed at a film formation rate of 100 (nm / min.). As a result, the gate insulating film 4 has a thickness of 100n.
m.

Next, a thin film to be the gate electrode 5 is deposited by a PVD method or a CVD method. Usually, the gate electrode and the gate wiring are made of the same material in the same process, so that this material is desired to have low electric resistance and to be stable to a heat process of about 350 ° C. In this embodiment, a tantalum thin film having a thickness of 600 nm is formed by a sputtering method. The substrate temperature for forming the tantalum thin film is 180 ° C., and an argon gas containing 6.7% of a nitrogen gas is used as a sputtering gas. The thus formed tantalum thin film has an α-structure crystal structure, and its specific resistance is about 40 μΩcm. After depositing a thin film to be a gate electrode, patterning is performed, and then impurity ion implantation is performed on the semiconductor film to form a source / drain region and a channel region. At this time, since the gate electrode serves as a mask for ion implantation, the channel has a self-aligned structure formed only under the gate electrode. As a source gas for the ion doping method, a hydride of an implanted impurity element such as phosphine (PH ₃ ) or diborane (B ₂ H ₆ ) diluted in hydrogen and having a concentration of about 0.1% to about 10% is used. In this example, phosphine (PH ₃ ) having a concentration of 5% diluted in hydrogen is injected at an acceleration voltage of 100 keV using an ion doping apparatus with the aim of forming an NMOS. The total ion implantation amount including PH ₃₊ and H ₂₊ ions is 1 × 10 ¹⁶ cm ⁻² .

Next, the gate electrode 5 is patterned by ordinary photolithography and dry etching. Subsequently, the photoresist is processed to be slightly larger than the shape of the portion to be the active layer of the transistor by photolithography, and the gate insulating film is etched perpendicular to the substrate by dry etching. Subsequent to the etching of the gate insulating film, the semiconductor layer is etched by isotropic etching. As a method of etching the semiconductor layer, sulfur hexafluoride (SF ₆ ) gas and chlorine (Cl
₂ ) Chemical dry etching is performed using a gas mixture. The reason for processing the semiconductor layer slightly larger than the active layer of the transistor before patterning the gate insulating film is that since the etching is isotropic, the shape of the semiconductor layer after etching is smaller than the processing dimension of the photoresist. is there.

Next, a 500 nm thick silicon oxide film is deposited on the interlayer insulating film by parallel plate PECVD using a mixed gas of TEOS gas and oxygen gas, and then a contact hole is formed on the source / drain. The drain extraction electrode 7 and the wiring are formed by a PVD method, a CVD method, or the like to complete a thin film transistor.

In the prior art, since the contamination of the semiconductor layer and the gate insulating film of the thin film transistor or the interface thereof cannot be controlled, there is a limit to the performance improvement of the transistor. In addition, since each transistor has a stepped shape at the time of gate patterning, it is difficult to make the gate length of the transistor uniform in the substrate surface. According to the present invention, a high-performance transistor can be formed uniformly in a plane.

[0047]

According to the method of manufacturing a semiconductor thin film transistor of the present invention, an interface between a base protective layer and a semiconductor layer, a semiconductor layer, an interface between a semiconductor layer and a gate insulating film, a gate insulating film, and a gate insulating film and a gate electrode are provided. Can be manufactured in a clean state without exposing the interface to a contamination source, so that a high-performance transistor can be manufactured, and a thin-film transistor having a uniform gate length over the substrate surface can be manufactured.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a method of manufacturing a semiconductor thin film transistor according to the present invention in the order of steps.

FIG. 2 is a cross-sectional view in a process order showing a process up to a gate insulating film forming process in a conventional method of manufacturing a semiconductor thin film transistor.

[Explanation of symbols]

 1. Substrate 2. 2. Insulating film Semiconductor layer 4. Insulating film 5. Gate wiring layer 6. 6. interlayer insulating film Source electrode, drain electrode 2-1. Substrate 2-2. Insulating film 2-3. Semiconductor layer 2-4. Photoresist 2-5. Insulating film

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) FF32.

Claims (7)

[Claims] A step of forming a first insulating film as a base protective layer on a substrate, a step of forming a semiconductor layer on the base protective layer, and a step of forming a crystal of the semiconductor layer in a non-oxidizing atmosphere. And a step of forming a second insulating film as a gate insulating layer on the semiconductor layer, a step of depositing a gate wiring layer on the gate insulating layer, and patterning the gate wiring layer. A method of forming a gate wiring, and a step of patterning a gate insulating layer and a semiconductor layer to perform element isolation, and performing these steps in this order. 2. The manufacturing method of a semiconductor thin film transistor according to claim 1, wherein the steps from the step of forming the base protective layer to the step of depositing the gate wiring layer are performed continuously without exposing the substrate to an atmosphere outside the device. Method. 3. The method according to claim 1, wherein crystallization of the semiconductor layer is performed by irradiating a laser. 4. The method of manufacturing a semiconductor thin film transistor according to claim 1, wherein the crystallization of the semiconductor layer is performed by selectively crystallizing only a portion to be an active layer of the transistor later. 5. The method according to claim 4, wherein the crystallization of the semiconductor layer is performed by irradiating a laser. 6. An electro-optical device comprising a step of using the method of manufacturing a thin film transistor according to claim 1. 7. An electro-optical device including a thin film transistor manufactured by the method of manufacturing a thin film transistor according to claim 1.