CN1273693A - Method of forming singl-crystal silicon layer and method of manufacturing semiconductor device - Google Patents
Method of forming singl-crystal silicon layer and method of manufacturing semiconductor device Download PDFInfo
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- CN1273693A CN1273693A CN 99801049 CN99801049A CN1273693A CN 1273693 A CN1273693 A CN 1273693A CN 99801049 CN99801049 CN 99801049 CN 99801049 A CN99801049 A CN 99801049A CN 1273693 A CN1273693 A CN 1273693A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76248—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using lateral overgrowth techniques, i.e. ELO techniques
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/02428—Structure
- H01L21/0243—Surface structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Abstract
Steps (4) formed on an insulating substrate (1) are used as seeds for depositing single-crystal silicon by catalytic CVD to form an epitaxial silicon layer (7). A large-sized glass substrate with a relatively low strain point can be used to form the epitaxial silicon layer (7) uniformly at low temperature. Therefore, a high-speed semiconductor device of large current density can be provided.
Description
The method that the present invention relates to form the method for monocrystalline silicon layer and make semiconductor device.Specifically, the present invention relates on dielectric substrate the epitaxial growth monocrystalline silicon layer as the method for active area manufacturing such as the isolated-gate field effect transistor (IGFET) semiconductor element.
TFT (thin-film transistor) utilizes to form the MOSFET (mos field effect transistor) that monocrystalline silicon layer is made on substrate.As prior art is disclosed, TFT demonstrates high several times of the transistorized mobility that its electron mobility Billy makes with polysilicon layer, and TFT is suitable for high speed operation (face reference as follows, R.P.Zingg et al. " First MOStransistors on Insulator by Silicon Saturated Liquid SolutionEpitaxy " .IEEE ELECTRON DEVICE LETTERS.VOL.13, N0.5 MAY1992 p294-6., Publication of Examined Japanese Patent ApplicationN0.Hei 4-57098, Masakiyo Matsumura, " Thin Film Transistor; " OYOBUTURI, VOL.65, N0.8 (1996) pp842-848).
About the monocrystalline silicon layer that forms above-mentioned semiconductor element 5 kinds of methods are arranged:
(1) by approximately decomposing silane, dichlorosilane under 800-1200 ℃ of nitrogen atmosphere 100-760Torr air pressure.Trichlorosilane, silicon tetrachloride growing single-crystal silicon.
(2) be heated to 920-930 ℃ indium melted silicon or indium gallium silicon solution by cooling and on monocrystalline substrate, form silicon epitaxy layer as seed crystal, form the silicon semiconductor layer (data that sees reference 1.Soo Hong Lee " VERY-LOW-TEMPERATURE LIQUID-PHASE EPITAXIAL GROWTH OF SILICON " .MATERIALSLETTERS.Vol.9.N0.2 then thereon, 3 (Jan.1990) pp53-56. reference 2, R.Bergmann etal, " MOS transistors with epitaxial Si laterally grown over SiO
2Byliquid phase epitaxy. " J.Applied Physics A; Vol.A54; no.1p.103-5. reference 3; R; Pzingg et al. " First MOS transistors on Insulator by SiliconSaturated Liquid Solution Epitaxy. " IEEE ELECTRON DEVICELETTERS VOL.13; N0.5, MAY 1992 p294-6.).
(3) on Sapphire Substrate epitaxially grown silicon (data 4 sees reference, G A Garcia, R.E.Reedy, and M.L.Burger, " High-quality CMOS in thin (100nm) silicon on sapphire; " IEEE ELECTRON DEVICE LETTERS, VOL.9, pp32-34 Jan.1988.).
(4) be infused in by oxonium ion and form silicon layer (data 5 that sees reference, K.Izumi, M.Doken, and H.Ariyoshtl, " CMOS device fabrication onburied SiO on the insulating barrier
2Layers formed by oxygen implantation into silicon, " Electon.Lett., vol.14, no, 18, pp593-594, Aug.1978.).
(5) on quartz substrate, form step, form polysilicon layer then thereon, utilize laser beam or strip heater that it is heated to 1400 ℃ or higher again, on the step that forms as the quartz substrate of seed crystal, form epitaxial loayer (row reference as follows: reference 6, SeijiroFurukawa, " Graphoepitaxy " The Transactions of the institute ofElectronics, Information and Communication Engineers, VOL.66, N0.5, pp486-489. (1983.May). reference 7, Geis, M.W., et al. " Crystallographicorientation of silicon on an amorphous substrate using an artificial-relief grating and laser crystallization ", Appl.Phys.Letter, 35,1, pp71-74 (July 1979). reference 8, Geis, M.W., et al. " Silicongraphoepitaxy ", Jpn.J.Appl.Phys.Suppl.20-1 pp.39-42 (1981).
In accordance with known methods, the form (providing by heating) with heat energy provides chemical reaction/crystal growth required whole energy.This causes epitaxial temperature significantly to be reduced to and is lower than about 800 ℃ problem, has hindered the research of grown silicon epitaxial loayer method on the big glass plate with low relatively strain point.On the other hand, grown silicon can not obtain uniform epitaxially grown silicon to begin epitaxially grown method at low temperature on the step that the glass plate as seed crystal forms.
This invention can overcome described shortcoming.The purpose of this invention is to provide the method that forms semiconductor layer and make semiconductor device, can on glass substrate, form even epitaxial growth silicon layer, can form the high-speed semiconductor element of high current density thereon with low relatively strain point with low temperature.
The method that the present invention forms monocrystalline silicon layer comprises the following steps: to form step on substrate, form thereon on the substrate of step to utilize catalyst to form the monocrystalline silicon with predetermined thickness by CVD (chemical vapor deposition).
The method that the present invention makes semiconductor device comprises the step of described formation monocrystalline silicon layer and makes the subsequent step of semiconductor element by the preliminary treatment monocrystalline silicon layer.
According to method of the present invention, utilize catalyst deposit (epitaxial growth) monocrystalline silicon on the step that the substrate as seed crystal forms by CVD.This can obtain multiple remarkable result and advantage, and concrete condition is as described below:
(A) forming silicon single-crystal film on as the step of seed crystal utilizes the low temperature deposition method to begin growing epitaxial silicon, just, utilize catalyst (wherein substrate temperature is 200-800 ℃, particularly 200-600 ℃) on substrate, to be formed uniformly monocrystalline silicon membrane with low temperature.
(B) this may utilize the substrate of easy buy cheap, and this substrate for example has the glass substrate or the ceramic substrate of low relatively strain point by the excellent material manufacturing.Certainly, can utilize the substrate of making by quartz glass.In addition, may utilize grow (greater than 100m) and than high surface area (greater than 1m
2) substrate.
(C) electron mobility of the silicon single crystal thin film that forms with low temperature on glass substrate or other substrate is 540cm
2/ v.sec big like that (seeing described reference 3), it is equivalent to the electron mobility of silicon substrate.Therefore, may on glass substrate, make and have at a high speed and the top grid of the LCD (LCD) of high current density, bottom gate or double grid TFT, the transistor of EL (electron luminescence) or FED (Field Emission Display), the high-performance semiconductor element, for example, diode, solar cell, capacitor or resistor etc., or integrated circuit.
Figure 1A and Figure 1B are each processing step of semiconductor device is made in explanation in order according to the embodiment of the invention cross-sectional views.
Fig. 2 A is the cross-sectional view that each step of the step shown in Figure 1 that continues is described to Fig. 2 C.
Fig. 3 A is the cross-sectional view that each step of the step shown in Figure 2 that continues is described to Fig. 3 C.
Fig. 4 A is the cross-sectional view that each step of the step shown in Figure 3 that continues is described to Fig. 4 C.
Fig. 5 is the sketch map that utilizes the CVD system of catalyst according to of the present invention, is used for producing the semiconductor devices.
Fig. 6 A and Fig. 6 B are described in the perspective view that carries out the silicon crystal growth on the amorphous silicon substrate.
Fig. 7 A is the sketch of expression various forms step and according to the diagram extension sketch in the crystal orientation of growing silicon crystal thereon to Fig. 7 E.
Present embodiment relates to utilization and forms step such as dry corrosion such as reactive ion etchings on dielectric substrate, utilizes catalyst (wherein substrate temperature is about 200-800 ℃) to form monocrystalline silicon layer by the CVD method.
Utilizing catalyst to form in the process of monocrystalline silicon layer, preferably by contacting the gas that decomposes the hydride that mainly comprises silicon with the catalyst that is heated to for example 800-2000 ℃ (being lower than its fusing point), deposit monocrystalline silicon layer on substrate by CVD.In this case, the hydride of silicon is silane preferably, and catalyst body is to be selected from by tungsten at least, comprises the tungsten of thorium oxide, molybdenum, and platinum, palladium, silicon, aluminium oxide has a kind of material in the group that the pottery of metal and carborundum constitutes.
Present embodiment can particularly have 1m on dielectric substrate
2Form crystal semiconductor layer on the big glass substrate with top surface area.In this embodiment, utilize catalyst very low, make and to utilize the low glass substrate that constitutes to the glass of 470-670 ℃ of strain point by the underlayer temperature that CVD handles.Cheap and the easy thin plate that forms of such glass.Therefore utilize this glass to form glass plate with the shape of long paper.On the glass plate of long paper shape, can utilize said method to form the thin epitaxy layer continuously or discontinuously.When utilizing the glass of described low strain point, be diffused into easily in the above-mentioned layer in order to prevent the element that constitutes this glass plate, wish on glass plate, to form film (for example constituting) as diffusion impervious layer by the thick silicon nitride of the 10-1000 dust order of magnitude.
Present embodiment also can be deposited on as the monocrystalline silicon layer on the above-mentioned step of seed crystal by preliminary treatment, makes semiconductor element.
In the technology of deposit monocrystalline silicon layer, dopant type in the silicon epitaxy layer that will grow (P type or N type) and/or carrier density are by for example B that mixes
2H
6, PH
3An amount of III family that form provides or V group element (for example, B, P, Sb As) can be by Optimal Control.
Present embodiment requires to be the channel region of isolated-gate field effect transistor (IGFET) that source region, drain region be epitaxial growth monocrystalline silicon on substrate, so that the dopant type and/or the impurity concentration in each district of control.
Be described in detail the ad hoc approach of making above-mentioned isolated-gate field effect transistor (IGFET) to Fig. 7 below with reference to Fig. 1.
At first, shown in Figure 1A, on dielectric substrate 1 first type surface, form photoresist 2 with predetermined pattern, this substrate 1 for example by quartz glass or glass ceramics (specifically, has about 470-1400 ℃ strain point, preferably have 470-670 ℃ of strain point, thickness is the glass substrate of several millimeters of 50 μ m-) constitute.Then, as mask, utilize for example CF with photoresist 2
4The F of plasma
+Ion 3 irradiation substrates 1 utilize RIE (reactive ion etching) to form a plurality of steps 4 then on substrate 1.In this case, step is as the seed crystal that is used to begin epitaxial growth monocrystalline silicon, and is as described below.The degree of depth of step 4 and width can be respectively 0.1 μ m and 1.5-1.9 μ m.
Then, shown in Figure 1B, after removing photoresist 2, by CVD to utilize catalyst to form epitaxial growth thickness on the whole surface of step 4 thereon be a few μ m to the monocrystalline silicon layer 7 of 0.005 μ m (for example 0.1 μ m) (wherein, substrate temperature is 200-800 ℃), for example have disclosed among the clear 63-40314 of JP-A N0..
Utilize the CVD technology of catalyst by the CVD system that utilizes catalyst shown in Figure 5.In utilizing the CVD system of catalyst, (add such as B as required from hydride (for example single silane) gas 40 of air supply pipe with silicon
2H
6Or PH
3Impurity gas) is incorporated into deposition chamber 41.The bearing 42 of support substrates 1 is housed and towards the catalyst body 43 of the coiled type of bearing 42 in the inside of deposition chamber 41.Utilize external heat device 44 (for example electric heater unit) heated substrate 1.Catalyst body 43 by will for example be made of resistance wire is heated to the temperature that is lower than fusing point (if utilize tungsten, preferably 800-2000 ℃, about 1700 ℃) and makes it activation.
By ventilation (approximately 15-20 branch) atmosphere in the deposition chamber 41 is changed into nitrogen atmosphere from blanket of nitrogen, be heated to about 200-800 ℃ then.By contacting, silane gas is decomposed, and be deposited on the substrate 1 that remains on low temperature (for example 300 ℃) with catalyst body 43.Can obtain the time of deposit from the thickness of the epitaxial loayer that will grow.Behind the growth ending, change into blanket of nitrogen, take out substrate 1 by the atmosphere of ventilation cooled interior and from nitrogen atmosphere.So the divided silicon atom that utilizes the catalytic reaction of catalyst body 43 or thermal decomposition to make to have high energy or the silicon atom of gathering form and are deposited on the step 4 as seed crystal.This makes the much lower low temperature deposition silicon fiml of deposition temperature when may use situation than hot CVD.
The monocrystalline silicon layer 7 of deposit has epitaxially grown on substrate (100) surface like this, and this is because well-knownly be called (the seeing above-mentioned reference 6,7,8) that the phenomenon that illustrates extension causes.As shown in Figure 6A, these layers are random orientations.But have deposit epitaxial loayer on the amorphous substrate (glass) 1 of the vertical step of sidewall 4, then making this layer have its (100) surface, shown in Fig. 6 B along the vertical wall growth of step 4.The size and the temperature and time of single die are proportional.Under the situation of low temperature and short time deposit, can reduce the spacing between the step.To shown in the 7E, form step as Fig. 7 A, make it possible to the crystal orientation of control growing layer with various forms.In most of the cases, on (100) surface, make MOS transistor.
Utilize catalyst and diagram extension behind deposit monocrystalline silicon layer 7 on the substrate 1 by CVD, utilize monocrystalline silicon layer 7 to make MOS transistor (TFT) as channel region.Shown in Fig. 2 C, forming thickness by oxidation (950 ℃) on the surface of monocrystalline silicon layer 7 is the gate oxidation films 8 of 350 dusts.
Then shown in Fig. 2 D, in order to control N-channel MOS transistor channel region impurity concentration, with photoresist 9 mask P channel MOS transistor zones, utilize for example 10KV, dosage is 2.7 * 10
11Atom/cm
2Ion injects p type foreign ion 10 (B for example
+) form silicon layer 11, obtain this layer by the monocrystalline silicon layer 7 of making p type conduction type.Shown in Fig. 2 E, in order to control p channel MOS transistor channel region impurity concentration, with photoresist 12 mask N-channel MOS transistor area, utilize for example 10KV then, dosage is 1 * 10
11Atom/cm
2Ion injects N type foreign ion (P for example
+) 13 formation silicon layers 14, obtain these layers by the monocrystalline silicon layer 7 of making N type conduction type.Then as shown in Figure 3A, utilizing CVD (under 620 ℃ of temperature) deposition thickness is that the polysilicon layer 15 of Doping Phosphorus of 4000 dusts is as the material of gate electrode.
Shown in Fig. 3 B, form photoresist 16 then, as mask polysilicon layer 15 is patterned into the figure of gate electrode with photoresist 16 according to predetermined pattern.Shown in Fig. 3 C, after removing photoresist 16, by at O
2Carry out oxidation in 60 minutes with 900 ℃ in the atmosphere, on gate electrode polysilicon 15 surfaces, form oxide-film 17.Shown in Fig. 3 C, with photoresist 18 mask P channel MOS transistor zones, utilize for example 20KV then, dosage for example is 5 * 10
15Atom/cm
2Ion injects for example As of N type impurity
+Ion 19.By at N
2Formed the transistorized N of N-channel MOS in 40 minutes 950 ℃ of annealing in the atmosphere
+ Type source region 20 and drain region 21.
Shown in Fig. 4 A, with photoresist 22 mask N-channel MOS transistor area, utilize for example 10KV then, dosage for example is 5 * 10
15Atom/cm
2Ion injects for example B of p type impurity
+Ion 23.By at N
2Formed the P of P channel MOS transistor in the atmosphere in 5 minutes 900 ℃ of annealing
+ Type source region 24 and drain region 25.
Shown in Fig. 4 B, on the entire wafer surface, utilize CVD then at for example 750 ℃ of SiO that deposition thickness is 500 dusts
2Film 26 is at for example 420 ℃ of SiN films 27 that deposition thickness is 2000 dusts.In addition, for example 450 ℃ to form thickness be that boron-doping phosphorosilicate glass (BPSG) film 28 of 6000 dusts is as the backflow film, then at for example N
2900 ℃ of backflow bpsg films 28 of atmosphere.
At last, shown in Fig. 4 C, contact window is opened in precalculated position at dielectric film, utilizing on the whole surface of perforate therein then and sputtering at 150 ℃ of deposition thicknesses is the film that 1 μ m is made of the electrode material such as aluminium, and, make each P-channel mosfet and N-channel MOS FET form source and drain electrode 29 (S and D) and the gate electrode or 30 (G) that connect up its composition.Make each MOSFET like this.
Effect and the advantage of this embodiment are as described below:
(a) adopt CVD, utilize catalyst and as the step 4 of seed crystal can enough low temperature (200-600 ℃) on glass substrate 1 even growing silicon single crystal film 7.
(b) not only on the glass substrate of low strain point, and can be on such as the dielectric substrate of ceramic substrate the growing silicon single crystal film, provide the wide region of backing material to select, this material strain point is low, buys cheaply superior performance.Make and utilize big substrate to become possibility.
(c) electron mobility of the silicon single crystal thin film 7 of growing on glass substrate or other substrate arrives 540cm greatly
2/ v.sec, it is equivalent to the mobility of silicon substrate.Therefore, may make the high speed transistor of high current density.Except transistor, diode can also be made, capacitor, resistance etc. or integrated circuit on glass substrate.The technology of the silicon semiconductor element of formation such as MOS transistor is identical with the well-known technology of making multi-crystal TFT basically.
Obviously, the above-mentioned embodiment of the invention can technology idea according to the present invention be carried out various changes and modifications.
As mentioned above, the method that forms the method for monocrystalline silicon layer according to the present invention or make semiconductor device relates to by CVD and utilizes catalyst deposit monocrystalline silicon on the step that forms on the substrate as seed crystal.This can make it may utilize the substrate of cheaply having bought easily with function admirable, such as glass substrate or ceramic substrate with low relatively strain point with the even growing single-crystal silicon fiml of low temperature on substrate.In addition, may utilize bigger substrate.And the electron mobility in silicon single crystal thin film is 540cm
2/ v.sec is big like that, and it is equivalent to the mobility of silicon substrate.Therefore, may on glass substrate, make the high speed transistor of high current density, the high-performance semiconductor element, for example, diode, capacitor, resistance or integrated circuit.
As mentioned above, form monocrystalline silicon layer method can in addition on big glass substrate with low relatively strain point with the even epitaxial growth silicon layer of low temperature, suitable manufacturing utilizes the semiconductor element such as isolated-gate field effect transistor (IGFET) of epitaxial growth monocrystalline silicon layer as active area.
Claims (15)
1. form the method for monocrystalline silicon layer, it comprises the following steps:
On substrate, form step;
Utilize catalyst to form thereon by CVD and form monocrystalline silicon layer on the substrate of step with predetermined thickness.
2. according to the method for the described formation monocrystalline silicon layer of claim 1, wherein utilize dry corrosion on dielectric substrate, to form step, growing single-crystal silicon layer under 200-800 ℃ temperature.
3. according to the method for the described formation monocrystalline silicon layer of claim 1, wherein utilize catalyst to form in the process of monocrystalline silicon layer by CVD, contact by catalyst body, decompose the gas of the hydride that mainly comprises silicon, monocrystalline silicon layer is deposited on the substrate with heating.
4. according to the method for the described formation monocrystalline silicon layer of claim 3, wherein, the hydride of silicon is silane, and catalyst body is to be selected from by tungsten at least, the tungsten that comprises thorium oxide, molybdenum, platinum, palladium, silicon, aluminium oxide is with the pottery of metal and a kind of material in the carborundum formation group.
5. according to the method for the described formation monocrystalline silicon layer of claim 2, wherein, dielectric substrate is a glass substrate.
6. according to the method for the described formation monocrystalline silicon layer of claim 5, wherein, on glass substrate, form diffusion impervious layer, growing single-crystal silicon layer on diffusion impervious layer.
7. according to the method for the described formation monocrystalline silicon layer of claim 1, wherein, in deposit monocrystalline silicon layer process, doped with II I family or V group element are so that the dopant type and/or the impurity concentration of control monocrystalline silicon layer.
8. make the method for semiconductor device, it comprises the following steps:
On substrate, form step;
Utilize catalyst to form thereon by CVD and form monocrystalline silicon layer on the substrate of step with predetermined thickness;
Make semiconductor element by the preliminary treatment monocrystalline silicon layer.
9. according to the method for the described manufacturing semiconductor device of claim 8, wherein monocrystalline silicon layer is as the channel region of isolated-gate field effect transistor (IGFET), and source region and drain region are so that III family or the V family dopant type and/or the impurity concentration in each district of control.
10. according to the method for the described manufacturing semiconductor device of claim 8, wherein, utilize dry corrosion on dielectric substrate, to form step, at 200-800 ℃ temperature growing single-crystal silicon layer.
11., wherein, utilize catalyst to form monocrystalline silicon layer by CVD according to the method for the described manufacturing semiconductor device of claim 8, contact the gas that decomposes the hydride that mainly comprises silicon by catalyst body with heating, monocrystalline silicon layer is deposited on the substrate.
12. according to the method for the described manufacturing semiconductor device of claim 11, wherein, the hydride of silicon is silane, catalyst body is to be selected from by tungsten at least, the tungsten that comprises thorium oxide, molybdenum, platinum, palladium, silicon, aluminium oxide, a kind of material in the pottery of attached metal and the carborundum formation group.
13. according to the method for the described manufacturing semiconductor device of claim 10, wherein, dielectric substrate is a glass substrate.
14., wherein, forming diffusion impervious layer on the glass substrate and growing single-crystal silicon layer on this diffusion impervious layer according to the method for the described manufacturing semiconductor device of claim 13.
15. according to the method for the described manufacturing semiconductor device of claim 8, wherein, when the deposit monocrystalline silicon layer, doped with II I family or V group element are so that the dopant type and/or the impurity concentration of control monocrystalline silicon layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18446798A JP2000021782A (en) | 1998-06-30 | 1998-06-30 | Method of forming single crystal silicon layer and manufacture of semiconductor device |
| JP184467/1998 | 1998-06-30 |
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| Publication Number | Publication Date |
|---|---|
| CN1273693A true CN1273693A (en) | 2000-11-15 |
| CN1146020C CN1146020C (en) | 2004-04-14 |
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| CNB998010499A Expired - Fee Related CN1146020C (en) | 1998-06-30 | 1999-06-30 | Method of forming singl-crystal silicon layer and method of manufacturing semiconductor device |
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|---|---|
| JP (1) | JP2000021782A (en) |
| CN (1) | CN1146020C (en) |
| WO (1) | WO2000001004A1 (en) |
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| CN101924101A (en) * | 2010-08-06 | 2010-12-22 | 锐迪科科技有限公司 | Structure of semiconductor passive device and making method thereof |
| CN109652770A (en) * | 2018-11-29 | 2019-04-19 | 天津大学 | Method for regulating vapor deposition metal film texture by using semiconductor substrate |
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| US7119365B2 (en) | 2002-03-26 | 2006-10-10 | Sharp Kabushiki Kaisha | Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate |
| JP2003282885A (en) * | 2002-03-26 | 2003-10-03 | Sharp Corp | Semiconductor device and its fabricating method |
| JP2005259828A (en) * | 2004-03-10 | 2005-09-22 | Sony Corp | Solid state imaging device and its manufacturing method |
| JP2010118675A (en) * | 2010-01-12 | 2010-05-27 | Sony Corp | Solid-state image sensing device and production method of the same |
| CN104392922B (en) * | 2014-11-26 | 2018-06-26 | 上海华力微电子有限公司 | The preparation method of embedded silicon carbide |
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| JPS6340314A (en) * | 1986-08-05 | 1988-02-20 | Hiroshima Univ | Manufacture of thin film by catalytic cvd method and device therefor |
| JPH01259526A (en) * | 1988-04-11 | 1989-10-17 | Matsushita Electron Corp | Formation of single crystal silicon film on insulating film |
| JP3453214B2 (en) * | 1995-03-15 | 2003-10-06 | 科学技術振興事業団 | Method of manufacturing thin film transistor by catalytic CVD method and thin film transistor |
| JP3889071B2 (en) * | 1995-08-04 | 2007-03-07 | 株式会社半導体エネルギー研究所 | Crystalline semiconductor manufacturing method |
| JP2970499B2 (en) * | 1995-10-30 | 1999-11-02 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| JP3858319B2 (en) * | 1996-12-05 | 2006-12-13 | ソニー株式会社 | Quantum wire manufacturing method |
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1998
- 1998-06-30 JP JP18446798A patent/JP2000021782A/en active Pending
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| CN101924101A (en) * | 2010-08-06 | 2010-12-22 | 锐迪科科技有限公司 | Structure of semiconductor passive device and making method thereof |
| CN101924101B (en) * | 2010-08-06 | 2013-09-11 | 锐迪科科技有限公司 | Structure of semiconductor passive device and making method thereof |
| CN109652770A (en) * | 2018-11-29 | 2019-04-19 | 天津大学 | Method for regulating vapor deposition metal film texture by using semiconductor substrate |
Also Published As
| Publication number | Publication date |
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| CN1146020C (en) | 2004-04-14 |
| WO2000001004A1 (en) | 2000-01-06 |
| JP2000021782A (en) | 2000-01-21 |
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