JP3994299B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method suitable for manufacturing an insulated gate field effect transistor using a single crystal silicon layer epitaxially grown on an insulating substrate as an active region.
[0002]
[Prior art]
Conventionally, a TFT (thin film transistor), which is a MOSFET (metal-oxide-semiconductor field effect transistor) using a single crystal silicon layer formed on a substrate, has an electron transfer several times larger than that using a polysilicon layer. And is known to be suitable for high-speed operation (Reference, RPZingg et al, “First MOS transistors on Insulator by Silicon Saturated Liquid Solution Epitaxy”. IEEE ELECTRON DEVICE LETTERS.VOL.13, NO. 5, MAY 1992, p294-6., Japanese Patent Publication No. 4-57098, Masayoshi Matsumura, "Thin Film Transistor" Applied Physics, Vol. 65, No. 8 (1996) pp 842-848).
[0003]
In such a semiconductor element, in order to form a single crystal silicon layer on a substrate, the following various film formation techniques (1) to (4) are known.
[0004]
(1) Using a single crystal silicon substrate as a seed, a silicon epitaxy layer is formed by cooling from an indium silicon solution or an indium gallium silicon solution heated to 920 to 930 ° C., and a silicon semiconductor is formed on this layer Create a layer. (Reference 1, Soo Hong Lee, “VERY-LOW-TEMPERATURE LIQUID-PHASE EPITAXIAL GROWTH OF SILICON”. MATERIALS LETTERS. Vol.9.No.2,3 (Jan., 1990) pp53-56. Reference2, R. Bergmann et al, "MOS transistors with epitaxial Si, laterally grown over SiO / Sub 2 / by liquid phase epitaxy." J. Applied Physics A, vol. A54, no. 1 p.103-5. Reference 3, RPZingg et al, "First MOS transistors on Insulator by Silicon Saturated Liquid Solution Epitaxy." IEEE ELECTRON DEVICE LETTERS.VOL.13, NO.5, MAY 1992 p294-6.)
[0005]
(2) Silicon is epitaxially grown on the sapphire substrate. (Reference 4, G.A.Garcia, R.E.Reedy, and M.L.Burger, "High-quality CMOS in thin (100 nm) silicon on sapphire," IEEE ELECTRON DEVICE LETTERS., VOL.9, pp32-34, Jan., 1988.)
[0006]
(3) A silicon layer is formed on the insulating substrate by oxygen ion implantation. (Reference 5, K. Izumi, M. Doken, and H. Ariyoshtl, "CMOS device fabrication on buried SiO₂layers formed by oxygen implantation into silicon, "Electron.Lett., vol.14, no.18, pp593-594, Aug.1978.)
[0007]
(4) A step is formed on a quartz substrate, a polysilicon layer is formed thereon, and this is then heated to 1400 ° C. or higher with a laser beam or a strip heater. The heated polysilicon layer forms an epitaxial growth layer with the step formed on the quartz substrate as a nucleus. (Reference 6, Shizujiro Furukawa, “Graphoepitaxy”, Journal of Electronic Communication Society, Vol. 66, No. 5, pp 486-489. (1983. May). Reference 7, Geis, MW, et al .: “Crystallographic orientation of silicon on an amorphous substrate using an artificial-relief grating and laser crystallization ", Appl. Phys. Letter, 35, 1, pp71-74 (July 1979). Reference 8, Geis, MW, et al .:" Silicon graphoepitaxy ", Jpn.J.Appl.Phys., Suppl.20-1, pp.39-42 (1981).)
[0007]
[Problems to be solved by the invention]
However, in the conventional techniques so far, there is no conventional technique that can form a silicon epitaxy layer on a large glass plate having a relatively low strain point. Further, silicon cannot be epitaxially grown at a low temperature and uniformly in a technique in which steps are formed on a glass plate and silicon is grown using this as a nucleus for epitaxial growth.
[0008]
The object of the present invention is to provide a method capable of epitaxially growing a silicon layer uniformly at a low temperature even in a large glass substrate having a relatively low strain point, and to produce a semiconductor element having a high current density at a high speed, and this method. It is to provide a semiconductor substrate and an element to be manufactured.
[0009]
[Means for Solving the Problems]
  The present invention
    Forming a step on the insulating substrate;
    On the insulating substrate including the step, a later-described material layer having a lattice match with single crystal silicon is provided.  Forming, and
    SaidPolysilicon or amorphous silicon layer is formed to a predetermined thickness on the material layerAfter  On the material layer and on or under the polysilicon or amorphous silicon layer,Later  ofForming a low melting point metal layer, orSaidContains silicon on the material layerSee below  Forming a low melting point metal layer;
    By heat treatment,Polysilicon or amorphous silicon layerThe low melting point metal  Dissolved in a layerOr silicon of the low melting point metal layer, the low melting point metalMelt ofA step of dissolving in
    Then by cooling process,Polysilicon or amorphous silicon layerSilicon  Or silicon of the low melting point metal layerThe step andEpitaxially growing the material layer as a seed to deposit a single crystal silicon layer;,
    A step of removing the low melting point metal layer remaining on the single crystal silicon layer;
For forming a single crystal silicon layerAssumingIs.
    The present invention also provides:
    Forming a later-described material layer having a good lattice match with single crystal silicon;
    Forming a step in the material layer;
    A polysilicon or amorphous silicon layer having a predetermined thickness is formed on the material layer including the step.  On the material layer and on the polysilicon or amorphous silicon layer.  Alternatively, below, a step of forming a low-melting point metal layer described later, or silicon on the material layer  A step of forming a low melting point metal layer, which will be described later, by sputtering or vacuum deposition;
    By heat treatment, the polysilicon or amorphous silicon layer is transformed into the low melting point metal.  Or the silicon of the low melting point metal layer is dissolved in the melt of the low melting point metal.  Process,
    Then, the silicon of the polysilicon or amorphous silicon layer is cooled.  Or using the silicon of the low melting point metal layer as an epitaxy using the step and the material layer as a seed.  And a step of depositing a single crystal silicon layer,
    A step of removing the low melting point metal layer remaining on the single crystal silicon layer;
The method for forming a single crystal silicon layer having the above is also assumed.
[0010]
  That isIn the present invention, the single crystal silicon layer is deposited.TheLater on thisRemain inRemoving the low melting point metal layer;In addition toApplying a predetermined treatment to the single crystal silicon layerForming a constituent layer of an insulated gate field effect transistor having the single crystal silicon layer existing inside the step as a channel region and having a source region and a drain region on both sides thereofProcessMoreA method for manufacturing a semiconductor deviceTheIt is to provide.
[0011]
  Semiconductor device manufactured by the method of the present inventionIsA step having a predetermined shape is formed at a predetermined position on the insulating substrate, and a later-described material layer having good lattice matching with single crystal silicon is formed on the insulating substrate including the step, and the field effect transistor is formed on the material layer. A semiconductor device in which a single crystal silicon layer constituting the substrate is formedMay be.
[0012]
  AlsoIn the method of the present inventionUsedSemiconductor substrate,as well asManufactured by that methodSemiconductor deviceIsIn particular, a later-described material layer having good lattice matching with single crystal silicon is formed on an insulating substrate, a step having a predetermined shape is formed on the material layer, and the field effect transistor is configured on the material layer including the step. Semiconductor substrate and semiconductor device on which a single crystal silicon layer is formedMay be.
[0013]
  According to the present invention, a material layer (for example, a sapphire layer) having good lattice matching with single crystal silicon.And stepsSince the silicon epitaxial layer is formed by the precipitation of single crystal silicon from the low melting point metal layer in which polysilicon or amorphous silicon is dissolved, using as a seed, the following remarkable (A) to (D) Advantageous effects can be obtained.
[0014]
(A) The above material layer, polysilicon or amorphous silicon layer can be formed by a method such as low pressure CVD (chemical vapor deposition: substrate temperature 500 to 600 ° C.), and the above low melting point metal layer is formed by a method such as sputtering. Furthermore, since the heat treatment temperature during the above-described silicon epitaxial growth can be 930 ° C. or less, a silicon single crystal film can be uniformly formed on an insulating substrate at a low temperature (eg, 920 to 930 ° C.). . In particular, since the above material layer such as a sapphire thin film is employed, the lattice matching with single crystal silicon is good (particularly due to the coincidence of lattice constant), and silicon epitaxy growth is facilitated.
[0015]
(B) Accordingly, a glass substrate or a ceramic substrate having a relatively low strain point can be easily obtained, a substrate with low cost and good physical properties can be used, and the size of the substrate can be increased. Therefore, the glass substrate can be formed into a wide and long roll shape, and a silicon single crystal thin film can be continuously formed.
[0016]
(C) Since the material layer such as a sapphire thin film becomes a diffusion barrier for various atoms, diffusion of impurities from the glass substrate can be suppressed.
[0017]
(D) The electron mobility of a silicon single crystal thin film formed on a glass substrate or the like at a low temperature is 540 cm.²/ V · sec (reference 3 mentioned above), which is as large as a silicon substrate, so it can be used for high-speed, high-current density top-gate, bottom-gate, and dual-gate LCDs (liquid crystal display devices). TFT, EL (electroluminescence element), FED (field emission display element) transistors, semiconductor elements such as high performance diodes, solar cells, capacitors, resistors, or electronic circuits in which these are integrated are made of glass. It can be created on a substrate or the like. In both the semiconductor substrate and the semiconductor device of the present invention, both the material layer and the step act as seeds during the growth of single crystal silicon and are structurally novel and useful for incorporating semiconductor elements.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
In the present invention, the material layer and the polysilicon or amorphous silicon layer are formed at a low temperature by a low pressure CVD method (substrate temperature of about 500 to 650 ° C.), a plasma CVD method, a sputtering method (substrate temperature of about 100 to 400 ° C.), or the like. The former is formed on the insulating substrate to a thickness of 5 to 200 nm, for example, and the latter is a thickness of several μm to 0.005 μm, for example, and the low-melting point metal layer is further several tens to several hundred times thicker than the polysilicon layer. It is preferable to perform the heat treatment after depositing by sputtering.
[0019]
  Also, a glass substrate is used as the insulating substrateCanThe material layer is made of a material selected from the group consisting of sapphire, spinel structure and calcium fluoride, and the low melting point metal layer is made of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum. It is formed with at least one selected from the above.
[0020]
In this case, when the low melting point metal layer is formed of metallic indium, the heat treatment is performed at 850 to 1100 ° C. (preferably 900 to 950 ° C.) in a hydrogen atmosphere to form an indium / silicon melt, and the low melting point metal is formed. When the layer is formed of metal indium gallium or gallium, the heat treatment is performed in a hydrogen atmosphere at 300 to 1100 ° C. (preferably 350 to 600 ° C.) or 400 to 1100 ° C. (preferably 420 to 600 ° C.). It can be a gallium-silicon melt or a gallium-silicon melt. In addition to a method of heating the entire substrate uniformly using an electric furnace, a lamp, or the like, the substrate can be heated by a method of locally heating only a predetermined place with an optical laser, an electron beam, or the like.
[0021]
As is apparent from the state diagram shown in FIG. 17, the melting point of the low melting point metal containing silicon is lowered according to the ratio of the low melting point metal. When indium is used, an indium melt layer containing silicon (for example, containing 1% by weight) is formed at a substrate temperature of 850 to 1100 ° C. Quartz plate glass can be used as the substrate up to about 1100 ° C. Up to 850 ° C., glass having lower heat resistance can be used. However, 850 ° C. to 600 ° C. is determined from the maximum use temperature (mostly the same as the strain point) of the aluminosilicate glass. Even when gallium is used, a gallium melt layer containing silicon (for example, containing 1% by weight) can be formed at a substrate temperature of 400 to 1100 ° C. for the same reason as described above.
[0022]
In either case, a glass substrate with a low strain point can be used as the substrate, so a large glass substrate (1 m²It is possible to form a semiconductor crystal layer on the above, but when the epitaxy temperature is as low as 350 to 600 ° C., glass having a low strain point of 470 to 670 ° C. should be used as the glass substrate. it can. This is inexpensive, can be easily made into a thin plate, and can produce a long rolled glass plate. By using this, a thin epitaxy layer can be continuously or discontinuously produced on a long rolled glass plate using the above method.
[0023]
After the single crystal silicon layer is deposited from the low melting point metal in which the silicon is dissolved by slow cooling using the material layer (and further the step) as a seed, the low melting point metal layer is deposited with hydrochloric acid or the like. The semiconductor element can be manufactured by dissolving and removing, and then subjecting the single crystal silicon layer to a predetermined treatment.
[0024]
As described above, the low melting point metal thin film such as metal indium deposited on the single crystal silicon layer after cooling is dissolved and removed using hydrochloric acid or the like.¹⁶(Atoms / cc and so on) can be made to remain, so that a P-type semiconductor is produced immediately after the production. This is therefore convenient for the fabrication of N-channel MOS transistors. However, since an N-type semiconductor crystal layer can be formed by ion-implanting an appropriate amount of N-type impurities such as phosphorus atoms, a P-channel MOS transistor can be formed. For this reason, a CMOS transistor can also be produced. Further, when the polysilicon or amorphous silicon layer is formed or when the low melting point metal layer is formed, a Group 3 or Group 5 impurity element (B, P, Sb, As, or the like) is mixed, thereby the single crystal. It is preferable to control the impurity species and / or the concentration of the silicon layer.
[0025]
As described above, the single crystal silicon layer epitaxially grown on the substrate is applied to the channel region, the source region, and the drain region of the insulated gate field effect transistor, and the impurity species and / or the concentration of each region can be controlled. it can.
[0026]
In the present invention, the material layer acts as a seed for single crystal silicon growth. In addition to this, a step having a predetermined shape to be a seed for the epitaxial growth is formed on the insulating substrate by dry etching such as reactive ion etching. When the material layer is formed on the insulating substrate including the step, the step also becomes the nucleus of the silicon epitaxy layer growth. Such a step may be formed in the material layer.
[0027]
Next, the present invention will be described in more detail with respect to preferred embodiments.
[0028]
  1 to 4,The present inventionThe embodiment ofFirst example to understandexplain.
[0029]
First, as shown in (1) of FIG. 1, a sapphire thin film (thickness 5 to 200 nm) 50 is formed on one main surface of a quartz glass substrate 1 (glass softening point of about 1000 ° C., thickness 50 microns to several mm). Form. The sapphire thin film 50 is formed by oxidizing and crystallizing trimethylaluminum gas with an oxidizing gas (oxygen / water) by a high-density plasma CVD method or a catalytic CVD method (see Japanese Patent Laid-Open No. 63-40314). To do.
[0030]
Next, as shown in FIG. 1B, the polysilicon film 5 is formed on the sapphire thin film 50 by a known low pressure CVD method (substrate temperature of about 500 to 650 ° C.) or plasma CVD method to several μm to 0.005 μm. It is deposited to a thickness (for example, 0.1 μm).
[0031]
Next, as shown in FIG. 1 (3), a metal indium film 6 is formed on the polysilicon film 5 by a thickness of several to several hundreds times the thickness of the polysilicon film 5 by sputtering or vacuum deposition (for example, 10 to 10 times). 15 μm).
[0032]
Next, the substrate 1 is held at 1000 ° C. or lower, particularly 920 to 930 ° C. for about 5 minutes under a hydrogen atmosphere. Thereby, the polysilicon 5 is dissolved in the melt of the metal indium 6.
[0033]
Next, by gradually cooling, the silicon dissolved in the metal indium is epitaxially grown as shown in FIG. 1 (4) using the sapphire thin film 50 as a seed, and a thickness of, for example, about 0.1 μm. A crystalline silicon layer 7 is deposited. In this case, since sapphire has almost the same lattice constant as single crystal silicon, for example, the (100) plane of silicon grows epitaxially on the sapphire thin film 50.
[0034]
Thus, after depositing the (100) plane single crystal silicon layer 7 on the substrate 1, the surface side metal indium 6 is dissolved and removed with hydrochloric acid or the like as shown in FIG. A MOS transistor (TFT) having a channel region 7 is manufactured.
[0035]
That is, as shown in FIG. 2 (6), a gate oxide film 8 having a thickness of 350 mm is formed on the surface of the single crystal silicon layer 7 by oxidation treatment (950 ° C.).
[0036]
Next, as shown in FIG. 2 (7), in order to control the impurity concentration of the channel region for the N-channel MOS transistor, the P-channel MOS transistor portion is masked with a photoresist 9, and P-type impurity ions (for example, B⁺) 10 for example 2.7 × 10 at 10 kV¹¹  atoms / cm²Then, the silicon layer 11 is formed by further implanting the conductivity type of the single crystal silicon layer 7 into P type.
[0037]
Next, as shown in FIG. 2 (8), in order to control the impurity concentration of the channel region for the P-channel MOS transistor, this time, the N-channel MOS transistor portion is masked with the photoresist 12, and N-type impurity ions (for example, P⁺) 13 for example 1 × 10 at 10 kV¹¹atoms / cm²The silicon layer 14 is formed by compensating the P-type of the single crystal silicon layer 7 by implanting with a dose amount of
[0038]
Next, as shown in FIG. 3 (9), a phosphorus-doped polysilicon layer 15 as a gate electrode material is deposited to a thickness of 4000 mm by, for example, a CVD method (620 ° C.).
[0039]
Next, as shown in FIG. 3 (10), a photoresist 16 is formed in a predetermined pattern, and using this as a mask, the polysilicon layer 15 is patterned into a gate electrode shape. Further, after removing the photoresist 16, FIG. For example, as shown in (11) of FIG.₂An oxide film 17 is formed on the surface of the gate polysilicon 15 by an oxidation process therein.
[0040]
Next, as shown in FIG. 3 (12), the P-channel MOS transistor portion is masked with a photoresist 18, and N-type impurities such as As⁺The ion 19 is 5 × 10 at 20 kV, for example.¹⁵atoms / cm²At a dose of 950 ° C. for 40 minutes, N₂N channel MOS transistor N by annealing in⁺A type source region 20 and a drain region 21 are formed.
[0041]
Next, as shown in FIG. 4 (13), the N-channel MOS transistor portion is masked with a photoresist 22, and P-type impurities such as B⁺For example, the ion 23 is 5 × 10 at 10 kV.¹⁵atoms / cm²Ion implantation at 900 ° C. for 5 minutes, N₂P channel MOS transistor P by annealing in⁺A type source region 24 and a drain region 25 are formed.
[0042]
Next, as shown in (14) of FIG.₂The film 26 is laminated to a thickness of 500 mm at, for example, 750 ° C., the SiN film 27 is laminated to a thickness of, for example, 2000 mm at 420 ° C., and the boron and phosphorus-doped silicate glass (BPSG) film 28 is reflowed as a reflow film, for example, 6000 mm The BPSG film 28 is formed, for example, at 900 ° C. with N₂Reflow in.
[0043]
Next, as shown in (15) of FIG. 4, a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is deposited on the entire surface including each hole to a thickness of 1 μm at 150 ° C. by sputtering or the like. Then, this is patterned to form the source or drain electrode 29 (S or D) and the gate extraction electrode or wiring 30 (G) of each of the P-channel MOSFET and N-channel MOSFET, thereby completing each MOS transistor.
[0044]
  As explained above,This exampleAccording to the above, the following remarkable effects can be obtained.
[0045]
(A) The silicon single crystal thin film 7 can be uniformly formed on the glass substrate 1 at a low temperature of 920 to 930 ° C.
[0046]
(B) Therefore, since a silicon single crystal thin film can be formed not only on a glass substrate but also on an insulating substrate such as a ceramic substrate, a substrate material having a low strain point, low cost and good physical properties can be arbitrarily selected. , Larger substrates (1m²And the like (100 m or more).
[0047]
(C) The sapphire thin film 50 acts as a barrier that suppresses the diffusion of atoms from the glass substrate 1 to the single crystal silicon layer 7.
[0048]
(D) The electron mobility of the silicon single crystal thin film 7 formed on the glass substrate or the like is 540 cm.²Since / v · sec, which is a large value equivalent to that of a silicon substrate, can be obtained, a transistor having a high current density can be formed at high speed. In addition to transistors, diodes, solar cells, capacitors, resistors, and the like, and electronic circuits in which these are integrated can be formed on a glass substrate. The process of forming a silicon semiconductor element such as a MOS transistor is almost the same as a conventionally known polysilicon TFT manufacturing process.
[0049]
  First mentioned aboveExampleIn FIG. 1, in order to control the conductivity type (or impurity concentration) of the single crystal silicon layer 7, an impurity supply gas is simultaneously fed during the polysilicon film formation shown in FIG.It is possibleThe
[0050]
  That is, when the polysilicon film 5 is formed, the solubility is high.TribeOr 5TribeElements such as B, P, Sb, As, etc.₂H₆And PH_ThreeIf the polysilicon film 5 is doped in an appropriate amount by supplying the polysilicon film 5 and the like, the P-type or N-type of the growing silicon epi layer 7 and the carrier concentration can be arbitrarily controlled.
[0051]
  5 to 6, the thirdExampleWill be explained.
[0052]
  This exampleThen, the above-mentioned firstExample1, the glass having a low strain point of about 670 ° C., for example, is used as the substrate 1 in the process shown in FIG. 1 (1), so that it is inexpensive and can be easily increased in size and thinned (for example, 50 μm thick). ) Can be rolled / lengthened, and such a glass plate is employed. Of course, a quartz substrate can also be employed.
[0053]
And after forming the sapphire thin film 50 like the above-mentioned, in the process shown in (2) of FIG. 1, well-known plasma CVD method, sputtering method (substrate temperature 100-400 degreeC), or well-known low-pressure CVD method (substrate temperature). The polysilicon film 5 (or amorphous silicon film) is deposited to a thickness of several μm to 0.005 μm (for example, 0.1 μm) by about 500 to 600 ° C.
[0054]
Next, in the step shown in FIG. 1 (3), a metal indium / gallium film (or metal gallium film) is deposited on the polysilicon film 5 by several tens to several hundred times of the polysilicon film 5 by sputtering or vacuum deposition. To a thickness (for example, 10 to 20 μm).
[0055]
Next, the substrate 1 is held at 350 to 600 ° C. for about 5 minutes in a hydrogen atmosphere. As a result, the polysilicon 5 (or amorphous silicon) is dissolved in the metal indium gallium melt or the metal gallium melt.
[0056]
Next, by gradually cooling, the silicon dissolved in the metal indium gallium (or metal gallium) is epitaxially grown with the sapphire thin film 50 as a seed as shown in FIG. For example, it is deposited as a single crystal silicon layer 7 of about 0.1 μm.
[0057]
Thus, after the single crystal silicon layer 7 is deposited on the substrate 1, the surface side metal indium gallium (or metal gallium) is dissolved and removed with hydrochloric acid or the like as shown in FIG. The layer 7 is patterned to produce a MOS transistor (TFT).
[0058]
That is, as shown in FIG. 5 (6), the surface of the single crystal silicon layer 7 is made of SiO 2 having a thickness of 2000 mm by plasma CVD at 400 ° C., for example.₂A gate insulating film composed of the film 40 and the SiN film 41 having a thickness of 500 mm is formed.
[0059]
Next, as shown in FIG. 5 (7), in order to control the impurity concentration of the channel region for the N-channel MOS transistor, P-type impurity ions (for example, B⁺) 10 for example 2.7 × 10 at 10 kV¹¹  atoms / cm²Then, the silicon layer 11 is formed by further implanting the conductivity type of the single crystal silicon layer 7 into P type.
[0060]
Next, as shown in FIG. 5 (8), a MoTa layer 42 (Mo 15%, Ta 85%) as a gate electrode material is deposited to a thickness of 5000 mm by, for example, a sputtering method.
[0061]
Next, as shown in FIG. 5 (9), a photoresist 43 is formed in a predetermined pattern, and the MoTa layer 42 is patterned into a gate electrode shape using this as a mask.
[0062]
Next, as shown in FIG. 6 (10), after removing the photoresist 43, for example, As type impurities such as As⁺The ion 19 is 5 × 10 at 20 kV, for example.¹⁵atoms / cm²N-type MOS transistor N is implanted by ion implantation at a dose of 10 ° C. and lamp annealed at 1000 ° C. for 10 seconds.⁺A type source region 44 and a drain region 45 are formed.
[0063]
Next, as shown in FIG. 6 (11), the entire surface is made of SiO by the CVD method.₂The film 46 is laminated to a thickness of 2000 mm, for example, and the phosphosilicate glass (PSG) film 47 is laminated to a thickness of 5000 mm, for example.
[0064]
Next, as shown in FIG. 6 (12), a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is deposited on the entire surface including each hole to a thickness of 1 μm at 150 ° C. by a sputtering method or the like. Then, this is patterned to form the respective source or drain electrode 48 (S or D) and gate extraction electrode 49 (G) of the N-channel MOSFET, thereby completing each N-channel MOS transistor.
[0065]
  As explained above,This exampleAccording to the above, the following remarkable effects can be obtained.
[0066]
(A) The silicon single crystal thin film 7 can be uniformly formed on the glass substrate 1 at a temperature as low as 350 to 600 ° C.
[0067]
(B) Therefore, since a silicon single crystal thin film can be formed not only on a low strain point glass substrate but also on an insulating substrate such as a ceramic substrate or an organic substrate, a substrate material having a low strain point, low cost and good physical properties can be obtained. It can be selected arbitrarily, and the substrate can be enlarged (1m²Above) and lengthening (100 m or more) is also possible. Glass substrates and organic substrates can be made at a lower cost than quartz substrates, and can be made thinner / longer / rolled. Large-sized glass substrates and the like can be manufactured with high productivity and at low cost.
[0068]
(C) When glass having a low strain point (for example, 670 ° C.) is used as the glass substrate, the constituent elements may diffuse from the glass into the upper layer, which may affect the transistor characteristics. Can be effectively prevented because it becomes a barrier.
[0069]
(D) The electron mobility of the silicon single crystal thin film 7 formed on the glass substrate or the like is 540 cm.²Since / v · sec, which is a large value equivalent to that of a silicon substrate, can be obtained, a transistor having a high current density can be formed at high speed. In addition to transistors, diodes, solar cells, capacitors, resistors, and the like, and electronic circuits in which these are integrated can be formed on a glass substrate. The process of forming a silicon semiconductor element such as a MOS transistor is almost the same as a conventionally known polysilicon TFT manufacturing process.
[0070]
  <No.1Embodiment>
  About FIGS.Of the present inventionFirst1The embodiment will be described.
[0071]
First, as shown in (1) of FIG. 7, a photoresist 2 is formed in a predetermined pattern on one main surface of the quartz glass substrate 1, and this is used as a mask, for example, CF_FourF of plasma⁺Irradiation with ions 3 and a plurality of steps 4 are formed on the substrate 1 by reactive ion etching (RIE). In this case, the step 4 serves as a seed for epitaxial growth of single crystal silicon, which will be described later, and may have a depth d of 0.1 μm and a width w of 1.5 to 1.9 μm.
[0072]
  Next, as shown in FIG. 7B, after the removal of the photoresist 2,ExampleIn the same manner as described above, a sapphire thin film 50 is deposited to a thickness of 5 to 200 nm on the entire surface including the step 4 by a known low-pressure CVD method (substrate temperature of about 500 to 650 ° C.) or plasma CVD method, and further ( As shown in 3), the polysilicon film 5 is deposited to a thickness of several μm to 0.005 μm (for example, 0.1 μm).
[0073]
Next, as shown in FIG. 7 (4), a metal indium film 6 is formed on the polysilicon film 5 by a thickness of several tens to several hundred times that of the polysilicon film 5 by sputtering or vacuum deposition (for example, 10 to 10 times). 15 μm).
[0074]
Next, the substrate 1 is held at 1000 ° C. or lower, particularly 920 to 930 ° C. for about 5 minutes under a hydrogen atmosphere. Thereby, the polysilicon 5 is dissolved in the melt of the metal indium 6.
[0075]
Next, by gradually cooling, the silicon dissolved in the metal indium is epitaxially grown as shown in FIG. 8 (5) using the sapphire thin film 50 as a seed, and a thickness of about 0.1 μm, for example, is formed. A crystalline silicon layer 7 is deposited.
[0076]
  In this case, the single crystal silicon layer 7 has the above-described first structure.ExampleAs described above, the (100) plane is epitaxially grown on the sapphire thin film 50. This is further promoted by the step 4. The step 4 becomes the nucleus of epitaxy layer growth, which is due to a known phenomenon called graphoepitaxy (see the above-mentioned documents 6, 7, and 8). As shown in FIG. 11, when a vertical wall such as the step 4 is formed on the amorphous substrate (glass) 1 and an epitaxy layer is formed thereon, a random wall as shown in FIG. As shown in FIG. 11B, the (100) plane grows along the surface of the step 4 in the plane orientation. The size of the single crystal grains increases in proportion to the temperature and time. However, when the temperature and time are reduced and shortened, the interval between the steps must be shortened.
[0077]
In this way, in addition to lattice matching of the sapphire thin film 50, after depositing the single crystal silicon layer 7 on the substrate 1 by graphoepitaxy, the metal indium 6 on the surface side is removed by hydrochloric acid or the like as shown in FIG. 8 (6). By dissolving and removing, a MOS transistor (TFT) using the single crystal silicon layer 7 as a channel region is manufactured.
[0078]
That is, as shown in FIG. 8 (7), the gate oxide film 8 having a thickness of 350 mm is formed on the surface of the single crystal silicon layer 7 by oxidation treatment (950 ° C.).
[0079]
Next, as shown in FIG. 8 (8), in order to control the impurity concentration of the channel region for the N-channel MOS transistor, the P-channel MOS transistor portion is masked with a photoresist 9, and P-type impurity ions (for example, B⁺) 10 for example 2.7 × 10 at 10 kV¹¹  atoms / cm²Then, the silicon layer 11 is formed by further implanting the conductivity type of the single crystal silicon layer 7 into P type.
[0080]
Next, as shown in FIG. 9 (9), in order to control the impurity concentration of the channel region for the P-channel MOS transistor, this time, the N-channel MOS transistor portion is masked with the photoresist 12, and N-type impurity ions (for example, P⁺) 13 for example 1 × 10 at 10 kV¹¹atoms / cm²The silicon layer 14 is formed by compensating the P-type of the single crystal silicon layer 7 by implanting with a dose amount of
[0081]
Next, as shown in FIG. 9 (10), a phosphorus-doped polysilicon layer 15 as a gate electrode material is deposited to a thickness of 4000 mm by, for example, a CVD method (620 ° C.).
[0082]
Next, as shown in FIG. 9 (11), a photoresist 16 is formed in a predetermined pattern, and using this as a mask, the polysilicon layer 15 is patterned into a gate electrode shape. Further, after removing the photoresist 16, FIG. For example, as shown in (12) of FIG.₂An oxide film 17 is formed on the surface of the gate polysilicon 15 by an oxidation process therein.
[0083]
Next, as shown in FIG. 10 (13), the P-channel MOS transistor portion is masked with a photoresist 18, and N-type impurities such as As⁺The ion 19 is 5 × 10 at 20 kV, for example.¹⁵atoms / cm²At a dose of 950 ° C. for 40 minutes, N₂N channel MOS transistor N by annealing in⁺A type source region 20 and a drain region 21 are formed.
[0084]
Next, as shown in FIG. 10 (14), the N-channel MOS transistor portion is masked with a photoresist 22, and P-type impurities such as B⁺For example, the ion 23 is 5 × 10 at 10 kV.¹⁵atoms / cm²Ion implantation at 900 ° C. for 5 minutes, N₂P channel MOS transistor P by annealing in⁺A type source region 24 and a drain region 25 are formed.
[0085]
Next, as shown in FIG. 10 (15), the entire surface is made of SiO by the CVD method.₂The film 26 is laminated to a thickness of 500 mm at, for example, 750 ° C., the SiN film 27 is laminated to a thickness of, for example, 2000 mm at 420 ° C., and the boron and phosphorus-doped silicate glass (BPSG) film 28 is reflowed as a reflow film, for example, 6000 mm The BPSG film 28 is formed, for example, at 900 ° C. with N₂Reflow in.
[0086]
Next, as shown in FIG. 10 (16), a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is deposited on the entire surface including each hole to a thickness of 1 μm at 150 ° C. by sputtering or the like. Then, this is patterned to form the source or drain electrode 29 (S or D) and the gate extraction electrode or wiring 30 (G) of each of the P-channel MOSFET and N-channel MOSFET, thereby completing each MOS transistor.
[0087]
  As described above, according to the present embodiment, the first step described above is caused by the step 4.ExampleAs a result, it is possible to further improve the remarkable effect of the above-described, and to obtain an effect that the epitaxial growth of single crystal silicon can be satisfactorily performed.
[0088]
  <No.2Embodiment>
  About FIGS.Of the present inventionFirst2The embodiment will be described.
[0089]
  In the present embodiment, the above-mentioned first1Compared to the first embodiment, in the step shown in FIG. 7A, glass having a low strain point of about 670 ° C., for example, is used as the substrate 1, so that it is inexpensive and easy to increase in size and is made thin ( For example, if the thickness is 50 μm, it is possible to roll / elongate, and such a glass plate is adopted. Of course, a quartz substrate can also be employed.
[0090]
And after forming the level | step difference 4 similarly to the above-mentioned, in the process shown to (2) and (3) of FIG. 7, well-known plasma CVD method, sputtering method (substrate temperature 100-400 degreeC), or well-known low-pressure CVD method (Substrate temperature of about 500 to 600 ° C.), the sapphire thin film 50 and the polysilicon film 5 (or amorphous silicon film) are formed on the entire surface including the step 4 in the former 5 to 200 nm, and the latter in the range of several μm to 0.005 μm (for example, 0. 1 μm).
[0091]
Next, in the step shown in FIG. 7 (4), a metal indium / gallium film (or metal gallium film) is deposited on the polysilicon film 5 by several tens to several hundred times of the polysilicon film 5 by sputtering or vacuum deposition. To a thickness (for example, 10 to 20 μm).
[0092]
Next, the substrate 1 is held at 350 to 600 ° C. for about 5 minutes in a hydrogen atmosphere. As a result, the polysilicon 5 (or amorphous silicon) is dissolved in the metal indium gallium melt or the metal gallium melt.
[0093]
Next, by gradually cooling, the silicon dissolved in metal indium gallium (or metal gallium) is formed as shown in FIG. 8 (5) using the sapphire thin film 50 and the step 4 as a seed. Epitaxially grown and deposited as a single crystal silicon layer 7 having a thickness of, for example, about 0.1 μm.
[0094]
In this case, the single crystal silicon layer 7 has a (100) plane epitaxially grown on the substrate as described above.
[0095]
After the single crystal silicon layer 7 is thus deposited on the substrate 1, the surface side metal indium gallium (or metal gallium) is dissolved and removed with hydrochloric acid or the like as shown in FIG. The layer 7 is patterned to produce a MOS transistor (TFT).
[0096]
That is, as shown in FIG. 13 (7), the surface of the single crystal silicon layer 7 is made of SiO 2 having a thickness of 2000 mm by plasma CVD at 400 ° C.₂A gate insulating film composed of the film 40 and the SiN film 41 having a thickness of 500 mm is formed.
[0097]
Next, as shown in FIG. 13 (8), in order to control the impurity concentration of the channel region for the N channel MOS transistor, P type impurity ions (for example, B⁺) 10 for example 2.7 × 10 at 10 kV¹¹  atoms / cm²Then, the silicon layer 11 is formed by further implanting the conductivity type of the single crystal silicon layer 7 into P type.
[0098]
Next, as shown in FIG. 13 (9), a MoTa layer 42 (Mo 15%, Ta 85%) as a gate electrode material is deposited to a thickness of 5000 mm by sputtering, for example.
[0099]
Next, as shown in (10) of FIG. 13, a photoresist 43 is formed in a predetermined pattern, and the MoTa layer 42 is patterned into a gate electrode shape using this as a mask.
[0100]
Next, as shown in FIG. 14 (11), after removing the photoresist 43, for example, As type impurities such as As⁺The ion 19 is 5 × 10 at 20 kV, for example.¹⁵atoms / cm²N-type MOS transistor N is implanted by ion implantation at a dose of 10 ° C. and lamp annealed at 1000 ° C. for 10 seconds.⁺A type source region 44 and a drain region 45 are formed.
[0101]
Next, as shown in FIG. 14 (12), the entire surface is SiO 2 by CVD.₂The film 46 is laminated to a thickness of 2000 mm, for example, and the phosphosilicate glass (PSG) film 47 is laminated to a thickness of 5000 mm, for example.
[0102]
Next, as shown in FIG. 14 (13), a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum is deposited on the entire surface including each hole to a thickness of 1 μm at 150 ° C. by sputtering or the like. Then, this is patterned to form each source or drain electrode 48 (S or D) and gate extraction electrode 49 (G) of the N channel MOSFET, thereby completing each N channel MOS transistor.
[0103]
  As described above, according to the present embodiment, the third step described above is caused by the step 4.ExampleIt is possible to further improve the remarkable effect of the above, and to favorably perform epitaxial growth of single crystal silicon.
[0104]
  FIG.4ofExampleIs shown.
[0105]
  This exampleThen, the above-mentioned firstExample1, after the step (1) in FIG. 1, for example, an indium film 6 is formed on the sapphire film 50 to a thickness of, for example, 10 to 20 μm by sputtering or vacuum deposition as shown in FIG. 15 (2). To do.
[0106]
Next, as shown in FIG. 15 (3), an amorphous silicon film 5 is deposited on the indium film 6 to a thickness of several μm to 0.005 μm (for example, 0.1 μm) by a known plasma CVD method.
[0107]
In this case, the formation temperature of the silicon film should not greatly exceed the melting point of the low melting point metal 6 (melting point 156 ° C. for indium and melting point 29.77 ° C. for gallium). (600-650 ° C.) is difficult. Therefore, the amorphous silicon film 5 is formed on the indium film 6 by plasma CVD.
[0108]
Next, the substrate 1 is held at 1000 ° C. or lower (particularly 920 to 930 ° C.) for about 5 minutes in a hydrogen atmosphere. As a result, the amorphous silicon 5 is dissolved in the melt of metallic indium.
[0109]
Next, by gradually cooling, the silicon dissolved in the metal indium is epitaxially grown using the sapphire film 50 as a seed as shown in FIG. 15 (4), and has a thickness of, for example, about 0.1 μm. Deposit as layer 7.
[0110]
In this case, the single crystal silicon layer 7 has a (100) plane epitaxially grown on the substrate as described above.
[0111]
Thus, after the single crystal silicon layer 7 is deposited on the substrate 1 by epitaxy, the metal indium on the surface side is dissolved and removed with hydrochloric acid or the like as described above, and the single crystal silicon layer 7 is patterned to form a MOS transistor (TFT). ).
[0112]
  This exampleThen, after the low melting point metal layer 6 is formed on the sapphire film 50 and the amorphous silicon layer 5 is formed thereon, heat melting and cooling are performed. This occurs in the same manner as the above-described embodiment.
[0113]
  FIG.5ofExampleIs shown.
[0114]
  This exampleThen, the above-mentioned firstExampleCompared to FIG. 1, after the step (1) in FIG. 1, for example, an indium film 6A containing a predetermined amount (for example, about 1 wt%) of silicon is sputtered on the sapphire film 50 as shown in FIG. 16 (2). For example, it forms in thickness of 10-20 micrometers by the vacuum evaporation method.
[0115]
Next, the substrate 1 is held at 1000 ° C. or lower (particularly 920 to 930 ° C.) for about 5 minutes in a hydrogen atmosphere. As a result, the silicon is dissolved in a melt of metallic indium.
[0116]
Next, by gradually cooling, the silicon dissolved in the metal indium is epitaxially grown as shown in FIG. 16 (3) using the sapphire film 50 as a seed, and a single crystal silicon having a thickness of about 0.1 μm, for example. Deposit as layer 7.
[0117]
In this case, the single crystal silicon layer 7 has a (100) plane epitaxially grown on the substrate as described above.
[0118]
Thus, after the single crystal silicon layer 7 is deposited on the substrate 1 by epitaxy, the metal indium on the surface side is dissolved and removed with hydrochloric acid or the like as described above, and the single crystal silicon layer 7 is patterned to form a MOS transistor (TFT). ).
[0119]
  This exampleThen, after forming the low-melting-point metal layer 6A containing silicon on the sapphire film 50, heat melting and cooling are performed, but the epitaxial growth of silicon from the melt of the low-melting-point metal has been described in the above-described embodiment. Occurs as well.
[0120]
The embodiment of the present invention described above can be variously modified based on the technical idea of the present invention.
[0121]
For example, sapphire (Al₂O_Three) Instead of single crystal silicon, a spinel structure having good lattice matching (for example, magnesia spinel) (MgO.Al₂O_Three)) Or calcium fluoride (CaF)₂) Etc. can be used.
[0122]
  Further, the step 4 described above can be formed not only on the substrate 1 but also on the sapphire film or the sapphire substrate itself having a thickness indicated by a virtual line in FIG. Further, the crystal orientation of the growth layer can be controlled by variously changing the shape of the step as shown in FIGS. When creating a MOS transistor, the (100) plane is most often used. Further, the step 4 has the above-described first.4And the second5ofExampleHowever, it may be formed.
[0123]
  The third mentioned aboveExample, first and secondAlso in the embodiment of the secondExampleSimilarly to 3 when forming polysilicon or amorphous siliconTribeOr 5TribeIt is also possible to dope the impurities.
[0124]
[Effects of the invention]
  According to the present invention, a material layer having a good lattice match with single crystal siliconAnd stepsSince the silicon epitaxial layer is formed by the deposition of single crystal silicon from the low melting point metal layer in which polysilicon or amorphous silicon is dissolved using the seed as a seed, the above material layer, polysilicon or amorphous silicon layer, low melting point metal layer Can be formed at a low temperature. Furthermore, since the heat treatment temperature during the above-described silicon epitaxial growth may be low, a silicon single crystal film can be uniformly formed on the insulating substrate at a low temperature.
[0125]
Accordingly, it is possible to use a substrate having a relatively low strain point such as a glass substrate or a ceramic substrate, which can be easily obtained at low cost and has good physical properties, and can be increased in size. Since the layer becomes a diffusion barrier of various atoms, diffusion of impurities from the glass substrate can be suppressed. The electron mobility of the silicon single crystal thin film is 540 cm.²/ V · sec, which is as large as a silicon substrate, so high-speed, high-current density transistors, high-performance diodes, solar cells, capacitors, resistors, and other semiconductor elements, or these are integrated. Electronic circuits can be created on glass substrates and the like.
[Brief description of the drawings]
FIG. 1 shows an embodiment of the present invention.First example to understandFIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the order of steps.
[Figure 2]same,It is sectional drawing which shows the manufacturing process of a semiconductor device in order of a process.
[Fig. 3]same,It is sectional drawing which shows the manufacturing process of a semiconductor device in order of a process.
[Fig. 4]same,It is sectional drawing which shows the manufacturing process of a semiconductor device in order of a process.
FIG. 5 shows an embodiment of the present invention.Second example to understandFIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the order of steps.
[Fig. 6]same,It is sectional drawing which shows the manufacturing process of a semiconductor device in order of a process.
FIG. 7 shows the first of the present invention.1It is sectional drawing which shows the manufacturing process of the semiconductor device by embodiment of this to process order.
[Fig. 8]same,It is sectional drawing which shows the manufacturing process of a semiconductor device in order of a process.
FIG. 9same,It is sectional drawing which shows the manufacturing process of a semiconductor device in order of a process.
FIG. 10same,It is sectional drawing which shows the manufacturing process of a semiconductor device in order of a process.
FIG. 11 is a schematic perspective view for explaining a situation of silicon crystal growth on an amorphous substrate.
FIG. 12 is a schematic cross-sectional view showing various step shapes and silicon growth crystal orientations in the graphoepitaxy technique.
FIG. 13 shows the first of the present invention.2It is sectional drawing which shows the manufacturing process of the semiconductor device by embodiment of this to process order.
FIG. 14same,It is sectional drawing which shows the manufacturing process of a semiconductor device in order of a process.
FIG. 15 shows an embodiment of the present invention.4th example to understandFIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the order of steps.
FIG. 16 shows an embodiment of the present invention.5th example to understandFIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the order of steps.
FIG. 17 is a Si—In phase diagram (A) and a Si—Ga phase diagram (B).
[Explanation of symbols]
1 ... Glass (or quartz) substrate, 4 ... Step,
5 ... polysilicon (or amorphous silicon) film, 6 ... metal indium film,
7 ... single crystal silicon layer, 8 ... gate oxide film, 10, 23 ... P-type impurity ions,
11 ... P-type impurity implantation layer, 13, 19 ... N-type impurity ions,
14 ... N-type impurity implantation layer, 15, 42 ... Gate electrode (material), 17 ... Oxide film,
20, 21, 44, 45 ... N⁺Type source or drain region,
24, 25 ... P⁺Type source or drain region,
26, 27, 28, 40, 41, 46, 47 ... insulating film,
29, 30, 48, 49 ... electrode or wiring, 50 ... sapphire thin film

Claims (13)

Forming a step in the insulating substrate;
Forming a material layer made of a material selected from the group consisting of sapphire, a spinel structure, and calcium fluoride on the insulating substrate including the step;
Forming a polysilicon or amorphous silicon layer on the material layer to a predetermined thickness;
A low melting point made of at least one selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum on the material layer and on or under the polysilicon or amorphous silicon layer. Forming a metal layer;
Dissolving the polysilicon or amorphous silicon layer in the low melting point metal layer by heat treatment;
Next, a step of epitaxially growing silicon of the polysilicon or amorphous silicon layer by the cooling process using the step and the material layer as a seed to deposit a single crystal silicon layer;
Removing the low melting point metal layer remaining thereon after deposition of the single crystal silicon layer;
Thereafter, the single crystal silicon layer is subjected to a predetermined treatment, the single crystal silicon layer existing inside the step is used as a channel region, and an insulated gate field effect transistor having a source region and a drain region on both sides of the channel region. And a step of forming a layer. Forming a material layer made of a material selected from the group consisting of sapphire, spinel structure and calcium fluoride;
Forming a step in the material layer;
Forming a polysilicon or amorphous silicon layer on the material layer including the step to a predetermined thickness;
A low melting point made of at least one selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum on the material layer and on or under the polysilicon or amorphous silicon layer. Forming a metal layer;
Dissolving the polysilicon or amorphous silicon layer in the low melting point metal layer by heat treatment;
Next, a step of epitaxially growing silicon of the polysilicon or amorphous silicon layer by the cooling process using the step and the material layer as a seed to deposit a single crystal silicon layer;
Removing the low melting point metal layer remaining thereon after deposition of the single crystal silicon layer;
Thereafter, the single crystal silicon layer is subjected to a predetermined treatment, the single crystal silicon layer existing inside the step is used as a channel region, and an insulated gate field effect transistor having a source region and a drain region on both sides of the channel region. And a step of forming a layer.   3. The method for manufacturing a semiconductor device according to claim 1, wherein the group 3 or group 5 impurity species and / or the concentration thereof are controlled in each of the channel region, the source region, and the drain region.   The step is formed by dry etching, and the material layer and the polysilicon or amorphous silicon layer are formed by a low pressure CVD (chemical vapor deposition) method, a plasma CVD method, or a sputtering method, and on the polysilicon or amorphous silicon layer Alternatively, the semiconductor device manufacturing method according to claim 1, wherein the low-melting-point metal layer is deposited below and the heat treatment is performed.   The method for manufacturing a semiconductor device according to claim 1, wherein a glass substrate is used as an insulating substrate on which the material layer is formed.   When the low melting point metal layer is formed of indium, the heat treatment is performed at 850 to 1100 ° C. in a hydrogen atmosphere. When the low melting point metal layer is formed of indium gallium or gallium, the heat treatment is performed under a hydrogen atmosphere, 300 The manufacturing method of the semiconductor device of Claim 1 or 2 performed at -1100 degreeC or 400-1100 degreeC.   3. The impurity species and / or concentration of the single crystal silicon layer is controlled by mixing a Group 3 or Group 5 impurity element when forming the polysilicon or amorphous silicon layer, thereby controlling the impurity species and / or the concentration of the single crystal silicon layer. A method for manufacturing a semiconductor device. Forming a step in the insulating substrate;
Forming a material layer made of a material selected from the group consisting of sapphire, a spinel structure, and calcium fluoride on the insulating substrate including the step;
On the material layer, a low melting point metal layer containing silicon and made of at least one selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum is formed by sputtering or vacuum deposition. Forming, and
Melting the low melting point metal by heat treatment, and dissolving the silicon in the melt;
Next, a step of epitaxially growing the silicon by the cooling process using the step and the material layer as a seed to deposit a single crystal silicon layer;
Removing the low melting point metal layer remaining thereon after deposition of the single crystal silicon layer;
Thereafter, the single crystal silicon layer is subjected to a predetermined treatment, the single crystal silicon layer existing inside the step is used as a channel region, and an insulated gate field effect transistor having a source region and a drain region on both sides of the channel region. And a step of forming a layer. Forming a material layer made of a material selected from the group consisting of sapphire, spinel structure and calcium fluoride;
Forming a step in the material layer;
A low melting point metal layer containing at least one selected from the group consisting of indium, gallium, tin, bismuth, lead, zinc, antimony and aluminum is sputtered on the material layer including the step. Forming by a method or a vacuum deposition method;
Melting the low melting point metal by heat treatment, and dissolving the silicon in the melt;
Next, a step of epitaxially growing the silicon by the cooling process using the step and the material layer as a seed to deposit a single crystal silicon layer;
Removing the low melting point metal layer remaining thereon after deposition of the single crystal silicon layer;
Thereafter, the single crystal silicon layer is subjected to a predetermined treatment, the single crystal silicon layer existing inside the step is used as a channel region, and an insulated gate field effect transistor having a source region and a drain region on both sides of the channel region. And a step of forming a layer.   10. The method according to claim 8, wherein the step is formed by dry etching, the material layer is formed by a low pressure CVD method, a plasma CVD method, or a sputtering method, the low melting point metal layer is deposited, and the heat treatment is performed. A method for manufacturing a semiconductor device.   The method for manufacturing a semiconductor device according to claim 8, wherein a glass substrate is used as an insulating substrate on which the material layer is formed.   When the low melting point metal layer is formed of indium, the heat treatment is performed in a hydrogen atmosphere at 850 to 1100 ° C., and when the low melting point metal layer is formed of indium gallium or gallium, the heat treatment is performed in a hydrogen atmosphere, 300 The manufacturing method of the semiconductor device according to claim 8 or 9 performed at -1100 ° C or 400-1100 ° C.   10. The semiconductor device according to claim 8, wherein an impurity element of Group 3 or Group 5 is mixed during film formation of the low melting point metal layer, thereby controlling an impurity species and / or concentration of the single crystal silicon layer. Manufacturing method.

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