JPH0691109B2 - Method for manufacturing field effect transistor - Google Patents
Method for manufacturing field effect transistorInfo
- Publication number
- JPH0691109B2 JPH0691109B2 JP21675285A JP21675285A JPH0691109B2 JP H0691109 B2 JPH0691109 B2 JP H0691109B2 JP 21675285 A JP21675285 A JP 21675285A JP 21675285 A JP21675285 A JP 21675285A JP H0691109 B2 JPH0691109 B2 JP H0691109B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- field effect
- effect transistor
- thin film
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 230000005669 field effect Effects 0.000 title claims description 12
- 238000000034 method Methods 0.000 title description 10
- 239000007790 solid phase Substances 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- 239000012535 impurity Substances 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 9
- 230000004913 activation Effects 0.000 claims description 5
- 239000012212 insulator Substances 0.000 claims description 2
- 238000002513 implantation Methods 0.000 claims 1
- 239000010409 thin film Substances 0.000 description 19
- 239000010410 layer Substances 0.000 description 18
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- -1 silicon ions Chemical class 0.000 description 12
- 239000013078 crystal Substances 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 239000011521 glass Substances 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 239000010408 film Substances 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 238000002844 melting Methods 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 239000003513 alkali Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000006911 nucleation Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電界効果型トランジスタ特に薄膜トランジス
タの製造方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a field effect transistor, particularly a thin film transistor.
本発明は、薄膜トランジスタの製法において、非晶質又
は多結晶半導体層のチャンネル領域に不活性イオンを注
入した後、熱処理して固相成長させ、次いでゲート電極
とセルフアラインでソース及びドレイン領域に不純物を
注入し、熱処理して活性化することにより、移動度μの
向上を図ると共に、固相成長及び不純物の活性化の時間
を短縮するようにしたものである。The present invention relates to a method of manufacturing a thin film transistor, in which inert ions are implanted into a channel region of an amorphous or polycrystalline semiconductor layer, followed by heat treatment for solid phase growth, and then self-alignment with a gate electrode to form impurities in the source and drain regions. Is implanted and heat-treated for activation to improve the mobility μ and to shorten the time for solid phase growth and activation of impurities.
一般に薄膜トランジスタは、石英ガラス等の絶縁基体上
にシリコン等の半導体薄膜を被着形成し、この半導体薄
膜にチャンネル領域、ソース領域及びドレイン領域を形
成して電界効果型トランジスタ(FET)を構成するよう
にしている。このような薄膜トランジスタとして、チャ
ンネル領域の半導体薄膜の膜厚を100Å〜800Åと薄くし
て特性向上を図った超薄膜トランジスタが提案されてい
る(特開昭60-136262号)。Generally, a thin film transistor is formed by depositing a semiconductor thin film such as silicon on an insulating substrate such as quartz glass, and forming a channel region, a source region and a drain region in the semiconductor thin film to form a field effect transistor (FET). I have to. As such a thin film transistor, a super thin film transistor has been proposed in which the semiconductor thin film in the channel region is thinned to 100 Å to 800 Å to improve the characteristics (JP-A-60-136262).
また、薄膜トランジスタの基板としては、高融点の石英
ガラスが一般に用いられているが、高価格となるため、
安価な低融点ガラス(例えば無アルカリガラス)を基板
に用いることが望まれている。このような比較的低融点
のガラスを基板に用いる場合には薄膜トランジスタの製
造工程中の温度を650℃以下とするような低温プロセス
が必要となる。Further, as the substrate of the thin film transistor, quartz glass having a high melting point is generally used, but since it is expensive,
It is desired to use an inexpensive low melting point glass (for example, non-alkali glass) for the substrate. When such a glass having a relatively low melting point is used as a substrate, a low temperature process is required so that the temperature during the manufacturing process of the thin film transistor is 650 ° C. or lower.
第1図は従来の薄膜トランジスタの製法の一例を示す。FIG. 1 shows an example of a conventional method for manufacturing a thin film transistor.
先ず、第2図Aに示すように低融点ガラス基板(1)の
一面上に例えば多結晶シリコンの薄膜シリコン層(2)
を被着形成して後、薄膜シリコン層(2)を島領域化し
(所定領域を残して他をエッチング除去する)、次いで
この薄膜シリコン層(2)にシリコンイオンSi+(3)
をイオン注入して(ドーズ量は例えば1.5×1015/cm2)
非晶質化する。なお、島領域化とSi+のイオン注入はど
ちらが先でもよい。First, as shown in FIG. 2A, a thin film silicon layer (2) of, for example, polycrystalline silicon is formed on one surface of a low melting point glass substrate (1).
Then, the thin film silicon layer (2) is formed into island regions (leaving a predetermined region to remove the others), and then silicon ions Si + (3) are added to the thin film silicon layer (2).
Ion implantation (dose amount is 1.5 × 10 15 / cm 2 )
Amorphize. Either island formation or Si + ion implantation may be performed first.
次に、600℃、15時間の熱処理を行って固相成長させる
(第2図B参照)。Next, heat treatment is performed at 600 ° C. for 15 hours for solid phase growth (see FIG. 2B).
次に、第2図Cに示すように薄膜シリコン層(2)上に
例えばSiO2等よりなるゲート絶縁膜(4)及び多結晶シ
リコンのゲート電極(5)を被着形成する。次いでゲー
ト電極(5)をマスクにソース領域(6)及びドレイン
領域(7)に、nチャンネルFETであればn形不純物例
えばリンイオン(P+)(8)をイオン注入する。このと
き多結晶シリコンのゲート電極(5)にもリンイオンが
注入され低抵抗となる。Next, as shown in FIG. 2C, a gate insulating film (4) made of, for example, SiO 2 and a gate electrode (5) of polycrystalline silicon are deposited on the thin film silicon layer (2). Next, using the gate electrode (5) as a mask, an n-type impurity such as phosphorus ion (P + ) (8) is ion-implanted into the source region (6) and the drain region (7). At this time, phosphorus ions are also implanted into the gate electrode (5) of polycrystalline silicon, resulting in low resistance.
次に、600℃、7〜8時間の熱処理を行ってソース領域
(6)及びドレイン領域(7)の活性化を行う(第2図
D参照)。Next, heat treatment is performed at 600 ° C. for 7 to 8 hours to activate the source region (6) and the drain region (7) (see FIG. 2D).
しかる後、CVD(化学気相成長)法によるSiO2の層間絶
縁層(9)を被着形成して後、コンタクト窓孔を形成
し、Alによるソース電極(10)及びドレイン電極(11)
を形成して薄膜トランジスタ(12)を得る。Then, a SiO 2 interlayer insulating layer (9) is deposited by CVD (Chemical Vapor Deposition) method, and then a contact window hole is formed, and a source electrode (10) and a drain electrode (11) made of Al are formed.
To obtain a thin film transistor (12).
上述した従来の製法においては、第2図Aの工程でシリ
コンイオン(Si+)のドーズ量が多い程、その後の熱処
理での結晶粒成長が大きくなり、移動度μが上がる。し
かし、ドーズ量を多くした場合には結晶粒成長時間が長
くかかるという問題点があった。例えばSi+のドーズ量
が2×1015cm-2であると、成長時間は30時間以上かか
る。In the conventional manufacturing method described above, the larger the dose of silicon ions (Si + ) in the step of FIG. 2A, the larger the crystal grain growth in the subsequent heat treatment and the higher the mobility μ. However, when the dose amount is increased, there is a problem that the crystal grain growth time is long. For example, when the dose amount of Si + is 2 × 10 15 cm -2 , the growth time is 30 hours or more.
本発明は、かかる点に鑑み、固相成長における結晶粒径
を大きくすると同時に、成長時間を短縮できるようにし
た電界効果型トランジスタの製造方法を提供するもので
ある。In view of the above point, the present invention provides a method for manufacturing a field effect transistor capable of increasing the crystal grain size in solid phase growth and reducing the growth time at the same time.
本発明は、表面が絶縁体である基板(21)上に形成した
非晶質又は多結晶半導体層(22)に電界効果型トランジ
スタを製造する方法において、その半導体層(22)のソ
ース領域(24)及びドレイン領域(25)に挟まれたチャ
ンネル領域(23)に選択的に不活性イオン(26)を注入
して後、650℃以下で熱処理して固相成長させる。The present invention relates to a method for producing a field effect transistor in an amorphous or polycrystalline semiconductor layer (22) formed on a substrate (21) whose surface is an insulator, in which the source region () of the semiconductor layer (22) is After selectively injecting the inert ions (26) into the channel region (23) sandwiched between the drain region (25) and the drain region (25), heat treatment is performed at 650 ° C. or lower for solid phase growth.
次に、チャンネル領域(23)上にゲート絶縁膜(26)を
介してゲート電極(27)を形成した後、ソース領域(2
4)及びドレイン領域(25)に第1導電形の不純物(2
8)を注入し、650℃以下で熱処理して活性化する。これ
以後は、通常のように層間絶縁層(9)を形成し、層間
絶縁層(9)にコンタクト用窓孔を形成して後、例えば
Alによるソース電極(10)及びドレイン電極(11)を形
成して、目的の電界効果型トランジスタ即ち薄膜トラン
ジスタ(30)を得る。Next, after the gate electrode (27) is formed on the channel region (23) via the gate insulating film (26), the source region (2
4) and impurities (2) of the first conductivity type in the drain region (25).
8) is injected and heat-treated at 650 ° C or below to activate. After that, the interlayer insulating layer (9) is formed as usual, and the contact window hole is formed in the interlayer insulating layer (9).
A source electrode (10) and a drain electrode (11) made of Al are formed to obtain a target field effect transistor, that is, a thin film transistor (30).
基板(21)としては、低温プロセスで使用可能な低融点
ガラス(例えば無アルカリガラス)、或いは石英ガラ
ス、半導体基板上にSiO2等の絶縁膜を被着した基板、等
を用いることができる。不活性イオン(26)としては、
半導体層(22)がシリコンの場合には、例えばシリコン
イオンSi+を用いることができる。As the substrate (21), it is possible to use a low melting point glass (for example, alkali-free glass) that can be used in a low temperature process, quartz glass, a substrate obtained by depositing an insulating film such as SiO 2 on a semiconductor substrate, or the like. As the inert ion (26),
When the semiconductor layer (22) is silicon, for example, silicon ion Si + can be used.
半導体層(22)のチャンネル領域(23)に不活性イオン
(26)を注入することにより、チャンネル領域(23)が
選択的に非晶質化される。次いで650℃以下の低温熱処
理で、チャンネル領域(23)が固相成長されるが、この
固相成長はチャンネル領域でランダム核生成が起きるよ
り先に、イオン注入されないソース領域(24)及びドレ
イン領域(25)の結晶粒を種としてソース及びドレイン
両領域側から成長されるため、固相成長時間が短縮され
る。By implanting the inert ions (26) into the channel region (23) of the semiconductor layer (22), the channel region (23) is selectively made amorphous. Next, the channel region (23) is solid-phase grown by low-temperature heat treatment at 650 ° C. or lower. This solid-phase growth occurs before the random nucleation occurs in the channel region, and the source region (24) and the drain region which are not ion-implanted. Since the crystal grains of (25) are used as seeds to grow from both source and drain regions, the solid phase growth time is shortened.
従って、不活性イオン(26)のドーズ量を多くして結晶
粒径を大きくする場合でも、その固相成長時間は短くな
る。Therefore, even when the dose amount of the inert ions (26) is increased to increase the crystal grain size, the solid phase growth time is shortened.
又、不純物イオンを注入した後のソース領域(24)及び
ドレイン領域(25)の活性化も低温(650℃以下)プロ
セスで行われる。この場合、固相成長と不純物の活性化
はほとんど同じ条件(温度、時間)で行われる。Further, activation of the source region (24) and the drain region (25) after implanting the impurity ions is also performed by a low temperature (650 ° C. or lower) process. In this case, solid phase growth and activation of impurities are performed under almost the same conditions (temperature, time).
以下、第1図を参照して本発明の電界効果型トランジス
タの製造方法の一例を説明する。An example of the method for manufacturing the field effect transistor of the present invention will be described below with reference to FIG.
先ず、第1図Aに示すように、例えば無アルカリガラス
の如き低融点ガラス基板(21)の一主面に膜厚800Å以
下の超薄膜のCVD多結晶シリコン層(又は水素化非晶質
シリコンa-Si:H)(22)を被着形成する。そして、この
多結晶シリコン層(22)を島領域化し、即ち所定領域を
残して、他をエッチング除去する。次いで、多結晶シリ
コン層(22)のチャンネル領域(23)を含む領域に対し
てマスクを介して選択的にシリコンイオン(Si+)(2
6)をイオン注入してチャンネル領域(13)を含む領域
を非晶質化する。従って、このときソース領域(24)及
びドレイン領域(25)はイオン注入されない。シリコン
イオン(26)のドーズ量は例えば2×1015cm-2程度であ
る。First, as shown in FIG. 1A, an ultra-thin CVD polycrystalline silicon layer (or hydrogenated amorphous silicon) having a film thickness of 800 Å or less is formed on one main surface of a low melting point glass substrate (21) such as non-alkali glass. a-Si: H) (22) is deposited. Then, the polycrystal silicon layer (22) is formed into an island region, that is, a predetermined region is left and the others are removed by etching. Then, silicon ions (Si + ) (2) are selectively applied to a region including the channel region (23) of the polycrystalline silicon layer (22) through a mask.
6) is ion-implanted to amorphize the region including the channel region (13). Therefore, at this time, the source region (24) and the drain region (25) are not ion-implanted. The dose amount of silicon ions (26) is, for example, about 2 × 10 15 cm -2 .
次に、第1図Bに示すように600℃のアニール処理を施
して、非晶質化されたチャンネル領域(23)を含む領域
を固相成長させる。このとき、ランダム核生成が起きる
より先に、ソース領域(24)及びドレイン領域(25)の
結晶粒を種としてソース及びドレイン領域の両側から固
相成長が起きる。従って、このときの固相成長時間は短
く、10時間程度である。Next, as shown in FIG. 1B, an annealing treatment is performed at 600 ° C. to solid-phase grow the region including the amorphized channel region (23). At this time, solid phase growth occurs from both sides of the source and drain regions using the crystal grains of the source region (24) and the drain region (25) as seeds before random nucleation occurs. Therefore, the solid phase growth time at this time is short, about 10 hours.
次に、第1図Cに示すようにチャンネル領域(23)上に
例えばSiO2等によるゲート絶縁膜(26)を介して多結晶
シリコンによるゲート電極(17)を形成し、このゲート
電極(27)とセルフアラインでソース領域(24)及びド
レイン領域(25)に、例えばnチャンネルFETであれば
n形不純物イオン(例えばリンイオンP+)(28)をイオ
ン注入する。このとき、同時にゲート電極(27)の多結
晶シリコンにもn形不純物が注入され、低抵抗のシリコ
ンゲート電極(27)が形成される。そして、このn形不
純物のイオン注入により、ソース領域(24)及びドレイ
ン領域(25)は非晶質化される。Next, as shown in FIG. 1C, a gate electrode (17) made of polycrystalline silicon is formed on the channel region (23) via a gate insulating film (26) made of, for example, SiO 2 , and the gate electrode (27) is formed. ) With self-alignment with the source region (24) and the drain region (25), for example, in the case of an n-channel FET, n-type impurity ions (eg phosphorus ions P + ) (28) are ion-implanted. At this time, n-type impurities are simultaneously implanted into the polycrystalline silicon of the gate electrode (27) to form a low resistance silicon gate electrode (27). The source region (24) and the drain region (25) are made amorphous by the ion implantation of the n-type impurity.
次に、第1図Dに示すように、600℃、7〜8時間のア
ニール処理を施し、ソース領域(24)及びドレイン領域
(25)を固相成長し、活性化する。Next, as shown in FIG. 1D, an annealing treatment is performed at 600 ° C. for 7 to 8 hours to solid-phase grow and activate the source region (24) and the drain region (25).
この場合、ゲート下のチャンネル領域(23)は既に結晶
化しているので、これを種にソース領域(24)及びドレ
イン領域(25)が結晶化される。In this case, since the channel region (23) under the gate is already crystallized, the source region (24) and the drain region (25) are crystallized using this as a seed.
然る後、第1図Eに示すように、全面に例えばPSG(リ
ンシリケートガラス)又はCVD SiO2等による層間絶縁
層(9)を被着形成して後、ソース及びドレインのコン
タクト用窓孔を形成し、次いで例えばAlのソース電極
(10)及びドレイン電極(11)を形成して目的の電界効
果型トランジスタ即ち超薄膜トランジスタ(30)を得
る。After that, as shown in FIG. 1E, an interlayer insulating layer (9) made of, for example, PSG (phosphosilicate glass) or CVD SiO 2 is deposited and formed on the entire surface, and thereafter, source and drain contact window holes are formed. Then, a source electrode (10) and a drain electrode (11) of Al, for example, are formed to obtain a target field effect transistor, that is, a super thin film transistor (30).
かかる製法によれば、第1図Bのアニール処理でチャン
ネル領域の固相成長に要する時間が、Si+のドーズ量2
×1015cm-2でも10時間程度となり、従来法の30時間に比
べて大幅に短縮される。しかもSi+のドーズ量を多くす
ることができるのでチャンネル領域の結晶粒成長が大き
くなり、移動度μが向上する。According to this method, the time required for solid phase growth of the channel region in the annealing process of FIG. 1 B is, Si + dose 2
Even with × 10 15 cm -2, it takes about 10 hours, which is much shorter than the conventional method of 30 hours. Moreover, since the dose amount of Si + can be increased, the crystal grain growth in the channel region is increased and the mobility μ is improved.
チャンネル領域(23)の固相成長において(第1図Bの
工程)、ソース領域(24)及びドレイン領域(25)の両
側から結晶粒成長が起きて例えばゲート下に結晶粒界
(29)が生じる場合には移動度μが多少下がるが、この
結晶粒界(29)がチャンネル長方向と直交する方向であ
るので、リーク電流はほとんど問題とならない。During solid phase growth of the channel region (23) (step of FIG. 1B), crystal grain growth occurs from both sides of the source region (24) and the drain region (25), and a grain boundary (29) is formed under the gate, for example. If it occurs, the mobility μ will be slightly lowered, but since this crystal grain boundary (29) is in the direction orthogonal to the channel length direction, the leakage current will hardly cause a problem.
尚、上例ではnチャンネルFETについて述べたが、Pチ
ャンネルFETの製法にも本発明は適用できる。Although the n-channel FET has been described in the above example, the present invention can be applied to a method of manufacturing a P-channel FET.
本発明によれば、非晶質又は多結晶半導体層のチャンネ
ル領域を不活性イオンの注入で選択的に非晶質化して低
温熱処理し、ソース及びドレイン領域からの結晶化を利
用して、チャンネル領域を固相成長させたことにより、
不活性イオンのドーズ量を多くしてもチャンネル領域の
固相成長時間を短くすることができる。従ってドーズ量
を多くし結晶粒径を大きくして移動度μを上げることが
できると同時に、その固相成長時間を大幅に短縮でき、
この種の薄膜トランジスタの製造を容易ならしめ得る。According to the present invention, a channel region of an amorphous or polycrystalline semiconductor layer is selectively amorphized by injecting inert ions and subjected to a low temperature heat treatment, and the crystallization from the source and drain regions is used to obtain the channel. By solid-phase growing the region,
Even if the dose amount of the inert ions is increased, the solid phase growth time of the channel region can be shortened. Therefore, the dose μ can be increased to increase the crystal grain size to increase the mobility μ, and at the same time, the solid phase growth time can be significantly reduced.
This type of thin film transistor can be easily manufactured.
第1図A〜Eは本発明の電界効果型トランジスタの製造
工程図、第2図A〜Eは従来の電界効果型トランジスタ
の製造工程図である。 (21)は基板、(22)は非晶質又は多結晶半導体層、
(23)はチャンネル領域、(24)はソース領域、(25)
はドレイン領域、(26)はゲート絶縁膜、(27)はゲー
ト電極である。1A to 1E are manufacturing process drawings of a field effect transistor of the present invention, and FIGS. 2A to 2E are manufacturing process drawings of a conventional field effect transistor. (21) is a substrate, (22) is an amorphous or polycrystalline semiconductor layer,
(23) is the channel area, (24) is the source area, (25)
Is a drain region, (26) is a gate insulating film, and (27) is a gate electrode.
Claims (1)
質又は多結晶半導体層に電界効果トランジスタを製造す
る方法において、 ソース領域とドレイン領域に挟まれたチャンネル領域に
不活性イオンを注入した後、650℃以下で熱処理を行っ
て固相成長させ、 さらにゲート電極を形成した後ソース領域及びドレイン
領域に不純物を注入し、650℃以下で熱処理を行って活
性化することを特徴とする電界効果型トランジスタの製
造方法。1. A method of manufacturing a field effect transistor in an amorphous or polycrystalline semiconductor layer formed on a substrate whose surface is an insulator, wherein inactive ions are introduced into a channel region sandwiched between a source region and a drain region. After implantation, heat treatment is performed at 650 ° C. or lower for solid phase growth, and after forming a gate electrode, impurities are implanted into the source region and the drain region, and heat treatment is performed at 650 ° C. or lower for activation. For manufacturing a field effect transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21675285A JPH0691109B2 (en) | 1985-09-30 | 1985-09-30 | Method for manufacturing field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21675285A JPH0691109B2 (en) | 1985-09-30 | 1985-09-30 | Method for manufacturing field effect transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6276772A JPS6276772A (en) | 1987-04-08 |
JPH0691109B2 true JPH0691109B2 (en) | 1994-11-14 |
Family
ID=16693365
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21675285A Expired - Lifetime JPH0691109B2 (en) | 1985-09-30 | 1985-09-30 | Method for manufacturing field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0691109B2 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2599726B2 (en) * | 1987-08-20 | 1997-04-16 | キヤノン株式会社 | Light receiving device |
JPS6450461A (en) * | 1987-08-20 | 1989-02-27 | Canon Kk | Photodetector |
KR970005945B1 (en) * | 1993-08-09 | 1997-04-22 | 엘지반도체 주식회사 | Thin film transistor & method of manufacturing the same |
JP3190520B2 (en) | 1994-06-14 | 2001-07-23 | 株式会社半導体エネルギー研究所 | Semiconductor device and manufacturing method thereof |
US5548132A (en) | 1994-10-24 | 1996-08-20 | Micron Technology, Inc. | Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions |
JP3376247B2 (en) * | 1997-05-30 | 2003-02-10 | 株式会社半導体エネルギー研究所 | Thin film transistor and semiconductor device using thin film transistor |
US6541793B2 (en) | 1997-05-30 | 2003-04-01 | Semiconductor Energy Laboratory Co., Ltd. | Thin-film transistor and semiconductor device using thin-film transistors |
JP4772258B2 (en) * | 2002-08-23 | 2011-09-14 | シャープ株式会社 | Manufacturing method of SOI substrate |
JP5271372B2 (en) * | 2011-03-18 | 2013-08-21 | 株式会社東芝 | Manufacturing method of semiconductor device |
-
1985
- 1985-09-30 JP JP21675285A patent/JPH0691109B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6276772A (en) | 1987-04-08 |
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