JPH0691109B2 - Method for manufacturing field effect transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a field effect transistor, particularly a thin film transistor.

[Outline of Invention]

The present invention relates to a method of manufacturing a thin film transistor, in which inert ions are implanted into a channel region of an amorphous or polycrystalline semiconductor layer, followed by heat treatment for solid phase growth, and then self-alignment with a gate electrode to form impurities in the source and drain regions. Is implanted and heat-treated for activation to improve the mobility μ and to shorten the time for solid phase growth and activation of impurities.

[Conventional technology]

Generally, a thin film transistor is formed by depositing a semiconductor thin film such as silicon on an insulating substrate such as quartz glass, and forming a channel region, a source region and a drain region in the semiconductor thin film to form a field effect transistor (FET). I have to. As such a thin film transistor, a super thin film transistor has been proposed in which the semiconductor thin film in the channel region is thinned to 100 Å to 800 Å to improve the characteristics (JP-A-60-136262).

Further, as the substrate of the thin film transistor, quartz glass having a high melting point is generally used, but since it is expensive,
It is desired to use an inexpensive low melting point glass (for example, non-alkali glass) for the substrate. When such a glass having a relatively low melting point is used as a substrate, a low temperature process is required so that the temperature during the manufacturing process of the thin film transistor is 650 ° C. or lower.

FIG. 1 shows an example of a conventional method for manufacturing a thin film transistor.

First, as shown in FIG. 2A, a thin film silicon layer (2) of, for example, polycrystalline silicon is formed on one surface of a low melting point glass substrate (1).
Then, the thin film silicon layer (2) is formed into island regions (leaving a predetermined region to remove the others), and then silicon ions Si ⁺ (3) are added to the thin film silicon layer (2).
Ion implantation (dose amount is 1.5 × 10 ¹⁵ / cm ² )
Amorphize. Either island formation or Si ⁺ ion implantation may be performed first.

Next, heat treatment is performed at 600 ° C. for 15 hours for solid phase growth (see FIG. 2B).

Next, as shown in FIG. 2C, a gate insulating film (4) made of, for example, SiO ₂ and a gate electrode (5) of polycrystalline silicon are deposited on the thin film silicon layer (2). Next, using the gate electrode (5) as a mask, an n-type impurity such as phosphorus ion (P ⁺ ) (8) is ion-implanted into the source region (6) and the drain region (7). At this time, phosphorus ions are also implanted into the gate electrode (5) of polycrystalline silicon, resulting in low resistance.

Next, heat treatment is performed at 600 ° C. for 7 to 8 hours to activate the source region (6) and the drain region (7) (see FIG. 2D).

Then, a SiO ₂ interlayer insulating layer (9) is deposited by CVD (Chemical Vapor Deposition) method, and then a contact window hole is formed, and a source electrode (10) and a drain electrode (11) made of Al are formed.
To obtain a thin film transistor (12).

[Problems to be solved by the invention]

In the conventional manufacturing method described above, the larger the dose of silicon ions (Si ⁺ ) in the step of FIG. 2A, the larger the crystal grain growth in the subsequent heat treatment and the higher the mobility μ. However, when the dose amount is increased, there is a problem that the crystal grain growth time is long. For example, when the dose amount of Si ⁺ is 2 × 10 ¹⁵ cm ^-2 , the growth time is 30 hours or more.

In view of the above point, the present invention provides a method for manufacturing a field effect transistor capable of increasing the crystal grain size in solid phase growth and reducing the growth time at the same time.

[Means for solving problems]

The present invention relates to a method for producing a field effect transistor in an amorphous or polycrystalline semiconductor layer (22) formed on a substrate (21) whose surface is an insulator, in which the source region () of the semiconductor layer (22) is After selectively injecting the inert ions (26) into the channel region (23) sandwiched between the drain region (25) and the drain region (25), heat treatment is performed at 650 ° C. or lower for solid phase growth.

Next, after the gate electrode (27) is formed on the channel region (23) via the gate insulating film (26), the source region (2
4) and impurities (2) of the first conductivity type in the drain region (25).
8) is injected and heat-treated at 650 ° C or below to activate. After that, the interlayer insulating layer (9) is formed as usual, and the contact window hole is formed in the interlayer insulating layer (9).
A source electrode (10) and a drain electrode (11) made of Al are formed to obtain a target field effect transistor, that is, a thin film transistor (30).

As the substrate (21), it is possible to use a low melting point glass (for example, alkali-free glass) that can be used in a low temperature process, quartz glass, a substrate obtained by depositing an insulating film such as SiO ₂ on a semiconductor substrate, or the like. As the inert ion (26),
When the semiconductor layer (22) is silicon, for example, silicon ion Si ⁺ can be used.

[Action]

By implanting the inert ions (26) into the channel region (23) of the semiconductor layer (22), the channel region (23) is selectively made amorphous. Next, the channel region (23) is solid-phase grown by low-temperature heat treatment at 650 ° C. or lower. This solid-phase growth occurs before the random nucleation occurs in the channel region, and the source region (24) and the drain region which are not ion-implanted. Since the crystal grains of (25) are used as seeds to grow from both source and drain regions, the solid phase growth time is shortened.

Therefore, even when the dose amount of the inert ions (26) is increased to increase the crystal grain size, the solid phase growth time is shortened.

Further, activation of the source region (24) and the drain region (25) after implanting the impurity ions is also performed by a low temperature (650 ° C. or lower) process. In this case, solid phase growth and activation of impurities are performed under almost the same conditions (temperature, time).

〔Example〕

An example of the method for manufacturing the field effect transistor of the present invention will be described below with reference to FIG.

First, as shown in FIG. 1A, an ultra-thin CVD polycrystalline silicon layer (or hydrogenated amorphous silicon) having a film thickness of 800 Å or less is formed on one main surface of a low melting point glass substrate (21) such as non-alkali glass. a-Si: H) (22) is deposited. Then, the polycrystal silicon layer (22) is formed into an island region, that is, a predetermined region is left and the others are removed by etching. Then, silicon ions (Si ⁺ ) (2) are selectively applied to a region including the channel region (23) of the polycrystalline silicon layer (22) through a mask.
6) is ion-implanted to amorphize the region including the channel region (13). Therefore, at this time, the source region (24) and the drain region (25) are not ion-implanted. The dose amount of silicon ions (26) is, for example, about 2 × 10 ¹⁵ cm ^-2 .

Next, as shown in FIG. 1B, an annealing treatment is performed at 600 ° C. to solid-phase grow the region including the amorphized channel region (23). At this time, solid phase growth occurs from both sides of the source and drain regions using the crystal grains of the source region (24) and the drain region (25) as seeds before random nucleation occurs. Therefore, the solid phase growth time at this time is short, about 10 hours.

Next, as shown in FIG. 1C, a gate electrode (17) made of polycrystalline silicon is formed on the channel region (23) via a gate insulating film (26) made of, for example, SiO ₂ , and the gate electrode (27) is formed. ) With self-alignment with the source region (24) and the drain region (25), for example, in the case of an n-channel FET, n-type impurity ions (eg phosphorus ions P ⁺ ) (28) are ion-implanted. At this time, n-type impurities are simultaneously implanted into the polycrystalline silicon of the gate electrode (27) to form a low resistance silicon gate electrode (27). The source region (24) and the drain region (25) are made amorphous by the ion implantation of the n-type impurity.

Next, as shown in FIG. 1D, an annealing treatment is performed at 600 ° C. for 7 to 8 hours to solid-phase grow and activate the source region (24) and the drain region (25).

In this case, since the channel region (23) under the gate is already crystallized, the source region (24) and the drain region (25) are crystallized using this as a seed.

After that, as shown in FIG. 1E, an interlayer insulating layer (9) made of, for example, PSG (phosphosilicate glass) or CVD SiO _{2 is} deposited and formed on the entire surface, and thereafter, source and drain contact window holes are formed. Then, a source electrode (10) and a drain electrode (11) of Al, for example, are formed to obtain a target field effect transistor, that is, a super thin film transistor (30).

According to this method, the time required for solid phase growth of the channel region in the annealing process of FIG. 1 B is, Si ⁺ dose 2
Even with × 10 ¹⁵ cm ^-2, it takes about 10 hours, which is much shorter than the conventional method of 30 hours. Moreover, since the dose amount of Si ⁺ can be increased, the crystal grain growth in the channel region is increased and the mobility μ is improved.

During solid phase growth of the channel region (23) (step of FIG. 1B), crystal grain growth occurs from both sides of the source region (24) and the drain region (25), and a grain boundary (29) is formed under the gate, for example. If it occurs, the mobility μ will be slightly lowered, but since this crystal grain boundary (29) is in the direction orthogonal to the channel length direction, the leakage current will hardly cause a problem.

Although the n-channel FET has been described in the above example, the present invention can be applied to a method of manufacturing a P-channel FET.

〔The invention's effect〕

According to the present invention, a channel region of an amorphous or polycrystalline semiconductor layer is selectively amorphized by injecting inert ions and subjected to a low temperature heat treatment, and the crystallization from the source and drain regions is used to obtain the channel. By solid-phase growing the region,
Even if the dose amount of the inert ions is increased, the solid phase growth time of the channel region can be shortened. Therefore, the dose μ can be increased to increase the crystal grain size to increase the mobility μ, and at the same time, the solid phase growth time can be significantly reduced.
This type of thin film transistor can be easily manufactured.

[Brief description of drawings]

1A to 1E are manufacturing process drawings of a field effect transistor of the present invention, and FIGS. 2A to 2E are manufacturing process drawings of a conventional field effect transistor. (21) is a substrate, (22) is an amorphous or polycrystalline semiconductor layer,
(23) is the channel area, (24) is the source area, (25)
Is a drain region, (26) is a gate insulating film, and (27) is a gate electrode.

Claims (1)

[Claims] 1. A method of manufacturing a field effect transistor in an amorphous or polycrystalline semiconductor layer formed on a substrate whose surface is an insulator, wherein inactive ions are introduced into a channel region sandwiched between a source region and a drain region. After implantation, heat treatment is performed at 650 ° C. or lower for solid phase growth, and after forming a gate electrode, impurities are implanted into the source region and the drain region, and heat treatment is performed at 650 ° C. or lower for activation. For manufacturing a field effect transistor.