JPH06132218A - Method for growing semiconductor crystal and manufacture of mos-type transistor - Google Patents

Abstract

PURPOSE:To provide a method for growing a semiconductor crystal and a method for manufacturing a MOS-type transistor which can reduce crystal defects and can grow a crystal uniformly. CONSTITUTION:The methods consist of a process (a) of forming a fine recessed part 14 in the surfaces of bases 10 and 12, a process (b) of forming a polycrystalline semiconductor layer 16 on the base surfaces including the inside of the recessed part 14, a process (c) of implanting ions into a semiconductor layer so as to turn a semiconductor layer 16B except a polycrystalline semiconductor layer 16A in the recessed part to a amorphous state, and a process (d) for performing low-temperature annealing treatment of the semiconductor layer, generating crystal growth using the polycrystalline semiconductor layer 16A left inside the recessed part as nuclei, and for growing a single crystal layer or polycrystalline layer in the amorphous semiconductor layer 16B.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for growing a semiconductor crystal and a method for manufacturing a MOS transistor.

[0002]

2. Description of the Related Art A stacked SRAM is proposed in which a thin film transistor (hereinafter abbreviated as TFT) using a thin film of amorphous silicon or polysilicon (hereinafter also referred to as polycrystalline silicon) is used as a load element. Also, TF
T is also used in LCD liquid crystal panels and the like. A polycrystalline silicon thin film is usually used in a TFT that requires high performance in on-current characteristics, subthreshold characteristics, on / off current ratio, and the like.

However, in polycrystalline silicon, dangling bonds of silicon atoms are present at a higher density than in single crystal silicon, which causes a leak current when the TFT is turned off, and when the TFT is turned on. It is also a cause of a decrease in the operating speed. Therefore, in order to improve the characteristics of the TFT, it is an important issue to form a polycrystalline silicon thin film having few crystal defects and excellent in uniformity.

The formation of polycrystalline silicon crystal grains has hitherto been carried out by a normal chemical vapor deposition method or a random solid phase growth method. However, it is difficult to form a polycrystalline silicon film having a uniform film quality, low leakage, and high mobility by an ordinary chemical vapor deposition method when forming large polycrystalline silicon crystal grains. Is. With the random solid phase growth method, it is possible to form a polycrystalline silicon thin film in which the grain size of the polycrystalline silicon crystal grains is 1 μm or more, but the polycrystalline silicon crystal grains are selectively grown. This is difficult, and moreover, there are many crystal grain boundaries in the TFT active region. As a result, the TF such as the leak current or the threshold voltage is changed depending on the grain boundary region.
The T characteristics vary, not only the reliability of the TFT is lowered, but also the lifetime of the TFT is shortened.

In order to improve these problems when a polysilicon thin film is used, in recent years, the Si ⁺ implantation dose amount for amorphization has been reduced at a predetermined position, and crystallization at the predetermined position has been performed. A method for forming silicon nuclei has been proposed (H. Kumomi et al., "Control
of Grain-Location in Solid State Crystallization
of Si ", Extended Abstracts of the 22nd (1990 Inter
national) Conferenceon Solid State Devices and Mat
erials, Sendai, 1990, pp 1159-1160, and JP-A-3-
No. 125422).

The method disclosed in Japanese Patent Laid-Open No. 3-125422 will be described with reference to the forming process diagram of FIG. First,
As shown in FIG. 3A, silicon (Si ⁺ ) is ion-implanted into the polysilicon layer 52 on the SiO ₂ layer 51 with a low dose amount. Next, as shown in FIG. 3B, a resist mask 53 is formed on the upper surface of the polysilicon layer 52 by using a lithographic technique, and the polysilicon layer 52 not covered with the resist mask 53 has a high dose Si. ⁺
Are selectively ion-implanted. Then, the resist mask 5
3 is removed, and as shown in FIG. 3C, a silicon crystal is grown by a low-temperature solid-phase growth method centering on a region implanted with ions at a low dose, and a single crystal silicon region 5 is formed.
4 is formed.

Alternatively, the present applicant has proposed a method of forming a silicon nucleus by irradiating a laser beam after coating a portion other than a predetermined position with a polysilicon / SiO ₂ layer (Japanese Patent Application No. 3-285720). No.). This method
As shown in FIG. 4A, a light shielding mask 64 is formed on the upper surface of the amorphous semiconductor layer 63 on the SiO ₂ layer 62 formed on the substrate 61 in the first step by using a lithography technique. Next, in a second step, using the light-shielding mask 64, the amorphous semiconductor layer is irradiated with excimer laser light to generate silicon nuclei 65 for crystal growth ((B) in FIG. 4).
reference). Subsequently, in the third step, a crystal is grown from the silicon nuclei 65 generated in the amorphous semiconductor layer 63 by performing the low temperature solid phase annealing treatment to form the single crystal region 66 ((in FIG. 4). See C)).

In these methods described in Japanese Patent Application Laid-Open No. 3-125422 or Japanese Patent Application No. 3-285720, the crystal grain size is increased at a predetermined position by solid phase growth at a low temperature. A TFT is produced in the crystal. The TFT manufactured by such a method is called a seed position control single crystal grain TFT. Such TFT
Since there is no grain boundary in the active region, it is expected to obtain a high-performance TFT with no variation in characteristics. Also, T
Since each FT can be formed in a single crystal grain, it is said that a plurality of TFTs with high uniformity can be manufactured.

An insulating film is formed on a base substrate, a concave portion is formed at a predetermined portion of the insulating film, and an island-shaped semiconductor thin film patterned to have a size to cover the concave portion is formed on the insulating film. A method for growing a semiconductor crystal that is recrystallized by irradiation is known from Japanese Patent Application Laid-Open No. 59-82714. The purpose of forming the recess is to control the molten / solidified state of the semiconductor thin film when the semiconductor thin film is solidified after beam annealing, and is not intended to start crystal growth from the recess.

[0010]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
In these semiconductor crystal growth methods described in Japanese Patent Application Laid-Open No. 2-285720 or Japanese Patent Application No. 3-285720, nuclei for crystal growth exist in the polysilicon layer 52 or the amorphous semiconductor layer 63. Usually, there is a region where the crystal axis is deviated in the nucleus for crystal growth. Since the contact area between the nucleus for crystal growth and the polysilicon layer 52 or the amorphous semiconductor layer 63 is large, even a single crystal region grown from the nucleus for crystal growth exists in the nucleus for crystal growth. There is a problem that crystal defects are generated due to the crystal defects.

Further, the method disclosed in Japanese Patent Application No. 3-285720, which selectively irradiates laser light, has a problem that it is difficult to ensure the uniformity of excimer laser light.

Therefore, an object of the present invention is to provide a method for growing a semiconductor crystal and a method for manufacturing a MOS transistor, which can further reduce crystal defects and can uniformly grow a crystal.

[0013]

In order to achieve the above object, the method for forming a semiconductor crystal according to the present invention comprises: (a) forming a fine recess on the surface of a base material; A step of forming a polycrystalline semiconductor layer on the surface of the base material including
(C) A step of performing ion implantation on the semiconductor layer to amorphize the semiconductor layer other than the polycrystalline semiconductor layer in the recess,
(D) A step of subjecting the semiconductor layer to a low-temperature annealing treatment to cause crystal growth with the polycrystalline semiconductor layer left in the recess as a nucleus, and to grow a single crystal or a polycrystal in the amorphized semiconductor layer. It is characterized by consisting of.

Further, in order to achieve the above-mentioned object, the method for manufacturing a MOS transistor of the present invention comprises:
Forming a fine recess in a part of the surface of the base material corresponding to the region where the type transistor is to be formed; and (b) forming a polycrystalline semiconductor layer on the base surface including the inside of the recess,
(C) A step of performing ion implantation on the semiconductor layer to amorphize the semiconductor layer other than the polycrystalline semiconductor layer in the recess,
(D) Low-temperature annealing treatment is applied to the semiconductor layer to cause crystal growth with the polycrystalline semiconductor layer left in the recess as nuclei, and single crystal grains or polycrystalline grains are grown on the amorphized semiconductor layer. And a step of forming a channel region formation scheduled region and a source / drain region formation scheduled region.

The method of forming a semiconductor crystal of the present invention or M
In the method of manufacturing the OS type transistor, the ion species in the ion implantation is preferably Si ⁺ or Ge ⁺ . Further, the ion implantation energy in the ion implantation is such that the polycrystalline semiconductor layer in the recess is not amorphized but the semiconductor layers other than the polycrystalline semiconductor layer in the recess are amorphized. Is desirable. A part of the polycrystalline semiconductor layer in the recess may be made amorphous. Further, the area of the recess is preferably 1 μm ² or less.

[0016]

In order to form a single crystal grain or a polycrystalline grain from a polycrystalline semiconductor layer at a desired position on a base material, a region serving as a nucleus for crystal growth is formed on the semiconductor layer corresponding to the desired position on the base material. Must exist. The region of the semiconductor layer that serves as a nucleus for crystal growth may be hereinafter referred to as a nucleation region. In the present invention, fine recesses are formed on a desired substrate surface, and the semiconductor layer is left only in the recesses. by this,
A nucleation region is formed, and crystal growth can be started from the semiconductor layer in the recess.

When a large number of nucleation regions are present, crystals grow from the large number of nucleation regions, so that the size of the obtained crystal grains becomes small. Therefore, in order to increase the size of the crystal grain, the smaller the nucleation region is, the better. In the present invention, the semiconductor layer is ion-implanted to amorphize the semiconductor layer except the polycrystalline semiconductor layer in the recess. As a result, the nucleation region can be limited to the semiconductor layer in the recess, and the size of the grown crystal grain can be increased.

When the area of the nucleation region is large, the nucleation region contains a large number of nuclei. As a result, many crystal defects exist in the grown crystal grains. Therefore, the smaller the area of the nucleation region, the better. In a preferred aspect of the present invention, the crystal defects in the grown crystal grains can be reduced by setting the area of the recesses to 1 μm ² or less.

Further, before the polycrystalline semiconductor layer is formed on the surface of the base material including the inside of the recesses, fine recesses which become nucleation regions during crystal growth are formed on the surface of the base material. The contact area with the qualitative semiconductor layer is small. Therefore, the crystal defects existing in the nucleation region do not adversely affect the growing single crystal or polycrystal, and a more uniform single crystal or polycrystal with less defects can be formed.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described based on embodiments with reference to the drawings. The embodiment will be described by taking a top gate type thin film p-type transistor as an example.

First, fine recesses are formed on the surface of the base material.
Therefore, the oxide film 12 is deposited on the substrate 10 based on the conventional semiconductor device manufacturing method. The substrate 10 is made of silicon, for example. The oxide film 12 is made of, for example, SiO ₂ having a thickness of about 500 nm formed by the CVD method. Next, by photolithography method and etching method,
Fine recesses 14 are formed at desired positions on the surface of the base material (specifically, the oxide film 12) (see FIG. 1A). Recess 14
Can be, for example, 0.5 × 0.5 μm and have a depth of 50 nm. In the present embodiment, the position where the concave portion 14 is to be formed corresponds to the channel region formation planned region in the MOS type transistor formation planned region.

Next, a polycrystalline semiconductor layer is formed on the surface of the base material including the inside of the recess. That is, the semiconductor layer 16 made of polycrystalline silicon is formed on the oxide film 12 including the fine recesses 14 (see FIG. 1B). The semiconductor layer 16 can be formed by a CVD method with good step coverage. The thickness of the semiconductor layer 16 is about 10 on the oxide film 12.
0 nm. Semiconductor layer 16A formed in the recess 14
Is the nucleation region (the region of the semiconductor layer that becomes the nucleus of crystal growth)
Equivalent to.

Thereafter, the semiconductor layer 16 is ion-implanted to amorphize the semiconductor layer 16B except for the polycrystalline semiconductor layer 16A in the recess (see FIG. 1C). The ion implantation energy in the ion implantation is the nucleation region 16
The energy is preferably such that A is not amorphized and the other semiconductor layers 16B are amorphized. Further, it is desirable that the ion species in the ion implantation is Si ⁺ or Ge ⁺ . Ion implantation can be performed, for example, under the following conditions. Implantation energy: 40 keV Dose amount: 3 × 10 ¹⁵ to 2 × 10 ¹⁶ / cm ² Ion species: Si Incidentally, a part of the polycrystalline semiconductor layer 16A in the recess may be made amorphous.

Next, the semiconductor layers 16A and 16B are subjected to a low temperature annealing treatment to cause crystal growth with the polycrystalline semiconductor layer 16A left in the recess as a nucleus, and the amorphized semiconductor layer 16B is made into a single crystal. Grains or polycrystalline grains are grown to form a channel region formation scheduled region and a source / drain region formation scheduled region. The low temperature annealing condition may be, for example, temperature: 550 to 800 ° C. time: 0.5 to 20 hours. As a result, crystal grains of about 5 to 10 μm can be obtained.

Thereafter, the top gate type thin film p is formed by the conventional method.
A type transistor is manufactured. That is, crystal grains existing in a region other than a region where a transistor is to be formed are removed by a photolithography method and an etching method (see FIG. 2A). After that, a thickness of 30 nm is formed on the crystal grain 18.
Gate oxide film 20 is further deposited, a polycrystalline silicon layer is further deposited thereon, and the polycrystalline silicon layer is patterned by a photolithography method and an etching method to form a gate electrode 22 ((B in FIG. 2). )reference).

Then, using the resist mask, ion implantation is performed to form the source / drain regions 24.
The ion implantation conditions, for example when using boron ^{ions, 10keV, 3 × 10 15 /} cm 2, when using the BF ₂ ^+, can be ^{35keV, 3 × 10 15 / cm} 2. Next, for example, activation annealing of the source / drain regions is performed using an electric furnace. The conditions of activation annealing can be, for example, temperature: 900 ° C. time: 20 minutes. Alternatively, by the RTA method, 11
Activation annealing at about 00 ° C. for about 10 seconds can also be performed.

After that, an interlayer insulating layer 26 made of PSG, silicon nitride or the like is formed on the entire surface, an opening is formed in the interlayer insulating layer 26 by the RIE method, and a metal wiring material is formed on the opening and the interlayer insulating layer 26. Is formed by a sputtering method, and then
The metal wiring material is patterned to form the wiring layer 28 (see FIG. 2C). Thus, the top gate thin film p-type transistor is completed.

Although the present invention has been described based on the preferred embodiment, the present invention is not limited to this embodiment. The various numerical values, conditions, etc. described in the embodiments are examples, and can be changed as appropriate. As the base material, a combination of a silicon substrate and an oxide film made of SiO ₂ is exemplified. For example, after forming elements such as transistors and capacitors on the silicon substrate, Si ₃ N ₄ , Si
It is also possible to form an interlayer insulating layer such as O ₂ or PSG and use this as a base material. When forming a p-type channel, B ⁺ and BF ₂ ⁺ can be used as ion species during ion implantation, and when forming an n-type channel, P ⁺ and As ⁺ can be used as ion species. As the MOS type transistor, besides the top gate type thin film p type transistor, a top gate type thin film n type transistor, a bottom gate type thin film p type transistor, a bottom gate type thin film n type transistor and the like can be exemplified.

[0029]

According to the method for growing a semiconductor crystal of the present invention, before forming a polycrystalline semiconductor layer on the surface of the base material including the inside of the concave portion, a fine concave portion which becomes a nucleation region during crystal growth is formed on the base material. Since it is formed on the surface, the contact area between the nucleation region and the amorphized semiconductor layer is small. Therefore, the crystal defects existing in the nucleation region do not adversely affect the growing single crystal or polycrystal, and it is possible to form more uniform and large crystal grains with few defects.

Further, according to the method of manufacturing a MOS transistor of the present invention, it is possible to manufacture a transistor from large crystal grains with few crystal defects, and it is possible to improve the rising characteristics and leak characteristics of the transistor. In addition, the resistance of the source / drain region can be reduced, and the current driving capability of the transistor can be improved. Furthermore,
Since there is no crystal grain boundary in the channel formation region, variations in threshold voltage are eliminated, so that a transistor with a small leak current and a large current driving capability can be manufactured.
When a TFT manufactured by the method for manufacturing a MOS transistor of the present invention is used as a load element for SRAM, low current consumption can be achieved, and alpha ray resistance and reliability can be improved.

[Brief description of drawings]

FIG. 1 is a semiconductor crystal growth method or MOS according to the present invention.
FIG. 6 is a schematic partial cross-sectional view of a semiconductor element for explaining the steps of the method for manufacturing the type transistor.

FIG. 2 is a schematic partial cross-sectional view of the semiconductor element for explaining the steps of the method for manufacturing a MOS transistor, continuing from FIG.

FIG. 3 is a schematic cross-sectional view of a semiconductor device for showing a manufacturing process of a conventional seed position controlled single crystal grain thin film transistor.

FIG. 4 is a schematic cross-sectional view of a semiconductor device for showing a manufacturing process of a conventional seed position controlled single crystal grain thin film transistor different from that of FIG.

[Explanation of symbols]

 10 Substrate 12 Oxide Film 14 Recess 16 Semiconductor Layer 16A Semiconductor Layer 18 Formed in Recess 14 Crystal Grain 20 Gate Oxide Film 22 Gate Electrode 24 Source / Drain Region 26 Interlayer Insulation Layer 28 Wiring Layer

Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784

Claims (8)

[Claims] 1. A process of forming fine recesses on the surface of a base material, and a process of forming a polycrystalline semiconductor layer on the surface of the base material including the inside of the recesses, and (c) the semiconductor layer. Ion-implanting the semiconductor layer to amorphize the semiconductor layers other than the polycrystalline semiconductor layer in the recess, and (d) low-temperature annealing treatment of the semiconductor layer to leave the polycrystalline semiconductor in the recess. A method of growing a semiconductor crystal, comprising the step of causing crystal growth to occur with the layer as a nucleus and growing a single crystal or a polycrystal in the amorphized semiconductor layer. 2. The ion species in the ion implantation is Si ⁺
2. The method for growing a semiconductor crystal according to claim 1, wherein the method comprises growing Ge ⁺ . 3. The ion implantation energy in the ion implantation does not amorphize the polycrystalline semiconductor layer in the recess, but amorphizes the semiconductor layers except the polycrystalline semiconductor layer in the recess. The method for growing a semiconductor crystal according to claim 2, wherein the energy is as described above. 4. The method of growing a semiconductor crystal according to claim 1, wherein the area of the recess is 1 μm ² or less. 5. A method for manufacturing a MOS transistor, comprising: (a) a step of forming a fine recess in a part of a surface of a base material corresponding to a region where a MOS transistor is to be formed; and (b) a base including the inside of the recess. A step of forming a polycrystalline semiconductor layer on the material surface, and (c) a step of implanting ions into the semiconductor layer to amorphize the semiconductor layer excluding the polycrystalline semiconductor layer in the recess. D) A low-temperature annealing treatment is applied to the semiconductor layer to cause crystal growth with the polycrystalline semiconductor layer left in the recess as a nucleus, and to grow single crystal grains or polycrystalline grains in the amorphized semiconductor layer. And a step of forming a channel region formation planned region and a source / drain region formation planned region. 6. The ion species in the ion implantation is Si ⁺
6. The method for manufacturing a MOS transistor according to claim 5, wherein the MOS transistor is made of Ge ⁺ . 7. The ion implantation energy in the ion implantation does not amorphize the polycrystalline semiconductor layer in the recess, but amorphizes the semiconductor layers except the polycrystalline semiconductor layer in the recess. 7. The method for manufacturing a MOS transistor according to claim 6, wherein the energy is as described above. 8. The method for producing a MOS transistor according to claim 5, wherein the area of the recess is 1 μm ² or less.