JPH09289168A - Semiconductor thin film, its forming method, semiconductor device and its forming method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor thin film having crystallinity which is equal to a single crystal, and a semiconductor device having an active layer formed by using the thin film. SOLUTION: A recessed or a protruded pattern 103 is intendedly formed on an silicon oxide film 102 which is in contact with a lower surface of an amorphous silicon film 104, and a site wherein metal elements which promote crystallization are easily segregated is formed. It becomes possible to selectively form a nuclear of a crystal on a position on which the recessed or the protruded pattern 103 is formed, and the diameter of crystal grains can be controlled. A monodomain region in which grain boundaies do not practically exist is formed by thermally treating a crystalline silicon film 109 obtained by the above processes, in an atomosphere containing halogen elements.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a semiconductor thin film having a region (hereinafter referred to as a monodomain region) formed on a substrate having an insulating surface and which can be regarded as a substantially single crystal, and a semiconductor device having the semiconductor thin film as an active layer. In particular, the present invention relates to a thin film transistor having an active layer made of a crystalline silicon film.

[0002]

2. Description of the Related Art In recent years, a technique for forming a thin film transistor (TFT) by using a thin silicon semiconductor film (having a thickness of several hundreds to several thousands Å) formed on a substrate having an insulating surface has received attention. Thin film transistors have been widely applied to electronic devices such as ICs and liquid crystal display devices.

The important part which should be called the heart of the thin film transistor is a channel forming region and a junction part for joining the channel forming region and the source / drain regions. That is, it can be said that the active layer most affects the performance of the thin film transistor.

As a semiconductor thin film forming an active layer of a thin film transistor, an amorphous silicon film (amorphous silicon film) formed by a plasma CVD method or a low pressure thermal CVD method is generally used.

At present, a thin film transistor using an amorphous silicon film has been put into practical use, but a silicon thin film having crystallinity (referred to as a crystalline silicon film) is used when higher speed operation is required. A thin film transistor utilized is needed.

For example, a peripheral circuit of an active matrix type liquid crystal display device or a passive type liquid crystal display device, a driving circuit for driving a pixel TFT arranged in a pixel region, a circuit for handling and controlling a video signal, A memory circuit or the like for storing various kinds of information is required.

Further, among these circuits, a circuit for handling and controlling a video signal and a memory circuit for storing various information are required to have performance comparable to an integrated circuit using a known single crystal wafer. Therefore, in order to integrate these circuits using a thin film semiconductor formed on a substrate, it is necessary to form a crystalline silicon film having crystallinity comparable to a single crystal on the substrate.

As a method for forming a crystalline silicon film on a substrate, Japanese Patent Laid-Open No. 6-232059 and Japanese Laid-Open Patent Application No.
The technique described in Japanese Patent No. 244103 is known. The technique described in this publication forms a crystalline silicon film having excellent crystallinity by heat treatment at 550 ° C. for about 4 hours by utilizing a metal element that promotes crystallization of silicon. .

However, even if the above-mentioned technique is applied to the active layer of a thin film transistor, there is a feeling that the thin film transistor is not useful as a thin film transistor for forming various arithmetic circuits and memory circuits. This is because the crystallinity is still insufficient and the required properties cannot be obtained.

In particular, it is a necessary condition that a crystalline silicon film having crystallinity comparable to that of a single crystal has substantially no crystal grain boundaries. This is because the crystal grain boundaries serve as energy barriers that hinder the progress of electrons traveling between crystals.

Here, the inventors of the present invention classify the process of crystal growth using the above technique into the first to fourth steps, and consider the following model. The description will be given with reference to FIG.

In FIG. 10A, reference numeral 11 is a silicon oxide film formed as a buffer layer on the surface of the substrate. An amorphous silicon film 13 is formed thereon. At this time, the concave or convex portion 12 on the silicon oxide film (only the convex portion is shown in the drawing)
Is formed by surface roughness and dust of the silicon oxide film.

Then, a solution containing a metal element that promotes crystallization is dropped on the surface of the amorphous silicon film 13, and coating is performed by spin coating. Then, as shown in FIG. 10A, a state in which the nickel layer 14 is held on the surface of the amorphous silicon film 13 is obtained.

In this state, heat treatment is performed in the temperature range of 500 to 700 ° C. to crystallize the amorphous silicon film 13.

Then, first, as indicated by the arrow in FIG. 10B, the metal element isotropically internally diffuses in the amorphous silicon film 13 and reaches the interface with the silicon oxide film 11. This is the first
Is the step.

Then, the metal element migrates at the interface between the silicon oxide film 11 and the amorphous silicon film 13 and segregates into the concave or convex portion 12. This is the second step.
This is because the metal element seeks an energy-stable site, and in this case, the concave or convex portion 12 became a segregation site. (Figure 10 (C))

At this time, since the metal element is present at a high concentration in the concave or convex portion 12 which has become the segregation site, crystal nuclei are generated there. According to the research conducted by the present inventors, when the metal element is nickel, a crystal nucleus can be formed when the concentration thereof is 1 × 10 ²⁰ atoms / cm ³ or more.

Crystal growth starts from the crystal nuclei, but first, crystallization proceeds in a direction substantially perpendicular to the silicon film surface. This is the third step. (Figure 10 (D))

A region 15 in which crystallization has proceeded in a direction substantially perpendicular to the surface of the silicon film (hereinafter referred to as a vertical growth region) 15 promotes crystallization while pushing up the metal element concentrated to a high concentration. The high-concentration metal element is also concentrated on the surface of the amorphous silicon film 13 located above the concave or convex portion 12.
As a result, the vertical growth region 15 becomes a region having a higher metal element concentration than other regions.

Then, the amorphous silicon film 13 is grown vertically on the region 15.
A direction substantially parallel to the substrate with the interface 16 in contact with
Crystal growth starts in 0 (E) (direction indicated by an arrow). This is the fourth step. The crystal 17 is a columnar or acicular crystal whose crystal width is almost equal to the film thickness of the amorphous silicon film 13. (FIG. 10E)

Since this crystal 17 travels in a direction substantially parallel to the substrate, it eventually collides with another crystal facing each other and stops growing. Then, as shown in FIG. 10 (F), the bumped boundaries become the crystal grain boundaries 18. Further, the crystal region (hereinafter, referred to as a lateral growth region) 19 formed in this way has a relatively uniform crystallinity.

As described above, in the conventional crystallization form, segregation sites are formed irregularly and innumerably, so that the density of crystal nuclei is high and the individual crystal grains interfere with each other's growth. I will end up. Therefore, the crystal grain size must be small.

That is, for example, even if the active layer of a thin film transistor is formed on the crystalline silicon film formed by the above technique,
Under the present circumstances, it is impossible to realize crystallinity comparable to that of a single crystal because the crystal grain boundary is always included in the inside.

Although the crystal grain size can be secured by reducing the generation density of the crystal nuclei, the position of the crystal nuclei is determined depending on where the segregation site of the metal element exists. Sites that will become segregation sites as they are (for example, the concave or convex portion 1 as shown in FIG.
It is impossible to control its position because 2) is irregularly formed.

Further, in the case of the means described in the above publication, the metal element used in the crystallization remains in the crystalline silicon film, and the reproducibility and the reproducibility of the semiconductor device when the semiconductor device is actually constructed. It has been suggested by the present inventors that it becomes an anxiety factor that affects stability.

[0026]

SUMMARY OF THE INVENTION An object of the invention disclosed in the present specification is to form a monodomain region having crystallinity comparable to a single crystal on a substrate having an insulating surface. Then, it is an object to obtain a semiconductor device in which an active layer is formed by the monodomain region.

[0027]

The structure of the invention disclosed in the present specification is a semiconductor thin film formed on a substrate having an insulating film on its surface, wherein the semiconductor thin film is in a columnar shape substantially parallel to the substrate or It has a monodomain region formed by accumulating a plurality of acicular crystals, and the insulating film in contact with the lower surface of the semiconductor thin film is provided with a deliberately formed concave or convex pattern. .

According to another aspect of the present invention, there is provided a semiconductor thin film formed on a substrate having an insulating film on the surface thereof, wherein the semiconductor thin film is formed by collecting a plurality of columnar or needle crystals substantially parallel to the substrate. Has a mono-domain region in which substantially no grain boundaries exist, and the insulating film in contact with the lower surface of the semiconductor thin film is provided with a deliberately formed concave or convex pattern. Hydrogen and halogen elements are contained in the semiconductor thin film constituting the above in a concentration of 5 atomic% or less, and the halogen element is an element selected from chlorine, bromine and fluorine.

A semiconductor device having a structure of another invention uses only the monodomain region as an active layer. The inside of this monodomain region is characterized in that there is substantially no grain boundary.

According to another aspect of the invention, in forming a semiconductor thin film on a substrate having an insulating film on its surface, a step of forming a silicon oxide film on the substrate having an insulating surface by a sputtering method, and the above-mentioned oxidation. Patterning the silicon film into a desired shape to intentionally provide a concave or convex pattern;
A step of forming an amorphous silicon film on the silicon oxide film by a low pressure thermal CVD method, and a step of holding a metal element that promotes crystallization in the silicon oxide film and / or the amorphous silicon film. A step of transforming the amorphous silicon film into a crystalline silicon film by a first heat treatment, and a halogen element on the crystalline silicon film by a second heat treatment in an atmosphere containing a halogen element. Forming a thermal oxide film containing, and removing the thermal oxide film,
At least, and the crystalline silicon film is transformed into a monodomain region by the second heat treatment. Further, it is characterized in that the active layer is constituted by a mono domain region formed through these steps.

The present inventors define the crystal region obtained by the present invention as a region that can be regarded as a substantially single crystal, that is, a monodomain region. The definition of the monodomain region is that there is substantially no crystal grain boundary in the region and there are almost no crystal defects due to dislocations, stacking faults and the like. Further, it goes without saying that it does not contain a metal element that affects the device.

It should be noted that "there is substantially no crystal grain boundary" means that even if the crystal grain boundary exists, it is electrically inactive. Such electrically inactive grain boundaries include {111} twin grain boundaries, {111} stacking faults,
{221} twin grain boundaries and {221} Twist twin grain boundaries have been reported (R.Simokawa and Y.Hayashi: Jpn.J.App.
l.Phys. 27 (1987) pp.751 to 758).

The present inventors speculate that the crystal grain boundaries contained in the monodomain region are highly likely to be these electrically inactive crystal grain boundaries. That is, it is considered to be an inactive region that does not electrically hinder the movement of carriers even if it appears as grain boundaries.

Therefore, the present inventors first examined means for increasing the crystal grain size in order to reduce the crystal grain boundaries. As a result, they have invented a means for controlling crystal nuclei that could not be controlled conventionally.

The means is to make the surface state of the insulating film in contact with the lower surface of the amorphous silicon film extremely smooth. Therefore, in the present invention, a silicon oxide film formed by a sputtering method using an artificial quartz target is provided below the amorphous silicon film as a buffer layer (as a reference material, a component table of the artificial quartz target is shown in FIG. 18). The silicon oxide film thus formed is extremely dense and smooth, and has almost no concaves or convexes that become segregation sites as in the conventional case.

Next, the silicon oxide film is patterned to intentionally form a concave or convex pattern. That is, it is possible to control the generation position of crystal nuclei by intentionally forming segregation sites of metal elements that promote crystallization.

Therefore, there is a great advantage that it is possible to design to form a crystal having a desired size at a desired position in the element designing stage. This is very useful industrially.

Further, it is one of the features of the present invention that the low pressure thermal CVD method is used as a method for forming the amorphous silicon film.
The amorphous silicon film formed by the low pressure thermal CVD method has a smaller hydrogen content than the amorphous silicon film formed by the plasma CVD method, and is characterized in that the film quality is dense, and thus the generation of natural nuclei is small. are doing.

Since a large amount of natural nucleation is a great obstacle to the purpose of controlling the crystal nuclei, it is extremely convenient that the natural nucleation is small.

Next, a means for making a crystal having a large crystal grain size formed as described above into a single crystal (more precisely, a monodomain region) was examined. As a result, it was found that the monodomain region can be formed by performing heat treatment in an atmosphere containing a halogen element.

The configuration of the present invention as described above will be described in detail with reference to the embodiments described below.

[0042]

【Example】

[Example 1] In this example, a process of forming a monodomain region, which is the most important concept in the present invention, will be described. 1A to 1F and 2A to 2C are cross-sectional views of a silicon film formed over a substrate having an insulating surface.

In FIG. 1A, reference numeral 101 is a substrate having excellent heat resistance, and a quartz substrate, a silicon substrate or the like is used. 102 is a silicon oxide film formed by a sputtering method. At this time, an artificial quartz target is used as the target used for sputtering.

The silicon oxide film 102 formed by using the artificial quartz target has an extremely flat surface and is in a smooth state. For example, the height of the surface irregularities is 30 Å or less, the width of the surface irregularities is 100 Å or more, and AFM (Atomic For
Even if it is observed by ce Microscopy), it becomes a level that is difficult to recognize as unevenness.

After forming the silicon oxide film 102, patterning is performed to intentionally form a concave or convex pattern 103. This embodiment describes only the case where a square fine island-shaped pattern is formed and is intentionally patterned so as to form a convex portion, but the same effect can be obtained by forming a concave portion. . This concave or convex pattern 103
May be as high as about half the thickness of an amorphous silicon film to be formed later.

After patterning into a desired shape, the amorphous silicon film 104 is subjected to 100 to 750 Å (preferably 150 to Å by plasma CVD, sputtering or low pressure thermal CVD.
Form a film with a thickness of 450Å). When the low pressure thermal CVD method is used, disilane (Si ₂ H ₆ ) or trisilane (Si ₃ H ₈ ) may be used as the film forming gas.

When the crystalline silicon film obtained by the subsequent crystallization is used as the active layer of the semiconductor device by setting the film thickness of the amorphous silicon film 104 to the above film thickness, a semiconductor device having a low off current is manufactured. can do.

The amorphous silicon film formed by the low pressure thermal CVD method has a small natural nucleus generation rate during the subsequent crystallization. The spontaneous nucleation rate is a rate at which an amorphous silicon film generates nuclei by thermal energy without being affected by a metal element such as nickel that promotes crystallization.

This is desirable for increasing the grain size of individual crystals in the subsequent crystallization step, because the rate of the individual crystals interfering with each other (colliding and stopping the growth) is reduced.

When forming the amorphous silicon film 104, attention must be paid to the cleanliness of the surface of the silicon oxide film 102 which is a buffer layer. As described in the conventional example, if there is dust or the like, it becomes a segregation site of a metal element that promotes crystallization, and becomes a starting point of nucleation.

After forming the amorphous silicon film 104, UV light is irradiated in an oxygen atmosphere to form a very thin oxide film (not shown) on the surface of the amorphous silicon film 104. This oxide film is for improving the wettability of the solution in the solution coating step when introducing the metal element later.

Next, a solution containing a metal element that promotes crystallization at a predetermined concentration is dropped on the surface of the amorphous silicon film 104 to form a water film (not shown). The metal elements include Fe, Co, Ni, Ru, Rh, Pd, Os and I.
One or more kinds selected from r, Pt, Cu, and Au can be used, but Ni (nickel) has shown the most remarkable effect according to the research of the inventors.

In consideration of residual impurities in the subsequent heating step, it is preferable to use a nickel nitrate salt solution as the above solution. Although a nickel acetate salt solution can be used, the nickel acetate salt solution contains carbon,
This is because there is a concern that this may be carbonized in the subsequent heating step and remain in the film.

In the state shown in FIG. 1A, spin coating is performed using a spinner so that the nickel layer 105 is held in contact with the amorphous silicon film 104 via an oxide film (not shown).

At this time, the amorphous silicon film 104 above the concave or convex pattern 103 has the concave or convex pattern 103.
Concave or convex portion 106 is formed along the shape of.
Therefore, during spin coating, the periphery of the concave or convex portion 106 is likely to be a region where nickel is locally present at a high concentration due to surface tension, and during later crystallization, crystallization by the fourth step (with respect to the substrate) is performed. Therefore, there is also an effect that crystallization in a substantially parallel direction) easily proceeds.

In this embodiment, the solution coating step is performed on the amorphous silicon film 104, but it may be performed on the silicon oxide film 102 which is a buffer layer before the amorphous silicon film 104 is formed. The same effect can be obtained. Further, solution coating may be performed on both surfaces of the silicon oxide film 102 and the amorphous silicon film 104.

After obtaining the state of FIG. 1 (A), hydrogen is degassed in an inert atmosphere at 450 ° C. for about 1 hour, and then at a temperature of 500 to 700 ° C., typically 550 to 600 ° C. for 4 hours. Amorphous silicon film 10 is formed by applying heat treatment for 8 hours.
Crystallization of No. 4 is performed (first heat treatment). This crystallization proceeds as follows.

First, as a first step, nickel is activated by being heated and isotropically diffuses inside the amorphous silicon film 104 as indicated by an arrow. (Fig. 1 (B))

Next, as a second step, nickel migrates at the interface between the silicon oxide film 102 and the amorphous silicon film 104 and segregates into the concave or convex pattern 103. That is, the concave or convex pattern 103 functions as an intentionally formed segregation site. (Fig. 1 (C))

Next, the nickel concentration in the peripheral portion of the concave or convex pattern 103, which has become the segregation site, is about 1 × 10 ²⁰ atoms /
When it becomes cm ³ or more, crystal nuclei are generated there, and crystallization proceeds in a direction substantially perpendicular to the silicon film surface. As described above, the vertical growth region 107 formed in the third step is a region containing nickel at a high concentration. (Fig. 1 (D))

Then, as a fourth step, crystal growth proceeds in a direction substantially parallel to the silicon film surface starting from the vertical growth region 107. The lateral growth region 108 thus formed is formed by a plurality of columnar or acicular crystals being aligned in a relatively aligned direction.
It is superior in terms of crystallinity.

At this time, since the segregation sites are intentionally controlled and formed, the crystal grain size can be expanded and grown without being affected by other crystal grains. That is, by appropriately designing the formation position of the segregation site, it becomes possible to form a crystal having a desired size at a desired position.

However, how much the crystal grain size can be increased is determined by the temperature and time of the heat treatment, so that it may be appropriately determined in consideration of the manufacturing cost and the like. Further, since heat treatment at a higher temperature is performed in the subsequent single crystallization step, it must be taken into consideration that the crystal growth also progresses at that time.

As described above, the crystalline silicon film 109 as shown in FIG. 1 (F) is obtained. It should be noted here that the present invention is fundamentally different from the known graphoepitaxy technique.

In the graphoepitaxy technique, when the surface shape of the underlayer film has regularity and the amorphous silicon film is crystallized,
The orientation of the crystalline silicon film is made uniform by utilizing the property that the most stable surface appears.

The present invention is characterized in that the surface energy of the underlayer is changed by changing the surface shape of the underlayer so that the metal element which promotes crystallization is easily segregated. Therefore, this is a technique different from the graphoepitaxy technique in that the formation of crystal nuclei is the reason for changing the surface shape.

Here, FIG. 3A shows a view of the crystalline silicon film 109 as viewed from above. In FIG. 3A, 301
Is the vertical growth region formed in the third step (FIG. 1D).
Area 107). In this embodiment, since a fine square island pattern is formed,
The shape is as shown.

Reference numeral 302 indicates a lateral growth region formed in the fourth step (109 in FIG. 1F).
Area). The lateral growth region 302 grows with the central vertical growth region 301 as a nucleus, and in the present embodiment, the vertical growth region 301 can be regarded as a point. Therefore, a substantially hexagonal shape as shown in FIG. It becomes the shape of.

The present inventors consider the reason for this as follows. Regarding the crystal morphology of a silicon film, it is generally (111)
It is known that when the nuclei surrounded by the planes are crystal-grown, the crystal grains become hexagonal.

Although nickel is used as the metal element that promotes crystallization in this embodiment, nickel suicide may be formed on the tip or side surface of the columnar or needle-like crystal during crystallization. Shown by the inventors.

The stable surface of this nickel silicide is (11
It is known that this is the 1) plane, and taking this into consideration, the (111) plane, which is the stable plane of nickel silicide, is predominant in the plane surrounding the vertical growth region 301 that becomes the crystal nucleus.

Therefore, if the vertical growth region 301 serving as the crystal nucleus is regarded as a point in the fourth step, it is an obvious reason that the lateral growth region 302 having the crystal grown from that point becomes a substantially hexagon. .

Lateral growth region 3 formed as described above
02 is divided into six parts A to F as shown in FIG. At this time, each of A to F looks like one crystal grain. This is because a defect such as a slip occurs in a region where A to F collide with each other and becomes a crystal grain boundary.

FIG. 3B shows a simplified diagram in which a part of the regions A to F is enlarged. As shown in FIG. 3 (B), when viewed microscopically, a plurality of columnar or needle-like crystals are formed in the regions A to F, and these are densely packed, so that they are macroscopically It looks like one crystal grain like 3 (A).

Each of the columnar or needle-like crystals is a monodomain which can be regarded as a substantially single crystal having no crystal grain boundary inside.

Further, since each crystal grows while excluding the impurity element such as nickel from the inside thereof, metal silicide is formed on the crystal surface, which is indicated by 30 in FIG. 3 (B).
A metal element, that is, nickel, is segregated at the crystal grain boundaries as shown by 3.

Therefore, in the state of FIG. 3B, only a plurality of monodomains are assembled, and although the crystallinity is relatively good, each of the regions A to F is not a single monodomain region. Absent.

In order to realize the present invention, this lateral growth region 30 is used.
The step of improving the crystallinity of No. 2 is required. In this specification, this step is particularly referred to as a single crystallization step. The details of the process will be described below with reference to FIG.

The single crystallization step is specifically a heat treatment step performed in an oxidizing atmosphere containing a halogen element. (Second heat treatment)

First, the crystalline silicon film 109 obtained through the above steps is subjected to a heat treatment at a higher temperature. The temperature range of heat treatment is 700 to 1100 ° C, typically 800
The treatment time is 1 to 24 hours, typically 6 to 12 hours. At this time, it is important that the processing atmosphere is an atmosphere containing a halogen element. (Fig. 2 (A))

In this embodiment, the content is 3% with respect to the oxygen atmosphere.
The heat treatment is performed at 950 ° C. for 6 hours in the atmosphere containing HCl at the concentration (volume concentration). Introducing nitrogen into the atmosphere to slow down the oxide film formation rate is effective for obtaining a sufficient gettering effect.

In this embodiment, the halogen element is C
Although an example in which HCl gas is selected and HCl gas is used as the introduction method has been shown, HF, NF ₃ , H
One or more selected from Br, Cl ₂ , F ₂ and Br ₂ can be used. In general, a hydride or an organic substance (hydrocarbon) of a halogen can also be used.

By this heat treatment, as shown in FIG. 2 (B), nickel in the crystalline silicon film is gettered by the action of chlorine, and is taken into the thermal oxide film 110 or released into the atmosphere. To be removed. Therefore, nickel inside the crystalline silicon film 109 is removed, and the crystalline silicon film 111 from which nickel is removed is obtained.

The nickel removed in the gettering step is crystal grain boundary (304 in FIG. 3B) during crystallization.
(Shown by) is segregated by being extruded into. That is, it is considered that nickel silicide was present at the crystal grain boundaries.

Nickel existing as silicide is released as volatile nickel chloride, and a large number of dangling bonds of silicon, which has been disconnected from nickel, exist at the crystal grain boundaries.

However, since the above process is performed at a relatively high temperature of 950 ° C., the dangling bonds formed are recombined between silicon. Further, the dangling bonds that cannot be supplemented are terminated by hydrogen and halogen elements contained in the crystalline silicon film 111. Therefore, the crystalline silicon film 111 contains 5 atomic% or less of hydrogen and halogen elements.

Therefore, the dangling bonds formed by the above process are bonded with good consistency by bonding silicon.
Virtually no grain boundaries exist. Furthermore, since crystal defects such as dislocations and stacking faults that are internal to the needle-shaped or columnar crystal are almost eliminated, the crystallinity of the originally columnar or needle-shaped crystal is remarkably improved.

The state at this time will be described while comparing FIG. 3 (B) and FIG. 3 (C). By subjecting the lateral growth region having the structure as shown in FIG. 3B to the heat treatment, nickel contained in the lateral growth region is gettered by the action of chlorine and removed to the outside of the film. .

At this time, the silicon atoms bonded to nickel are broken, forming many dangling bonds, but recombined with the adjacent silicon atoms during the heat treatment. (FIG. 3 (C))

Note that the broken line 304 in FIG. 3C indicates the bonding interface in which the crystal grain boundary 303 in FIG. 3B is once dissociated by the heat treatment and then recombined.

That is, in the individual regions A to F, the columnar or acicular crystals are recombined with each other with good conformity, and FIG.
As shown in (3), there is substantially no grain boundary. Therefore, each of the regions A to F shown in FIG. 3A contains almost no crystal grain boundary or an impurity element such as nickel inside,
In addition, it becomes a monodomain region in which crystal defects hardly exist.

It is noted that the nickel concentration in the mono-domain region is reduced from a few thousandth before the treatment to a fraction or less by SIMS (secondary ion mass spectrometry).
It is clarified by the analysis by.

Then, as shown in FIG. 2C, when the gettering of nickel is completed, the thermal oxide film 110 which has become the gettering site is removed. This prevents nickel from diffusing into the crystalline silicon film 111 again.

Through the above process, a crystalline silicon film 111 having a reduced nickel concentration as shown in FIG. 2C can be obtained. In this region, the heat treatment in a halogen atmosphere does not interfere with the manufacturing of semiconductor devices by nickel (1
× 10 ¹⁸ atoms / cm ³ or less, preferably 1 × 10 ¹⁷ atoms / cm ³
Hereinafter, more preferably 1 × 10 ¹⁶ atoms / cm ³ or less) is sufficiently removed, and the crystallinity is remarkably improved, and the monodomain region has a crystallinity comparable to that of a single crystal.

One of the structures of the present invention is to form an active layer of a semiconductor device represented by a thin film transistor by utilizing only the above-mentioned monodomain region.

FIG. 11 shows active layers arranged in a matrix on a substrate 21 having an insulating surface for manufacturing an active matrix type liquid crystal display device.

The region indicated by the broken line 22 is the place where the vertical growth region existed. Reference numeral 23 is a place where a crystal grain boundary formed by the lateral growth regions hitting each other exists. Since it cannot be confirmed after the active layer is formed, it is shown by a dotted line.

As shown in FIG. 11, the active layer 24 of the thin film transistor is formed in a matrix so as not to include the vertical growth region and the crystal grain boundaries.

FIG. 11 is a view seen locally, showing the base 2
The same is true for all active layers formed on 1. That is, the active layers of millions of thin film transistors are formed by using only the monodomain regions that do not include grain boundaries.

[Embodiment 2] In this embodiment, an active layer of a thin film transistor is formed by using the monodomain region obtained in the process shown in Embodiment 1. In this embodiment, the top gate type is taken as an example, but it can be easily applied to the bottom gate type by using a gate electrode having high heat resistance.

First, as shown in FIG. 4A, a semiconductor thin film including a monodomain region is formed according to the process shown in the first embodiment, and an active layer 403 including only the monodomain region is formed by patterning. . Incidentally, 401 is a quartz substrate as described in Example 1, and 402 is a silicon oxide film.

Next, a silicon oxide film 404 functioning as a gate insulating film is formed to a thickness of 1500Å by the plasma CVD method. It may be a silicon oxynitride film or a silicon nitride film.

Next, an aluminum film 405 for forming a gate electrode is formed to a thickness of 5000Å by a sputtering method. 0.2% scandium is contained in this aluminum film.
% By weight. In addition to aluminum, other metals such as tantalum and molybdenum may be used. Thus, the state shown in FIG. 4A is obtained.

After forming the aluminum film 405, a 100 Å thick anodic oxide film (not shown) is formed on the surface thereof. This anodic oxide film is formed by using an ethylene glycol solution containing 3% tartaric acid neutralized with aqueous ammonia as an electrolytic solution. That is, in this electrolytic solution, anodization is performed using the aluminum film 405 as an anode and platinum as a cathode.

The anodic oxide film formed in this step has a dense film quality and functions to improve the adhesion to the resist mask formed later.

Next, the aluminum film 405 is patterned to form an island-shaped aluminum film pattern 406 which serves as a base of the gate electrode. The resist mask (not shown) used at this time is left as it is. (FIG. 4
(B))

After obtaining the state shown in FIG. 4B, anodization is performed again using the aluminum film pattern 406 as an anode. Here, a 3% oxalic acid aqueous solution is used as the electrolytic solution. In this anodizing step, anodization proceeds only on the side surface of the aluminum pattern 406 due to the presence of a resist mask (not shown). Therefore,
An anodic oxide film is formed as indicated by 407 in FIG.

Also, the anodic oxide film 40 formed in this step
No. 7 has a porous shape, and its growth distance can be increased up to several μm.

The film thickness of the porous anodic oxide film 407 is set to 7,000 Å. The film thickness of the anodic oxide film 407 can be controlled by the anodic oxidation time.

The porous anodic oxide film 4 shown in FIG.
After forming 07, the resist mask not shown is removed. Then, by performing anodic oxidation again, a dense anodic oxide film 408 is formed. This anodic oxidation process is performed under the same conditions as those for forming the dense anodic oxide film described above.

However, the film thickness to be formed is 800 Å.
In this step, since the electrolytic solution enters the inside of the porous anodic oxide film 407, the anodic oxide film 408 is formed as shown in FIG. 4C.

If the thickness of this anodic oxide film is increased to 1500 Å or more, the offset gate region can be formed in the subsequent impurity ion implantation step.

This dense anodic oxide film 408 functions to suppress the generation of hillocks on the surface of the gate electrode 409 in a later step.

After forming the dense anodic oxide film 408,
In this state, impurity ions are implanted to form the source / drain regions. Here, P ions are implanted in order to manufacture an N-channel thin film transistor.

In this step, the source region 410 and the drain region 411, which are highly doped with impurities, are formed. (FIG. 4 (C))

Next, using a mixed acid obtained by mixing acetic acid, phosphoric acid and nitric acid, the porous anodic oxide film 407 is selectively removed, and then P ion ion implantation is performed again. This ion implantation is performed with a lower dose amount than when forming the source / drain regions.

As a result, low-concentration impurity regions 412 and 413 having a lower impurity concentration than the source region 410 and the drain region 411 are formed. Then, the region 414 is formed as a channel forming region in a self-aligning manner. (FIG. 4
(D))

After the above-described impurity ion implantation step, laser light, infrared light, or ultraviolet light is irradiated to anneal the region into which the ions have been implanted.

In this way, the source region 410, the low concentration impurity region 412, the channel forming region 414, the low concentration impurity region 413, and the drain region 411 are formed. Here, the low-concentration impurity region 413 is a region usually called an LDD (lightly doped drain region).

Here, the plasma hydrogenation treatment is performed in the range of 300 to 35.
It is effective to perform the treatment in the temperature range of 0 ° C. for 0.5 to 1 hour.
By this step, 5 atomic% or less (1 ×
10 ²¹ atoms / cm ³ or less), preferably 1 × 10 ¹⁵ to 1 ×
Hydrogen of 10 ²¹ atoms / cm ³ or less is added.

Since this hydrogen is active, it is possible to neutralize and remove the dangling bonds of silicon in the active layer 403 or the levels at the active layer / gate insulating film interface.

After the state shown in FIG. 4D is obtained in this way, an interlayer insulating film 415 is formed next. Interlayer insulating film 415
Is formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a resin film, or a stacked film of these films. It is preferable to use a silicon nitride film because hydrogen added in the previous step can be prevented from being released again to the outside of the device.

Then, contact holes are formed to form a source electrode 416 and a drain electrode 417. Pixel TFT in active matrix type liquid crystal display device
However, in the case of the circuit TFT used in the peripheral drive circuit, the extraction electrode from the gate electrode 409 also needs to be formed at the same time.

Further, heat treatment is performed in a hydrogen atmosphere at 350 ° C. to hydrogenate the entire element, and the thin film transistor shown in FIG. 4E is completed.

Since the active layer of the thin film transistor thus formed is composed of the mono-domain region, it exhibits a good field-effect mobility that can correspond to high-speed operation. In addition, since there is no segregation of crystal grain boundaries and nickel compounds in the channel region and the drain junction, a thin film transistor with excellent reliability can be manufactured.

[Embodiment 3] In this embodiment, the effect of the thermal oxidation step in the atmosphere containing a halogen element, which is performed when forming the monodomain region as described in Embodiment 1, will be described.

FIG. 6 shows the relationship between the vapor pressure of NiCl ₂ (nickel chloride), which is a compound of chlorine and nickel, and the temperature.

Since nickel chloride is a sublimation substance as shown in FIG. 6, when nickel in the crystalline silicon film is gettered by chlorine, it immediately becomes volatile.
As a result, the produced nickel chloride compound diffuses into the air or is taken into the thermal oxide film and escapes to the outside of the crystalline silicon film. In this way, the metal element such as nickel can be removed from the silicon film.

In this example, the electrical characteristics of the thin film transistor using the present invention and the electrical characteristics of the thin film transistor not using the present invention are compared. The electrical characteristics referred to here are Id-Vg curves (Id-V) in which the horizontal axis represents the gate voltage (Vg) and the vertical axis represents the drain voltage (Id).
g characteristic).

In FIG. 5, reference numeral 501 shows the electric characteristics of a thin film transistor using the present invention, and 502 shows the electric characteristics of a thin film transistor not using the present invention.
Specifically, reference numeral 502 is an electrical characteristic of a thin film transistor manufactured by a process in which heat treatment in an atmosphere containing a halogen element and subsequent nitrogen annealing are removed from the process of Example 1.

Comparing the characteristics of both transistors, it can be confirmed that the thin film transistor according to the present invention flows an on-current that is approximately 2 to 4 orders of magnitude higher, even if the gate voltage is the same. Note that the on-state current refers to a drain current flowing when the thin film transistor is in an on state (gate voltage range of 0 to 5 V in FIG. 5).

It can also be confirmed that the thin film transistor according to the present invention has a better subthreshold characteristic. The subthreshold characteristic is a parameter indicating the steepness of the switching operation of the thin film transistor, and it can be said that the steeper the rise of the Id-Vg curve when the thin film transistor switches from the off state to the on state, the better the subthreshold characteristic.

The subthreshold characteristic when the present invention is not used is around 350 mV / decade, whereas the subthreshold characteristic when the present invention is used is 100 mV / decade.
It is around decades. It can be said that the smaller this value is, the better the switching performance is. The field effect mobility, which is a measure of the operating speed of a transistor, is 80 to 100 cm ² / Vs when the present invention is not used, and 180 to 200 cm ² / Vs when the present invention is used. It can be said that the larger this value, the faster the operating speed of the transistor.

As described above, the effects of the present invention are obvious, and it is experimentally clear that the use of the present invention significantly improves the electrical characteristics of thin film transistors.

Example 4 In this example, the gettering effect of a metal element by chlorine will be described based on experimental data.

FIG. 7 shows the results of measuring the chlorine concentration distribution in the cross-sectional direction of the crystalline silicon film obtained by using nickel. This measured value is obtained by SIMS (secondary ion mass spectrometry).

The measured data in the vicinity of the surface is not significant because it is affected by the surface irregularities and adsorbed substances. Further, for the same reason, some error is included in the data near the interface.

As is clear from FIG. 6, chlorine is concentrated near the interface between the crystalline silicon film and the thermal oxide film. It is presumed that this is because chlorine adsorbed on the surface of the crystalline silicon film at the time of starting the heat treatment was taken into the thermal oxide film while gettering nickel.

Further, since it is considered that many dangling bonds, so-called dangling bonds, existed on the surface of the crystalline silicon film before thermal oxidation formation, it was confirmed that these dangling bonds were terminated with chlorine. It seems to suggest.

[Embodiment 5] A structure in which a silicon oxide film is formed on a silicon substrate and a single crystal is formed thereon, so-called S
The OI structure has been receiving attention in recent years. The research on SOI structure is remarkable as a breakthrough of low power consumption.

Since the monodomain region according to the present invention has a crystallinity substantially equal to that of a single crystal, SO
It is easy to apply to I technology. In this embodiment, S
Contrast the problem left on the OI substrate with the present invention.

Problems associated with the SOI technology are summarized in FIG. As shown in FIG. 8, there are things related to crystallinity such as interface states and fixed charges in the silicon film, and external things such as metal contamination and boron concentration.

In the present invention, the crystalline silicon film is heat-treated in an atmosphere containing a halogen element, so that the silicon film is single-crystallized and the metal element is gettered at the same time.

First, metal contamination is easily removed by the gettering effect. This is due to the action of the halogen element, and as a result, it has a secondary action of increasing the number of dangling bonds of silicon atoms that have broken bonds with nickel.

Next, there is a single crystallization due to the annealing effect of the heat treatment. As this effect, factors that adversely affect the crystallinity such as pipe density, interface state, fixed charge, and threading transition can be removed or sufficiently reduced.

The precipitate in FIG. 8 can be removed by a gettering effect of a halogen element if it is a silicide type substance. Further, in the case of an oxide-based substance, it can be expected that oxygen is desorbed and diffused again by heat treatment and the oxide disappears.

[Embodiment 6] In this embodiment, an example in which the shape of the concave or convex pattern formed in the silicon oxide film serving as the buffer layer in Embodiment 1 is changed is shown.

In Example 1, a square fine island pattern was formed, but in this Example, a rectangular groove pattern is formed. Although the present embodiment is an example of forming a concave portion, the same effect can be obtained by forming a convex portion.

The crystallization process of the amorphous silicon film is the same as that of the first embodiment, and the description is omitted here. Here, FIG. 9 shows the shape of crystal grains when crystallized.

As shown in FIG. 9, a lateral growth region 902 is formed with the vertical growth region 901 as a crystal nucleus. The difference from Example 1 is that the crystal nuclei are regarded not as dots but as lines.

Therefore, the shape of the crystal grain is a substantially elongated hexagon as shown in FIG. This lateral growth region 902 is A to
It is divided into eight areas of H. However, the vertical growth region 90
1, the length Y is sufficiently longer than the lateral width X. Therefore, when actually formed on a quartz substrate, the regions A to C and F to H are negligibly smaller than the regions D and E.

The advantage of forming the concave or convex pattern in such a shape is that when the regions D and E are monodomain regions, a larger monodomain region than that in Example 1 can be obtained. That is, if the active layer of the thin film transistor is configured using only that region, it is possible to form a plurality of active layers having the same crystallinity in one monodomain region.

[Embodiment 7] This embodiment is an example of forming a CMOS structure with the TFT shown in Embodiment 2. FIG.
2 to 14 show the manufacturing process of this embodiment. Note that the crystalline silicon film formed according to the present invention has a wide range of applications.
The method of forming the OS structure is not limited to this embodiment.

First, according to the structure shown in Example 1, a silicon oxide film 32 is formed on a quartz substrate 31, and a crystalline silicon film having a monodomain region is obtained thereon. Then, by patterning it, an active layer 33 of the N-channel type TFT and an active layer 34 of the P-channel type TFT composed of only the mono domain region are obtained.

After forming the active layers 33 and 34, a silicon oxide film 35 functioning as a gate insulating film is formed by plasma CVD. Thickness is 500-2000Å, typically 1
000 to 1500Å. Further, as the gate insulating film, another insulating film such as a silicon oxynitride film or a silicon nitride film may be used.

Thus, the state shown in FIG. 12A is obtained.
Here, an example in which a pair of N-channel thin film transistors and P-channel thin film transistors is formed is shown for simplicity of description. Generally, an N-channel type thin film transistor and a P-channel type thin film transistor are formed in units of several hundreds or more on the same glass substrate.

When the state shown in FIG.
As shown in (B), an aluminum film 36 which will later form a gate electrode is formed.

This aluminum film contains scandium in an amount of 0.2 wt% in order to suppress the generation of hillocks and whiskers. The aluminum film is formed by a sputtering method or an electron beam evaporation method.

Hillocks and whiskers are barbed or needle-shaped protrusions resulting from abnormal growth of aluminum. The presence of hillocks or whiskers causes short circuits or crosstalk between adjacent wirings or between wirings separated by an upper limit.

As a material other than the aluminum film, anodizable metal such as tantalum can be used.

After forming the aluminum film 36, anodization is performed in the electrolytic solution using the aluminum film 36 as an anode to form a thin and dense anodic oxide film 37.

Here, an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia is used as an electrolytic solution. By using this anodizing method, an anodized film having a dense film quality can be obtained. The film thickness can be controlled by the applied voltage.

Here, the thickness of the anodic oxide film 37 is 100Å
Degree. The anodic oxide film 37 has a role of improving the adhesion with a resist mask formed later. Thus, the state shown in FIG. 12B is obtained.

Next, resist masks 38 and 39 are formed. Then, using the resist masks 38 and 39, the aluminum film 36 and the anodic oxide film 37 on the surface thereof are patterned. Thus, the state shown in FIG. 12C is obtained.

Next, using 3% oxalic acid aqueous solution as an electrolytic solution, anodic oxidation is performed with the patterns 40 and 41 made of the aluminum film remaining in this solution as anodes.

In this anodic oxidation process, the anodic oxidation selectively progresses on the side surfaces of the remaining aluminum films 40 and 41. This is because the dense anodic oxide film and the resist masks 38 and 39 remain on the upper surfaces of the aluminum films 40 and 41.

Further, in this anodic oxidation, the anodic oxide films 42 and 43 having a porous (porous) film quality are formed. Further, the porous anodic oxide films 42 and 43
Can be grown to about several μm.

In the present embodiment, the progress distance of this anodic oxidation,
That is, the film thickness is 7,000 Å. The length of the low-concentration impurity region will be determined later by the progress distance of this anodic oxidation. Empirically, the growth distance of this porous anodic oxide film is 6000Å
It is desirable to set it to ~ 8000Å. Thus, FIG.
The state shown in (D) is obtained.

In this state, the gate electrodes 1 and 2 are defined. After obtaining the state shown in FIG. 12D, the resist masks 38 and 39 are removed.

Next, anodic oxidation is performed again using an ethylene glycol solution containing 3% tartaric acid neutralized with ammonia as an electrolytic solution. In this step, the electrolytic solution penetrates into the porous anodic oxide films 42 and 43. As a result, dense anodic oxide films indicated by 44 and 45 in FIG. 12E are formed.

The thickness of the dense anodic oxide films 44 and 45 is set to 500 to 4000 Å. The film thickness is controlled by the voltage application time. The dense anodic oxide film 3 previously formed
The remaining portion of 7 is integrated with the anodic oxide films 44 and 45.

Next, in the state shown in FIG.
The entire surface is doped with P (phosphorus) ions as a type-imparting impurity.

This doping is 0.2-5 × 10 ¹⁵ / c
The dose is as high as m ² , preferably 1 to 2 × 10 ¹⁵ / cm ² . A plasma doping method or an ion doping method is used as the doping method.

As a result of the step shown in FIG. 12E, regions 46, 47, 48 and 49 in which P ions are implanted at a high concentration are formed.
Is formed.

Next, the porous anodic oxide films 42 and 43 are removed using aluminum mixed acid. At this time, the anodic oxide film 42,
The active layer region located immediately below 43 is substantially intrinsic because it is not ion-implanted.

Next, the resist mask 5 is formed so as to cover the element forming the P-channel type thin film transistor on the right side.
Form 0. Thus, the state shown in FIG. 13A is obtained.

When the state shown in FIG.
As shown in (B), P ions are implanted again. This P
The dose of ion implantation is 0.1 to 5 × 10 ¹⁴ / cm 3.
² , preferably a low value of 0.3 to 1 × 10 ¹⁴ / cm ² .

That is, the dose amount of P ion implantation performed in the step shown in FIG. 13B is lower than the dose amount performed in the step shown in FIG. 12E.

As a result of this step, the regions 52 and 54 become lightly doped low concentration impurity regions. Further, the regions 51 and 55 are high-concentration impurity regions in which P ions are implanted at a higher concentration.

In this step, the region 51 becomes the source region of the N-channel type thin film transistor. And 5
2 and 54 are low concentration impurity regions, and 55 is a drain region. The region indicated by 53 is a substantially intrinsic channel forming region. The region indicated by 54 is a region generally called an LDD (lightly doped drain) region.

Although not shown in particular, there is a region where the ion implantation is blocked by the anodic oxide film 44 between the channel forming region 53 and the low concentration impurity regions 52 and 54. This region is called an offset gate region and has a distance corresponding to the film thickness of the anodic oxide film 44.

Although the offset gate region is substantially intrinsic without being ion-implanted, it does not form a channel because a gate voltage is not applied and functions as a resistance component that relaxes the electric field strength and suppresses deterioration.

However, the distance (offset gate width)
Is short, it does not function as an effective offset gate region. Also, there is no clear boundary as to how far away it will work effectively.

Next, the resist mask 50 is removed, and a resist mask 56 covering the left N-channel type thin film transistor is formed as shown in FIG.

Next, in the state shown in FIG.
B (boron) ions are implanted as an impurity imparting a mold. Here, the dose amount of B ions is 0.2 to 10 × 1.
It is about 0 ¹⁵ / cm ² , preferably about 1 to 2 × 10 ¹⁵ / cm ² . This dose amount can be approximately the same as the dose amount in the step shown in FIG.

The regions 57 and 61 formed by this step include impurities imparting N-type and P-type, but are substantially pads (hereinafter referred to as contact pads) for making contact with the extraction electrodes. It has only the function of calling. That is, unlike the N-channel thin film transistor on the left side, the regions 57 and 61 are clearly distinguished from the source / drain regions.

The present inventors defined the source region as a region indicated by 58 and the drain region as a region indicated by 60 in the P-channel type thin film transistor.

These regions 58 and 60 are formed by implanting only B ions into the substantially intrinsic region.
Therefore, since other ions do not coexist, the impurity concentration can be easily controlled, and a PI junction with good compatibility can be realized. Further, the disorder of crystallinity due to ion implantation can be relatively small.

Although the offset gate region can be formed by using the anodic oxide film 45, it is empirically determined that P
Since the channel type thin film transistor hardly deteriorates,
It is not necessary to provide the offset gate region.

Thus, the source region 58 and the drain region 60 of the P-channel type thin film transistor are formed. Further, the region 59 is a channel forming region without any impurities being implanted. Further, as described above, 57 and 61 serve as contact pads for taking out current from the source region 58 and the drain region 60, respectively.

Next, after the step shown in FIG.
The resist mask 56 is removed to obtain the state shown in FIG. In this state, laser light irradiation is performed to activate the implanted impurities and anneal the regions where the impurity ions are implanted.

At this time, the source / drain regions of the N-channel type thin film transistor, which are indicated by a pair of 51 and 55, and the source / drain region of the P-channel type thin film transistor,
Irradiation with laser light can be performed in a state where the difference in crystallinity between the drain region 58 and the region indicated by the pair 60 is not so large.

The difference in crystallinity is not so large because the source / drain regions 58 and 60 of the P-channel type thin film transistor are not greatly damaged during the ion implantation in the step shown in FIG. 13C. Is.

Therefore, when laser light irradiation is performed in the state shown in FIG. 13D to anneal the source / drain regions of the two thin film transistors, the difference in annealing effect can be corrected. That is, the obtained N
The difference in characteristics between the P-channel thin film transistor and the P-channel thin film transistor can be corrected.

When the state shown in FIG. 13D is obtained, the state shown in FIG.
As shown in (A), an interlayer insulating film 62 is formed to a thickness of 4000Å. The interlayer insulating film 62 may be any of a silicon oxide film, a silicon oxynitride film, and a silicon nitride film, and may have a multilayer structure. A plasma CVD method or a thermal CVD method may be used as a method for forming these silicide films.

Next, contact holes are formed to form a source electrode 63 and a drain electrode 64 of an N-channel type thin film transistor (NTFT). At the same time, a source electrode 65 and a drain electrode 66 of a P-channel type thin film transistor (PTFT) are formed.

Patterning is performed so that the drain electrode 64 of the N-channel thin film transistor and the drain electrode 66 of the P-channel thin film transistor are connected to each other, and the gate electrodes of two TFTs are connected to each other to form a CMOS structure. You can do it. (Fig. 14
(B))

For example, the CMOS type thin film circuit as shown in this embodiment can be used for an active matrix type liquid crystal display device or an active matrix type EL display device.

Note that FIG. 12 (E), FIG. 13 (B), and FIG.
In the step of implanting the impurity ions shown in FIG. 3C, it is important that the active layer is covered with the silicon oxide film 35 forming the gate insulating film.

By implanting impurity ions in such a state, it is possible to suppress the surface of the active layer from being roughened or contaminated. This greatly contributes to improving the yield and the reliability of the obtained device.

[Embodiment 8] This embodiment shows an example in which the crystalline silicon film shown in Embodiment 1 is formed on a silicon wafer. In this case, it is necessary to provide an insulating layer on the surface of the silicon wafer, but usually a thermal oxide film is often used.

The temperature range of the heat treatment is generally 700 to 1300 ° C., and the treatment time varies depending on the desired oxide film thickness.

Further, thermal oxidation of a silicon wafer is usually O
₂ , O ₂ -H ₂ O, H ₂ O, O ₂ -H ₂ combustion or the like. Further, oxidation in an atmosphere to which a halogen element such as HCl or Cl ₂ is added is also widely used.

The silicon wafer is one of the essential substrates for semiconductor devices such as ICs, and techniques for forming various semiconductor elements on the wafer have been created.

According to this embodiment, a crystalline silicon film having crystallinity comparable to that of a single crystal can be combined with the conventional technique using a silicon wafer to further expand the range of application of the crystalline silicon film. .

[Embodiment 9] This embodiment shows an example of Embodiment 8 in which a TFT using a crystalline silicon film according to the present invention is formed on an IC formed on a silicon wafer. The outline of the manufacturing process will be described with reference to FIG.

FIG. 15A shows a MOS-FET formed on a silicon wafer by a normal process. Reference numeral 71 indicates a silicon substrate, and reference numerals 72 and 73 indicate insulating films for separating the elements from each other. Generally, a thermal oxide film is used.

Also, 74 is a source region and 75 is a drain region, which are formed through a diffusion process after implanting impurity ions imparting one conductivity type into the silicon substrate 71.
If the silicon substrate 71 is P type, an impurity (phosphorus) that imparts N type is implanted, and if the silicon substrate 71 is N type, an impurity (boron) that imparts P type is implanted.

Further, the region indicated by 76 is a channel forming region. A part of the thermal oxide film formed in the diffusion process after ion implantation is left on the silicon surface in this region by controlling the film thickness, and functions as a gate insulating film. Reference numeral 77 is a gate electrode made of a polycrystalline silicon film having one conductivity type.

The gate electrode 77 is an insulating film 7 such as a silicon oxide film.
It is covered with 8 and is not electrically short-circuited with the source electrode 79 and the drain electrode 80. (Fig. 15 (A))

After the state of FIG. 15A is obtained, an interlayer insulating film 81 is formed. A silicon oxide film, a silicon nitride film, or the like is used as this interlayer insulating film. After forming the interlayer insulating film 81, a contact hole is formed and a lead wiring 82 from the drain electrode is formed. (Fig. 15 (B))

After obtaining the state of FIG. 15B, the exposed surface is flattened by polishing by CMP (chemical mechanical polishing) technique or the like. By this step, the interlayer insulating film 81 is flattened, and the protruding portion of the take-out wiring 82 disappears.

In FIG. 15C, reference numeral 83 is a flattened interlayer insulating film, and 84 is a flat surface thereof. In addition, reference numeral 85 is a lead-out wiring having no convex portion, and a lead-out wiring 86 is formed in connection with the lead-out wiring.

The source electrode 79, the drain electrode 80, and the take-out wiring 86 must all be made of a material having heat resistance that can withstand up to about 1100 ° C.
This is in consideration of the formation temperature of the active layer formed later.

Next, an interlayer insulating film 87 is formed. The present invention can be applied on the interlayer insulating film 87. That is, a thin film transistor having an active layer formed by using a monodomain region is formed on the interlayer insulating film 87.

First, the active layer 88 formed of a monodomain region is formed according to the first embodiment. And the gate insulating film 8
9 is formed, and then the gate electrode 90 is formed. And
An impurity imparting one conductivity type is injected into the active layer.

After the impurity implantation is completed, sidewalls 91 for forming a low-concentration impurity region later are formed.
The sidewall 91 is formed according to the following steps.

First, an insulating film (not shown) made of a silicon oxide film or the like is formed so as to cover the gate electrode 90 and have a thickness equal to or larger than that of the gate electrode 90. Next, anisotropic etching is performed by dry etching to remove the formed insulating film, so that the insulating film remains only on the side surface of the gate electrode 90. This becomes the sidewall 91.

Impurity implantation is performed again in this state. Then, the region into which the impurity is implanted a second time becomes the source region and the drain region, and the region shielded by the sidewall becomes the impurity region having a lower concentration than the source region and the drain region. After implanting the impurities, the impurities are activated by heat treatment, laser light irradiation, or the like.

After the active layer is formed as described above, a silicon oxide film or a silicon nitride film is formed as an interlayer insulating film 92, contact holes are formed, and a source electrode 93 and a drain electrode 94 are formed.

As described above, by applying the present invention on an IC as shown in this embodiment, an integrated circuit having a three-dimensional structure as shown in FIG. 15D can be formed. According to the present invention, since the TFT formed above the IC has a performance comparable to that of the TFT formed on the single crystal, it is possible to realize a higher density integrated circuit than before without impairing the original performance of the IC. You can [Embodiment 10] In this embodiment, a TFT manufactured by applying the present invention is a DRAM (Dynamic Rondom Access Memory).
An example applied to is explained. FIG. 16 is used for the description.

The DRAM is a type of memory in which information to be stored is stored in a capacitor as an electric charge. The transfer of charge as information to and from the capacitor is controlled by a TFT connected in series to the capacitor. FIG. 16 shows a circuit of a TFT and a capacitor constituting one memory cell of a DRAM.
It shows in (A).

When a gate signal is applied by the word line 1601, the TFT indicated by 1603 becomes conductive. In this state, the capacitor 16
04 is charged with electric charges to read information, or electric charges are taken out from a charged capacitor to read information.

A sectional structure of the DRAM is shown in FIG. Reference numeral 1605 denotes a base made of a quartz substrate or a silicon substrate. If it is a silicon substrate, a so-called SOI structure can be formed.

A silicon oxide film 1606 is formed as a base film on the base 1605, and a TFT to which the present invention is applied is formed on the silicon oxide film 1606. Note that when the base 1605 is a silicon substrate, a thermal oxide film can be used as the base film 1606. Further, 1607 is an active layer composed of a mono domain region formed according to the first embodiment.

The active layer 1607 is covered with a gate insulating film 1608, on which a gate electrode 1609 is formed.
Then, after an interlayer insulating film 1610 is laminated thereon,
A source electrode 1611 is formed. This source electrode 16
At the same time as the formation of 11, the electrodes indicated by the bit lines 1602 and 1612 are formed. 1613 is a protective film made of an insulating film.

This electrode 1612 maintains a fixed potential, and a capacitor 1614 is formed between the electrode 1612 and the drain region of the active layer located therebelow. That is, the electric charge accumulated in this capacitor is written into or read from the TFT to have a function as a memory element.

The feature of the DRAM is that the number of elements constituting one memory is very small with only the TFT and the capacitor.
It is suitable for constructing large-scale memory with high integration density.
In addition, the price is kept low, so it is currently used in the largest amount.

For example, when an SOI structure to which the present invention is applied is formed on a silicon substrate, the junction area is small, so T
The leak current of the FT can be suppressed to a small value. This greatly contributes to the data retention time.

Further, as a characteristic of the DRAM cell formed on the SOI substrate, since the storage capacitance can be set small, it is possible to operate at a low voltage.

[Embodiment 11] In this embodiment, a TFT manufactured by applying the present invention is used as an SRAM (Static RondomAcces).
s Memory) will be described. FIG. 17 is used for the description.

The SRAM is a memory that uses a bistable circuit such as a flip-flop as a storage element, and is an O of the bistable circuit.
The binary information value (0 or 1) is stored corresponding to the two stable states of N-OFF or OFF-ON. This is advantageous in that memory is retained as long as power is supplied.

The memory circuit is composed of N-MOS and C-MOS. The SRAM circuit shown in FIG. 17A is a circuit using a high resistance as a passive load element.

Reference numeral 1701 is a word line,
1702 is a bit line. Reference numeral 1703 denotes a load element having a high resistance, and an SRAM is composed of two sets of driver transistors as indicated by 1704 and two sets of access transistors as indicated by 1705.

A cross-sectional structure of the TFT is shown in FIG.
A silicon oxide film 1707 is formed as a base film over a base 1706 formed of a quartz substrate or a silicon substrate, and a TFT to which the present invention is applied can be manufactured thereover. 170
Reference numeral 8 is an active layer composed of a monodomain region formed according to the first embodiment.

The active layer 1708 is covered with a gate insulating film 1709, and a gate electrode 1710 is formed thereon.
Then, after an interlayer insulating film 1711 is laminated thereon,
The source electrode 1712 is formed. This source electrode 17
The bit line 1702 and the drain electrode 1713 are formed at the same time as the formation of the bit line 12.

An interlayer insulating film 1714 is laminated again thereon, and then a polysilicon film 1715 is formed as a high resistance load. Reference numeral 1716 denotes a protective film made of an insulating film.

The characteristics of the SRAM having the above-described structure are that it can operate at high speed, has high reliability, and can be easily incorporated into a system.

[Embodiment 12] In this embodiment, the semiconductor device of Embodiment 2 and the CMOS structure of Embodiment 7 are used to integrate an active matrix region and a peripheral drive circuit for driving this active matrix region on the same substrate. An example is shown below.

One of the substrates constituting the integrated active matrix type liquid crystal display device has the following constitution. That is, in the active matrix area, at least one thin film transistor for switching is arranged in each of the pixels arranged in a matrix, and peripheral circuits for driving the active matrix area are arranged around the active matrix area. There is. All of these circuits are integrated on a single quartz substrate (or silicon substrate).

When the invention disclosed in this specification is used for such a structure, the active matrix region and the peripheral circuit can be formed by thin film transistors having performance comparable to that of a MOS-FET formed on a single crystal. .

That is, the thin film transistor shown in FIG. 4 constitutes the pixel TFT in the active matrix region, and the CMOS circuit shown in FIGS. 12 to 14 constitutes the peripheral circuit.

Since it is necessary for the thin film transistor arranged in the active matrix region to maintain the electric charge held in the pixel electrode for a predetermined time, it is desirable to make the off current value as small as possible.

Since the active layer of the thin film transistor according to the present invention is formed in the monodomain region, there is substantially no crystal grain boundary that can serve as a path (current path) through which the off current preferentially flows. Therefore, a thin film transistor with a small off-state current can be provided.

On the other hand, a CMOS circuit is often used as the peripheral drive circuit. And in order to improve its characteristics, C
It is necessary to make the characteristics of the N-channel type thin film transistor and the P-channel type thin film transistor forming the MOS circuit uniform as much as possible.

For such a purpose, the CMOS structure as shown in Embodiment 7 (see FIGS. 12 to 14) is optimum.

In this way, it is possible to obtain an integrated active matrix type liquid crystal display device having a structure in which each circuit has preferable characteristics.

[Embodiment 13] In this embodiment, an example in which the step of forming the gate insulating film is different from that in Embodiment 2 will be described.

First, a semiconductor thin film including a monodomain region is formed through the same steps as in Example 1, and then only the monodomain region is selectively utilized to form an active layer of a semiconductor device.

Next, 200 to 1500Å so as to cover the active layer.
An insulating film (silicon oxide film in this embodiment) having a thickness of (800 Å in this embodiment) containing silicon as a main component is formed by CVD or PV.
A film is formed by a vapor phase method typified by method D. At this time, the thickness of the silicon oxide film may be determined in consideration of the final withstand voltage. Further, a silicon oxynitride film or a silicon nitride film can be used instead of the silicon oxide film.

After the formation of the silicon oxide film is completed, the third heat treatment is again performed in an atmosphere containing a halogen element.
This heat treatment may be performed under the same conditions as the heat treatment (second heat treatment) in the atmosphere containing the halogen element in the first embodiment.

By the third heat treatment, the metal elements such as nickel remaining in the active layer are further reduced, and the crystallinity of the monodomain region is further improved accordingly. Also,
At the interface between the active layer and the silicon oxide film described above, a thermal oxidation reaction proceeds to form a thermal oxide film of about 200 Å. At that time, the final thickness of the active layer is 200 to 300 Å (typically
Setting it to 250 Å) is effective in reducing the off current.

In this embodiment, the heat treatment in the atmosphere containing the halogen element is followed by a nitrogen atmosphere,
By performing heat treatment at 950 ° C. for about 1 hr, the film quality of the thermal oxide film and the insulating film containing silicon as its main component is improved.

Further, as a result of performing the heat treatment in the atmosphere containing the halogen element, the halogen element remains at a high concentration near the interface between the active layer and the gate insulating film. According to SIMS measurement, it exists at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cm ³ .

Further, the thermal oxide film formed at the interface between the active layer and the above-mentioned silicon oxide film constitutes a gate insulating film together with the silicon oxide film. At this time, when the thermal oxide film is formed, the defect level at the interface of the active layer and the interstitial silicon atoms are reduced, so that the interface state between the active layer and the gate insulating film becomes very excellent.

Further, as described in Example 1, since the surface of the active layer is extremely flat, the thermal oxidation reaction proceeds uniformly and the thickness of the gate insulating film becomes uniform. This is preferable not only for improving the interface state but also for improving the breakdown voltage of the gate insulating film.

As described above, by carrying out this embodiment, not only the metal elements such as nickel are reduced, but also the interface state between the active layer and the gate insulating film is made extremely excellent, and excellent electrical characteristics are obtained. It is possible to realize a semiconductor device having high reliability.

Note that the second heat treatment shown in Embodiment 1 and the third heat treatment shown in this Embodiment can be simultaneously performed. For that purpose, the crystalline silicon film 109 (the crystalline silicon film before the second heat treatment) in Example 1 is patterned to form an active layer, and the constitution as in this example may be adopted.

[Embodiment 14] This embodiment is an example of improving the interface state between the active layer and the gate insulating film under the conditions different from those of the embodiment 12.

First, a semiconductor thin film including a monodomain region is formed through the same steps as in Example 1, and then only the monodomain region is selectively utilized to form an active layer of a semiconductor device. Then, as in Example 12, a silicon oxide film having a thickness of 200 to 1500 Å is formed by the CVD method or the PVD method.

Under this condition, the temperature is 500 to 700 ° C (typically 640
Heat treatment (~ 650 ℃). This temperature range is a temperature close to the lower limit at which thermal oxidation can be performed. Further, this heat treatment may be performed in an atmosphere containing only oxygen or an atmosphere containing a halogen element. Alternatively, the atmosphere may be a wet atmosphere containing water vapor.

When heat treatment is performed under the conditions of this embodiment,
If it is processed for about 5 to 2 hours, it will be less than several tens of liters (eg
Å) thermal oxide film is formed. Then, the growth of the thermal oxide film is substantially converged to this thickness.

According to the findings of the present inventors, fixed charges and defect levels are present near the polar interface between the active layer and the gate insulating film (region of about 10 to 30 Å from the interface toward the active layer side and the gate insulating film side). It is not an exaggeration to say that this region determines the interface state between the active layer and the gate insulating film, since the above concentration occurs.

Therefore, in order to obtain a good interface state between the active layer and the gate insulating film, only 10 to 30 Å of the active layer interface is required.
Area is thermally oxidized (active layer is reduced by 10 to 30Å
It is only necessary to eliminate the fixed charges and defect levels near the pole interface by forming a thermal oxide film of ~ 60Å). In other words, it is sufficient to form a thermal oxide film of less than several tens of liters in order to realize a good interface state.

In the thermal oxidation process as in this embodiment, since the processing temperature is low, it is possible to reduce the load on the device, and it is possible to improve the throughput of the semiconductor device manufacturing process.

[Embodiment 15] This embodiment shows an example in which a crystalline silicon film (polysilicon film) is used as a gate electrode. FIG. 19 is used for the description.

In FIG. 19A, 1901 is a glass substrate, 1902 is a base film, 1903 is an active layer formed of the monodomain region obtained in the process shown in Example 1, and 1904.
Is a gate insulating film, and 1905 is a gate electrode made of a polysilicon film having one conductivity.

Next, in this state, impurity ions for imparting one conductivity type to the active layer 1903 are implanted. Then, the impurity regions 1906, 1 are formed by this ion implantation process.
907 is formed.

After the implantation of impurity ions is completed, a silicon nitride film 1908 is formed to a thickness of 0.5 to 1 μm. The film forming method may be any of a low pressure thermal CVD method, a plasma CVD method and a sputtering method. Further, a silicon oxide film may be used instead of the silicon nitride film.

Thus, the state shown in FIG. 19B is obtained.
After the state of FIG. 19B is obtained, the silicon nitride film 19 is then formed.
08 is etched by the etch-back method and left only on the side wall of the gate electrode 1905. The silicon nitride film left in this way functions as a sidewall 1909.

At this time, the gate insulating film 1904 is removed except the region where the gate electrode 1905 and the sidewall 1909 serve as a mask, and remains in the state shown in FIG. 19C.

Then, impurity ions are implanted again in the state shown in FIG. At this time, the dose amount is set higher than the dose amount for the ion implantation. At the time of this ion implantation, the region 191 immediately below the sidewall 1909.
0 and 1911 are not ion-implanted, so that the impurity ion concentration does not change. However, the exposed area 19
12, 1913 are to be implanted with impurity ions of higher concentration.

Through the second ion implantation as described above, low concentration impurity regions (LDD regions) 1910 and 1911 having an impurity concentration lower than that of the source region 1912, the drain region 1913 and the source / drain regions are formed. Immediately below the gate electrode 1905 is an undoped region, which serves as a channel formation region 1914.

When the state of FIG. 19C is obtained through the above steps, a titanium film (not shown) having a thickness of 300 Å is formed, and the titanium film and the silicon film are reacted with each other. Then, after the titanium film is removed, heat treatment such as lamp annealing is performed, so that the source region 1912 and the drain region 19 are formed.
13. Titanium silicides 1915 to 1917 are formed on the exposed surface of the gate electrode 1905. (FIG. 19D)

In the above process, a tantalum film, a tungsten film, a molybdenum film or the like can be used instead of the titanium film.

Next, a silicon oxide film is formed as an interlayer insulating film 1918 to a thickness of 5000Å to form a source wiring 1919, a drain wiring 1920, and a gate wiring 1921. Thus, the TFT having the structure shown in FIG. 19D is completed.

The TFT of the structure shown in this embodiment has wiring and T
Since the connection with the FT is made through the titanium silicide layers 1915 to 1917, good ohmic contact can be realized.

[Embodiment 16] A semiconductor device in this specification refers to all devices that function by utilizing a semiconductor, and is an active matrix electro-optical device having a structure as shown in Embodiment 12. (Liquid crystal display devices, EL display devices, EC display devices, etc.) and applied products incorporating such electro-optical devices are also included in the category.

In this embodiment, the applied product will be described with reference to the drawings. Examples of semiconductor devices utilizing the present invention include TV cameras, head mounted displays, car navigations, projections (front and rear types), video cameras, personal computers and the like. A brief description will be given with reference to FIG.

FIG. 20A shows a mobile computer, which has a main body 2001, a camera section 2002, and an image receiving section 200.
3, an operation switch 2004, and a display device 2005. The present invention is applied to the display device 2005 and an integrated circuit incorporated in the device.

FIG. 20B shows a head mount display, which is composed of a main body 2101, a display device 2102, and a band portion 2103. Two display devices 2102 having a relatively small size are used.

FIG. 20C shows a car navigation system, which includes a main body 2101, a display device 2102, and operation switches 2.
103 and an antenna 2104. The present invention can be applied to the display device 2102 and an integrated circuit inside the device. The display device 2202 is used as a monitor, but since the main purpose is to display a map, it can be said that the allowable range of resolution is relatively wide.

FIG. 20D shows a mobile phone, which is a main body 23.
01, voice output unit 2302, voice input unit 2303, display device 2304, operation switch 2305, antenna 230
6. The present invention can be applied to the display device 2304 and an integrated circuit inside the device.

FIG. 20E shows a video camera, which has a main body 2401, a display device 2402, a voice input section 2403, operation switches 2404, a battery 2405, and an image receiving section 24.
06. The present invention can be applied to the display device 2402 and an integrated circuit inside the device.

FIG. 20F shows a front projection, which comprises a main body 2501, a light source 2502, a reflection type display device 2503, an optical system (including a beam splitter and a polarizer) 2504, and a screen 2505.
Since the screen 2505 is a large screen used for presentations such as conferences and conference presentations, the display device 2503 is required to have high resolution.

In addition to the electro-optical device shown in this embodiment, it can be applied to portable information terminal equipment such as rear projection and handy terminal. As described above, the application range of the present invention is extremely wide, and the present invention can be applied to display media in all fields.

[0287]

EFFECTS OF THE INVENTION The present invention is characterized in that the crystal grain size can be controlled by intentionally forming a site serving as a crystal nucleus.
A major feature is that the crystal grains thus formed having a relatively large crystal grain size are heat-treated in an atmosphere containing a halogen element.

As an effect of these techniques, it is possible to form a monodomain region which can be regarded as a substantially single crystal on a substrate having an insulating surface. That is, it becomes possible to form an active layer of a semiconductor device such as a thin film transistor using a crystalline silicon film having crystallinity comparable to that of a single crystal.

Therefore, it is possible to construct a semiconductor circuit having performance comparable to that of an integrated circuit using a known single crystal wafer.

[Brief description of drawings]

FIG. 1 is a diagram showing a process of forming a semiconductor thin film having a monodomain region.

FIG. 2 is a diagram showing a process for forming a semiconductor thin film having a monodomain region.

FIG. 3 is a diagram showing the structure of a monodomain region.

4A to 4C are diagrams illustrating a manufacturing process of a semiconductor device.

FIG. 5 is a diagram showing electric characteristics of a thin film transistor.

FIG. 6 is a diagram showing the relationship between vapor pressure and temperature of nickel chloride.

FIG. 7 is a diagram showing a chlorine concentration distribution in a crystalline silicon film.

FIG. 8 is a diagram showing problems in SOI technology.

FIG. 9 is a diagram showing the structure of a monodomain region.

FIG. 10 is a diagram showing a process for forming a crystalline semiconductor thin film.

FIG. 11 is a diagram showing an active layer formed in a monodomain region.

FIG. 12 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 13 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 14 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 15 is a diagram showing a manufacturing process of a semiconductor device.

FIG. 16 is a diagram showing a configuration of a DRAM;

FIG. 17 is a diagram showing a configuration of SRAM.

FIG. 18 is a diagram showing a composition table of an artificial quartz target.

FIG. 19 illustrates a manufacturing process of a semiconductor device.

FIG. 20 is a diagram for explaining an example of an applied product.

[Explanation of symbols]

 101 quartz substrate or silicon substrate 102 silicon oxide film 103 concave or convex pattern 104 amorphous silicon film 105 nickel layer 106 concave or convex portion 107 vertical growth region 108 lateral growth region 109 crystalline silicon film 110 thermal oxide film 111 crystalline silicon Film 301 Vertical growth region 302 Horizontal growth region 303 Crystal grain boundary 304 Bonding interface

Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical display location // H01L 21/205 H01L 29/78 616S 616A 627G (72) Inventor Kenji Fukunaga 398 Hase, Atsugi, Kanagawa Stocks Shares Company Semiconductor Energy Research Institute

Claims (35)

[Claims] 1. A semiconductor thin film formed on a substrate having an insulating film on the surface thereof, wherein the semiconductor thin film comprises a monodomain region formed by collecting a plurality of columnar or acicular crystals substantially parallel to the substrate. The semiconductor thin film, wherein the insulating film in contact with the lower surface of the semiconductor thin film is provided with an intentionally formed concave or convex pattern. 2. The semiconductor thin film according to claim 1, wherein the monodomain region is substantially free of crystal grain boundaries. 3. A semiconductor thin film formed on a substrate having an insulating film on the surface thereof, wherein the semiconductor thin film has a monodomain region substantially free of crystal grain boundaries, and the monodomain region is the substrate. Is formed by collecting a plurality of columnar or needle-like crystals substantially parallel to each other, and the insulating film in contact with the lower surface of the semiconductor thin film is provided with a deliberately formed concave or convex pattern. Thin film. 4. A step of forming a silicon oxide film on a substrate having an insulating surface by a sputtering method, a step of patterning the silicon oxide film into a desired shape to intentionally form a concave or convex pattern, A step of forming an amorphous silicon film on the silicon oxide film by a low pressure thermal CVD method; and a step of holding a metal element that promotes crystallization in the silicon oxide film and / or the amorphous silicon film. , A step of transforming the amorphous silicon film into a crystalline silicon film by a first heat treatment, and a second heat treatment in an atmosphere containing a halogen element so that a halogen element is formed on the crystalline silicon film. It is produced by at least the steps of forming a thermal oxide film containing the same and transforming the crystalline silicon film into a mono-domain region, and removing the thermal oxide film. Semiconductor thin film. 5. A semiconductor thin film formed on a substrate having an insulating film on the surface thereof, wherein the semiconductor thin film is substantially a crystal formed by collecting a plurality of columnar or acicular crystals substantially parallel to the substrate. The semiconductor thin film has a monodomain region in which no grain boundary exists, and the insulating film in contact with the lower surface of the semiconductor thin film is provided with a concave or convex pattern intentionally formed. Contains hydrogen and a halogen element at a concentration of 5 atomic% or less, and the halogen element is an element selected from chlorine, bromine, and fluorine. 6. The semiconductor thin film according to claim 5, wherein the halogen element has a high concentration distribution near the surface of the semiconductor thin film. 7. The semiconductor thin film according to claim 1, wherein the monodomain region has a film thickness of 150 to 450 Å. 8. The semiconductor thin film forming the monodomain region according to claim 1, wherein hydrogen is 1 × 10 ^15.
A semiconductor thin film, which is added at a concentration of 1 × 10 ²¹ atoms / cm ³ . 9. The monodomain region according to claim 1, wherein the monodomain region is composed of two regions, one of which is a vertical growth region formed on a concave or convex pattern, and the other of which starts from the vertical growth region. 1. A semiconductor thin film, which is a lateral growth region in which crystal growth is performed in a direction substantially parallel to a silicon film surface, and the vertical growth region contains a metal element at a higher concentration than the lateral growth region. 10. When forming a semiconductor thin film on a substrate having an insulating film on its surface, a step of forming a silicon oxide film on the substrate having an insulating surface by a sputtering method, and forming the silicon oxide film into a desired shape. Patterning to intentionally provide a concave or convex pattern; a step of forming an amorphous silicon film on the silicon oxide film by a low pressure thermal CVD method; and the silicon oxide film and / or the amorphous silicon film. A step of holding a metal element that promotes crystallization in the film; a step of transforming the amorphous silicon film into a crystalline silicon film by the first heat treatment; a second step in an atmosphere containing a halogen element; At least a step of forming a thermal oxide film containing a halogen element on the crystalline silicon film by performing a heat treatment; and a step of removing the thermal oxide film, the second heating The method for manufacturing a semiconductor thin film characterized by allowed to shift the crystalline silicon film monodomain region by sense. 11. The method according to claim 10, wherein in the step of holding the metal element that promotes crystallization, the metal element is concentrated in a higher concentration than other areas due to surface tension in the peripheral area of the concave or convex pattern. A method for manufacturing a semiconductor device, comprising: 12. The semiconductor thin film according to claim 10, wherein the crystalline silicon film formed by the first heat treatment is formed by collecting a plurality of columnar or needle crystals substantially parallel to the substrate. Of manufacturing. 13. The method of manufacturing a semiconductor thin film according to claim 10, wherein the step of forming the silicon oxide film is performed by a sputtering method using an artificial quartz target. 14. The metal element for promoting crystallization according to claim 10, is Fe, Co, Ni, Ru, Rh, or P.
A method for manufacturing a semiconductor thin film, wherein one or more kinds selected from d, Os, Ir, Pt, Cu, and Au are used. 15. The atmosphere containing a halogen element according to claim 10, wherein an atmosphere of O ₂ is HCl, HF, HBr, Cl.
_{2. A} method for producing a semiconductor thin film, wherein one or more kinds of gases selected from ₂ , NF ₃ , F ₂ and Br ₂ are added. 16. The semiconductor according to claim 10, wherein the first heat treatment is performed in a temperature range of 500 to 700 ° C., and the second heat treatment is performed in a temperature range of 700 ° C. to 1100 ° C. Thin film manufacturing method. 17. A semiconductor device having an active layer made of a semiconductor thin film formed on a substrate having an insulating film on the surface thereof, wherein the semiconductor thin film is composed of a plurality of columnar or needle-like crystals substantially parallel to the substrate. And a concave or convex pattern intentionally formed on the insulating film in contact with the lower surface of the active layer composed of only the monodomain region. Semiconductor device. 18. The semiconductor device according to claim 17, wherein the active layer has substantially no crystal grain boundaries. 19. A semiconductor device having an active layer made of a semiconductor thin film formed on a substrate having an insulating film on its surface, wherein the semiconductor thin film is composed of a plurality of columnar or acicular crystals substantially parallel to the substrate. Has a monodomain region in which substantially no crystal grain boundaries are formed, and a concave or convex formed intentionally in the insulating film in contact with the lower surface of the active layer composed of only the monodomain region. A semiconductor device having a pattern. 20. A step of forming a silicon oxide film on a substrate having an insulating surface by a sputtering method, a step of patterning the silicon oxide film into a desired shape to intentionally form a concave or convex pattern, A step of forming an amorphous silicon film on the silicon oxide film by a low pressure thermal CVD method; and a step of holding a metal element that promotes crystallization in the silicon oxide film and / or the amorphous silicon film. A step of transforming the amorphous silicon film into a crystalline silicon film by a first heat treatment, and a step of subjecting the crystalline silicon film to a second heat treatment in an atmosphere containing a halogen element to contain a halogen element Formed at least at the same time as forming the thermal oxide film described above, and transforming the crystalline silicon film into a monodomain region; and removing the thermal oxide film. A semiconductor device characterized in that an active layer is constituted only by a semiconductor region. 21. When manufacturing a semiconductor device having an active layer made of a semiconductor thin film, a step of forming a silicon oxide film on a substrate having an insulating surface by a sputtering method, and patterning the silicon oxide film into a desired shape. Intentionally forming a concave or convex pattern, forming an amorphous silicon film on the silicon oxide film by a low pressure thermal CVD method, and the silicon oxide film and / or the amorphous silicon film. A step of holding a metal element that promotes crystallization, a step of transforming the amorphous silicon film into a crystalline silicon film by heat treatment, and a patterning of the crystalline silicon film to form an active layer. A step of forming an insulating film containing silicon as a main component so as to cover the active layer by a vapor phase method, and a heat treatment in an atmosphere containing a halogen element to form the active layer and the silicon. A step of forming a thermal oxide film at the interface with the insulating film as a component and transforming the active layer into a monodomain region by gettering and removing the metal element that promotes the crystallization from the active layer, And a step of improving the film quality of the insulating film containing silicon as a main component including the thermal oxide film by a heat treatment in a nitrogen atmosphere. 22. A semiconductor device having an active layer made of a semiconductor thin film formed on a substrate having an insulating film on the surface thereof, wherein the semiconductor thin film is a collection of a plurality of columnar or needle-like crystals substantially parallel to the substrate. Has a monodomain region in which substantially no crystal grain boundaries are formed, and a concave or convex formed intentionally in the insulating film in contact with the lower surface of the active layer composed of only the monodomain region. A pattern is provided, and the active layer contains hydrogen and a halogen element in a concentration of 5 atomic% or less, and the halogen element is an element selected from chlorine, bromine, and fluorine. Semiconductor device. 23. The semiconductor device according to claim 20, wherein the halogen element has a high concentration distribution near the surface of the semiconductor thin film. 24. The semiconductor device according to claim 17, wherein the active layer has a film thickness of 150 to 450 Å. 25. The hydrogen according to claim 17, wherein 1 × 10 ¹⁵ to 1 × 10 ²¹ atoms / cm 3 are contained in the active layer.
A semiconductor device characterized by being added at a concentration of ³ . 26. A semiconductor device having an active layer made of a semiconductor thin film on an insulating film formed above an IC integrated on a silicon substrate, wherein the semiconductor thin film is in a columnar shape substantially parallel to the base or There is a monodomain region formed by accumulating a plurality of needle-like crystals, and a concave or convex pattern intentionally formed in the insulating film in contact with the lower surface of the active layer composed of only the monodomain region. A semiconductor device which is provided. 27. The active layer according to claim 26, wherein hydrogen and a halogen element are contained in a concentration of 5 atom% or less, and the halogen element is an element selected from chlorine, bromine and fluorine. Semiconductor device. 28. When manufacturing a semiconductor device having an active layer made of a semiconductor thin film, a step of forming a silicon oxide film on a substrate having an insulating surface by a sputtering method, and patterning the silicon oxide film into a desired shape. Intentionally forming a concave or convex pattern, forming an amorphous silicon film on the silicon oxide film by a low pressure thermal CVD method, and the silicon oxide film and / or the amorphous silicon film. A step of holding a metal element that promotes crystallization, a step of transforming the amorphous silicon film into a crystalline silicon film by a first heat treatment, and an atmosphere containing a halogen element in the crystalline silicon film. At least a step of forming a thermal oxide film containing a halogen element by performing a second heat treatment therein, and a step of removing the thermal oxide film. The allowed shift a crystalline silicon film in monodomain region by forming a thermal oxide film containing, method for manufacturing a semiconductor device characterized by forming the active layer by using only the monodomain region. 29. When manufacturing a semiconductor device having an active layer made of a semiconductor thin film, a step of forming a silicon oxide film on a substrate having an insulating surface by a sputtering method, and patterning the silicon oxide film into a desired shape. Intentionally forming a concave or convex pattern, forming an amorphous silicon film on the silicon oxide film by a low pressure thermal CVD method, and the silicon oxide film and / or the amorphous silicon film. A step of holding a metal element that promotes crystallization, a step of transforming the amorphous silicon film into a crystalline silicon film by heat treatment, and a patterning of the crystalline silicon film to form an active layer. A step of forming an insulating film containing silicon as a main component so as to cover the active layer by a vapor phase method, and a heat treatment in an atmosphere containing a halogen element to form the active layer and the silicon. A step of forming a thermal oxide film at the interface with the insulating film as a component and removing the metal element that promotes the crystallization from the active layer by gettering, and removing the thermal oxide film by heat treatment in a nitrogen atmosphere. And a step of improving the film quality of the insulating film containing silicon as a main component, wherein the active layer is transformed into a monodomain region by heat treatment in an atmosphere containing the halogen element. Method for manufacturing device. 30. In Claim 28 or Claim 29,
Fabrication of a semiconductor device characterized in that, in the step of holding the metal element that promotes crystallization, the metal element is concentrated in a higher concentration than other areas due to surface tension in the peripheral area of the concave or convex pattern. Method. 31. In Claim 28 or Claim 29,
A method for manufacturing a semiconductor device, wherein the crystalline silicon film is formed by collecting a plurality of columnar or needle-like crystals that are substantially parallel to the substrate. 32. The method according to claim 28 or 29.
A method for manufacturing a semiconductor device, wherein the step of forming a silicon oxide film is performed by a sputtering method using an artificial quartz target. 33. The method according to claim 28 or claim 29.
Metal elements that promote crystallization include Fe, Co, Ni,
A method for manufacturing a semiconductor device, wherein one or more kinds selected from Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au are used. 34. The method according to claim 28 or claim 29.
The atmosphere containing the halogen element is HCl, H in the O ₂ atmosphere.
A method for manufacturing a semiconductor device, wherein one or more gases selected from F, HBr, Cl ₂ , NF ₃ , F ₂ , and Br ₂ are added. 35. The semiconductor according to claim 28, wherein the first heat treatment is performed in a temperature range of 500 to 700 ° C. and the second heat treatment is performed in a temperature range of 700 ° C. to 1100 ° C. Method for manufacturing device.