JPH02143417A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To leave single crystal unremoved only within recesses when a semiconductor device having an Si layer on an insulating layer is manufactured, by forming the insulating layer on an Si substrate, forming recesses in the regions of the insulating layer where elements are to be formed, depositing a polycrystalline Si layer on the whole surface including the recesses and melting and curing the polycrystalline Si to convert the same into single crystal. CONSTITUTION:An insulating layer 2 is formed on one surface of an Si substrate 2 either by thermal oxidation of the substrate 1 or by a CVD process. Recesses 16 are formed in element forming regions of the insulating layer so that each recess has configurations corresponding to those of the element to be formed there. A polycrystalline Si layer 3 is deposited on the whole surface including the recesses 16 and covered with an anti-reflection insulating layer 4. A laser beam 5 is applied to the surface so that the layer 3 is molten and cured to provide a single crystal Si layer. While the layer 3 is molten, the part of the layer 3 present on the layer 2 also flows into the recesses 16 whereby the surface is flattened substantially. Then, the single crystal Si layer other than the parts thereof present in the recesses 16 is removed by an RIE process such that only the single crystal Si as required is left unremoved within the recesses 16.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a method of manufacturing a semiconductor device. More specifically, a structure having a silicon layer on an insulating layer (hereinafter Sol
The present invention relates to a method for manufacturing a semiconductor device (hereinafter referred to as "structure").

(b) A semiconductor device having a conventional Sol structure is shown in FIGS. 3(a) to (e).
) is manufactured by the method shown in

First, an interlayer insulating film 2 is formed on a silicon substrate l, a polycrystalline silicon film 3 is formed on it, and an oxide film 4 for preventing beam reflection is formed on the top layer, and then the surface of this structure is An energy beam, such as a laser beam 5, is irradiated to the side (FIG. 2(a)) to melt and solidify the polycrystalline silicon film 3, thereby forming a single crystal silicon film 8.

Next, the uppermost antireflection film 4 is removed to expose the surface of the single crystal silicon film 8, and an oxide film 6 is formed over the entire surface thereof. Thereafter, the element region is exposed through a photorenost mask, and only the element region is formed by a method such as reactive ion etching (hereinafter referred to as RIE). On this oxide film 6, P S Ga4 is further formed on the entire surface by atmospheric pressure CVD, etc., and the film is uniformly removed from the entire surface by RIE to expose the surface of the oxide film 6. A Zidewall 7' of the PSG film 7 is formed around the periphery (FIG. 6(b)).

In this state, the single crystal silicon film 8 is etched by RIE to form the oxide film 6 and the sidewall P.
A single crystal silicon film 8° is formed leaving only the lower side of the SG film 7°. At this time, depending on the RIE conditions, a slight sidewall PSG film 7 is formed around the single crystal silicon film 8°.
′ can be inserted inside. Thereafter, the sidewall PSG film 7° is removed, only the peripheral portion of the single crystal silicon film 8° is exposed, and impurity 9 for preventing side channels is ion-implanted (FIG. 4(C)).

After that, the portion of the single crystal silicon film other than 8° is buried with an insulating film 10, the oxide film 6 is removed, and the single crystal silicon film 8″
(d) of the same figure.

Thereafter, an SO2 structure element is formed by a normal MOSFET forming method (FIG. 4(e)). FIG. 4 shows a partial plan view of the structure of this element.

(c) Problems to be Solved by the Invention As device miniaturization progresses, the channel width becomes narrower. Due to heat treatment during the formation process, it diffuses into the channel portion and changes the substrate concentration, which adversely affects device characteristics.

Further, in the conventional method, the process is complicated and requires a long time, which causes problems such as a decrease in reliability of device performance.

This invention was made in view of the above situation, and it is possible to miniaturize elements, improve the degree of integration, and provide highly reliable S.
The present invention aims to provide a method for manufacturing a semiconductor device having an OL structure.

(d) Means for Solving the Problems Thus, according to the present invention, an insulating layer is formed on a silicon substrate, a recess is formed in advance in the area where elements are to be formed in this insulating layer, and then a polycrystalline layer is formed on the insulating layer. After laminating silicon layers and melting and solidifying this polycrystalline silicon layer to form a single crystal silicon layer, the single crystal silicon layer is subjected to an etching treatment to form a single crystal silicon layer remaining only in the recessed portion. A method for manufacturing a semiconductor device is provided.

In the present invention, the formation of recesses in the insulating layer can be achieved by etching techniques commonly used in the field, such as RIE using a photoresist mask or the like. The above recess is
The shape, size, and depth are sufficient to form the intended element. This recess may be, for example, groove-shaped.

One feature of the present invention is that by adjusting the depth of the recess, the single crystal silicon layer formed in the recess can be formed flush with the insulating layer or lower than the surface of the insulating layer. be.

In this invention, a polycrystalline silicon layer is laminated by a known method such as a CVD method on the insulating layer in which the element region recesses are formed as described above. This polycrystalline silicon layer is then melted and solidified into a single crystalline silicon layer. This melting and solidifying condition is carried out under the usual conditions in the field.

The single crystal silicon layer on the insulating layer obtained as above is
It is removed by methods known in the art such as RYE. This removal is performed until the surface of the insulating layer other than the recessed portions is exposed. By the above removal, a single crystal silicon layer is formed only in the recess, and the single crystal silicon layer formed in one recess is separated from the single crystal silicon layer formed in another recess by an insulating layer. At the same time, isolation between elements is achieved.

In the present invention, the individual remaining monocrystalline silicon layers, obtained in isolation as described above, are formed with primary elements using materials and methods known in the art.

(e) Effect According to the present invention, a polycrystalline silicon layer is laminated on an insulating layer in which four parts for the intended element formation area are provided in advance, and by melting the silicon layer, silicon flows into the recessed part. Then, the insulating layer is covered with a single crystal silicon layer by solidification. At this time, a thick single crystal silicon layer is formed in the recess. Next, the covering single crystal silicon layer on the insulating layer is removed uniformly over the entire surface to expose the surface of the insulating layer, so that the single crystal silicon layer remains only in the recess.

The present invention will be described in detail below with reference to Examples, but the present invention is not limited thereby.

(f) Example Figure 1 (a) to (g) shows an example of the method of this invention.
FIG. 2, which is a step explanatory diagram showing the cross-sectional configuration four times, is a partial plan view explanatory diagram of an embodiment of a semiconductor device manufactured by the method of one example of the present invention.

In these figures, the semiconductor device includes a silicon substrate l, insulating layers 2 and 14, diffusion layers 13° and 8°, and a gate oxide film 1.
1, a gate electrode 12, and a wiring layer 15.

The manufacturing method will be explained.

An insulating layer 2 was formed on one surface of the silicon substrate 1. This formation may be performed by thermally oxidizing the silicon substrate 1, or may be formed by CVD or the like. Next, a recess 16 was formed in this insulating layer 2 in a shape corresponding to the intended element region (FIG. 1(a)). This formation can be performed by a method such as RIE in which exposure is performed through a photoresist mask.

Next, a silicon substrate is laminated on the insulating layer 2. First, a polycrystalline silicon layer 3 is laminated on the insulating layer, and an antireflection insulating layer 4 is formed on the polycrystalline silicon layer 3. After forming the polycrystalline silicon layer 3, a laser beam 5 is irradiated from above the insulating layer 4 to melt and solidify the polycrystalline silicon layer 3 to form a single crystal silicon layer (FIG. 2(b)). During the above melting, the molten silicon flows into the element region recess 16 formed in the insulating layer 2, and the surface of the single crystal silicon approaches a flat surface (FIG. 4(C)). After that, when the substrate silicon 8 is uniformly removed from the entire surface, the substrate silicon 8 is left only in the thickest part of the substrate silicon 8, that is, in the element region recess 16. The RIE method was used for this removal method. Next, an impurity 9 was implanted from the surface of the silicon substrate 8 to form a diffusion layer 8° (FIG. 4(d)).

Next, a gate oxide film 11 was formed on the upper surface of this diffusion layer 8°, and an electrode layer 12 made of doped polycrystalline silicon or various metals was laminated on the gate oxide film U. Next, by implanting impurity ions 13 from above this electrode, a diffusion layer 13' was formed (FIG. 2(e)).
.

An insulating layer 14 is further provided on the upper surface of the semiconductor layer of the structure obtained above.
A coating was formed ((f) in the same figure). This insulating layer 14 is CV
This is an oxide film formed using the D method, and a contact hole is formed in this oxide film.

Next, in the region including the contact hole, the wiring layer 15
was formed ((g) in the same figure). This wiring layer 15 is electrically connected to the diffusion layer 13° through a contact hole.

As described above, by forming the element region recess 16 in advance in the insulating layer 2, molten silicon flows into the insulating layer 2, and the polycrystalline silicon layer can be formed thickly in that portion. After this, by uniformly removing from the surface of the silicon layer,
It is now possible to easily separate devices by leaving only the silicon substrate 8 (single-crystal silicon layer) in the device region. By using thermal oxidation and hydrofluoric acid etching as the method for removing the silicon substrate 8, it is possible to align the height of the surface of the diffusion layer 8' and the insulating layer 2 (oxide film) in the surrounding area to the same height. Therefore, surface planarization and element isolation process can be realized at the same time. Furthermore, by adjusting the depth of the element region recess 16, it is also possible to form the insulating layer 2 around the diffusion layer 8' at a position higher than the surface of the diffusion layer 8'. This has the advantage that side channels of the gate can be prevented.

(G) Effects of the Invention According to the present invention, it is not necessary to implant impurity ions into the side wall of the silicon substrate to prevent side channels. In addition, it is possible to simultaneously perform planarization, which aligns the surface of the silicon substrate and the surface of the surrounding insulating layer to the same height, and isolation between elements.
The manufacturing process is simplified and the reliability of the semiconductor device can be improved.

As a result, the semiconductor device can be miniaturized efficiently, the degree of integration can be significantly improved, and the functionality of the semiconductor device can be improved.

[Brief explanation of the drawing]

FIGS. 1(a) to (g) show an embodiment of the method of this invention,
2 is an explanatory diagram of a partial planar configuration of an embodiment of a semiconductor device manufactured by the method of one example of the present invention, and FIGS. FIG. 4 is an explanatory diagram of the manufacturing process of the example, and FIG. 4 is a partial plane configuration explanatory diagram of the conventional example. !・・・・・・Silicon J[, 2, 4, 10, 14...Insulating layer, 3...
・Polycrystalline silicon layer, 5... Laser beam,
6... Oxide film, 7゛...
PSG film, 8... single crystal silicon layer, 8°, 13'... diffusion layer, 9.13... impurity ion implantation, ■1...
...Gate oxide film, 12...Gate electrode,
15...Wiring layer, I6...
・Concave part for element area. Diagram! 1 Figure (a) ~1 ~1 ~1

Claims (1)

[Claims] 1. After forming an insulating layer on a silicon substrate and forming a concave portion in advance in the area where elements are to be formed in this insulating layer, a polycrystalline silicon layer is laminated on the insulating layer, and this polycrystalline silicon layer is melted and solidified. 1. A method of manufacturing a semiconductor device, comprising: forming a single-crystal silicon layer by etching the single-crystal silicon layer, thereby forming the single-crystal silicon layer remaining only in the recessed portion.