JPH0330300B2 - - Google Patents
Info
- Publication number
- JPH0330300B2 JPH0330300B2 JP55178073A JP17807380A JPH0330300B2 JP H0330300 B2 JPH0330300 B2 JP H0330300B2 JP 55178073 A JP55178073 A JP 55178073A JP 17807380 A JP17807380 A JP 17807380A JP H0330300 B2 JPH0330300 B2 JP H0330300B2
- Authority
- JP
- Japan
- Prior art keywords
- insulator
- polycrystalline silicon
- film
- substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 27
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 239000010410 layer Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 238000002955 isolation Methods 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 238000000992 sputter etching Methods 0.000 claims description 8
- 239000011810 insulating material Substances 0.000 claims description 5
- 239000011241 protective layer Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 18
- 150000004767 nitrides Chemical class 0.000 description 7
- 238000001039 wet etching Methods 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 241000293849 Cordylanthus Species 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000011247 coating layer Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関するもので
あり、さらに詳しく述べるならば素子分離領域の
形成方法の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to an improvement in a method for forming an element isolation region.
素子分離は半導体装置の製造においては必須の
技術であり、古くは半導体基板上に絶縁膜を選択
的に形成して活性領域を囲み、多の活性領域から
分離していたが、最近は、窒化膜をマスクとして
選択酸化を行ない半導体基板表面に厚い酸化膜を
形成し、これを素子分離に用いるいわゆる
LOCOS法が多用されるようになつた。しかし、
このLOCOS法では素子分離酸化膜の縁がバード
ビークとなつて窒化膜と半導体基板の間に食い込
み、この部分の巾が全体の約1/2にも及ぶという
問題がある。そこで、１ミクロン程度の寸法の大
小が活性領域の微細化のため無視し得なくなつて
おり、この要請から提案された方法が素子分離領
域に狭い巾で且つ任意の深さにSiO2を埋め込む
ものである。この方法ではチヤネルカツト用イオ
ン注入を行ない、次にイオン注入領域をパターン
ニングしてシリコン基板に穴孔けを行ない、そし
てSiO2を基板全面にCVDにて被着しそしてウエ
ツトエツチにより、SiO2が穴の中に埋め込まれ
るようにSiO2を選択的に除去していた。この方
法では、パターンニングで孔けられた精度と一致
するようにSiO2が穴の中に埋め込まれるので、
バードビークのようなパターンニング精度以下の
絶縁層が得られるという不都合は見られない。し
かし、従来のSiO2埋込み法ではウエツトエツチ
によりSiO2の埋込み構造を得ているために、エ
ツチングの制御が容易ではなく、SiO2膜上面が
基板の穴孔け部で凹形を呈した場合にこの凹形が
最終構造でも残存するという問題が生じる。 Element isolation is an essential technology in the manufacture of semiconductor devices.In the past, an insulating film was selectively formed on a semiconductor substrate to surround the active region and isolate it from other active regions, but recently, nitride Selective oxidation is performed using the film as a mask to form a thick oxide film on the surface of the semiconductor substrate, and this is used for device isolation.
The LOCOS method has come into widespread use. but,
The problem with this LOCOS method is that the edge of the element isolation oxide film becomes a bird's beak that digs into the space between the nitride film and the semiconductor substrate, and the width of this part is about 1/2 of the total width. Therefore, dimensions of about 1 micron can no longer be ignored due to the miniaturization of active regions, and the method proposed in response to this demand embeds SiO 2 in a narrow width and arbitrary depth in the element isolation region. It is something. In this method, ion implantation for channel cutting is performed, then the ion implantation area is patterned and holes are made in the silicon substrate, SiO 2 is deposited on the entire surface of the substrate by CVD, and wet etching is performed to form holes in the silicon substrate. The SiO 2 was selectively removed so that it was embedded in the pores. In this method, SiO 2 is embedded into the holes to match the precision drilled during patterning.
There is no problem of obtaining an insulating layer that is less than the patterning accuracy as in Bird's Beak. However, in the conventional SiO 2 embedding method, the SiO 2 embedding structure is obtained by wet etching, which makes it difficult to control the etching. A problem arises in that this concave shape remains in the final structure.
本発明はこのような問題を解決することを主た
る目的としており、半導体基板に絶縁物を埋設し
て半導体素子を相互に分離する素子分離領域を形
成する方法であつて、前記半導体基板の絶縁物埋
込部を包含する領域に少なくとも絶縁物からなる
保護層と多結晶シリコン層とを順次積層して被覆
層を形成し、前記被覆層を選択的に除去して前記
半導体基板の絶縁物埋込部を表出し続いて絶縁物
埋込用孔部を前記基板に穿設し、前記基板上に絶
縁物を被着して該絶縁物の表面が前記多結晶シリ
コン層の上面より高くなるように前記絶縁物埋込
用孔部内に沈着させ、そして前記絶縁物上にレジ
ストを平坦に塗布し、しかる後に、前記絶縁物お
よびレジストの除去速度がそれぞれ略同一であ
り、かつ前記多結晶シリコンの除去速度に比し大
なるスパツタエツチにより、前記多結晶シリコン
層が表出するまで前記レジスト及び前記絶縁物を
逐次除去し、ついで、前記保護層が表出するまで
前記多結晶シリコン層を除去する工程を有するこ
とを特徴とする。 The main purpose of the present invention is to solve such problems, and the present invention provides a method for forming an element isolation region for separating semiconductor elements from each other by embedding an insulator in a semiconductor substrate. A covering layer is formed by sequentially laminating at least a protective layer made of an insulating material and a polycrystalline silicon layer in a region including the buried portion, and the covering layer is selectively removed to bury the insulating material in the semiconductor substrate. Then, a hole for embedding an insulator is formed in the substrate, and an insulator is deposited on the substrate so that the surface of the insulator is higher than the upper surface of the polycrystalline silicon layer. A resist is deposited in the hole for embedding the insulator, and a resist is applied flatly on the insulator, and then the removal rate of the insulator and the resist are substantially the same, and the polycrystalline silicon is removed. The resist and the insulator are sequentially removed by a sputter etch that is large compared to the speed, until the polycrystalline silicon layer is exposed, and then the polycrystalline silicon layer is removed until the protective layer is exposed. It is characterized by having.
以下、本発明方法の必須工程順にその特徴を説
明する。 Hereinafter, the characteristics of the method of the present invention will be explained in order of essential steps.
先ず、多結晶シリコン層を含む被覆層を形成す
るが、この事は従来法の如く直接SiO2膜を被着
埋込みするのではなく、一旦被覆層を形成するこ
とを意味する。次に、この被覆層を選択的に表出
して半導体基板を表出し、続いて絶縁膜埋込用孔
部を穿設する。したがつてこの工程では被覆層が
絶縁膜埋込用孔部以外に残存している。続いて、
SiO2などの絶縁膜を被板上面から被着すると、
SiO2は被覆層上にもまた孔部内にも被着する。
この段階ではSiO2膜は孔部で平坦になつていな
いために、ホトレジストをSiO2膜全面に平坦に
塗布し、最後の工程でスパツタエツチを行なう。
スパツタエツチの速度はSiO2等の絶縁膜及びホ
トレジストに関してはほぼ物質の種類に関係なく
同じであるが、この速度は多結晶シリコンの速度
より著しく大きいという特色がある。そこで、最
終工程で多結晶シリコンが表出された時点でスパ
ツタエツチを停止することは容易であり、上面が
平坦な埋込み構造を得ることができる。このよう
に本発明では溝内への絶縁物の充てんに先だつ
て、あらかじめ溝外に基板保護膜として働く絶縁
物膜と、充てん絶縁物をスパツタエツチでエツチ
バツクする際、多結晶Si膜を積層した被覆層を形
成しておく構成を採用することにより、多結晶Si
がエツチングストツパーとなるので、基板にダメ
ージを与えることなくウエツトエツチより制御性
の良いスパツタエツチを使つてエツチバツクして
平坦化ができ、又、この多結晶Siの下には絶縁物
保護膜が形成されているので、この多結晶Siの除
去の際にも、その後の熱処理等においても、基板
がダメージを受けたり、汚染されたりしない。 First, a covering layer including a polycrystalline silicon layer is formed, which means that the covering layer is once formed, rather than directly depositing and embedding a SiO 2 film as in the conventional method. Next, this coating layer is selectively exposed to expose the semiconductor substrate, and then a hole for embedding an insulating film is formed. Therefore, in this step, the coating layer remains in areas other than the hole for embedding the insulating film. continue,
When an insulating film such as SiO 2 is applied from the top surface of the substrate,
SiO 2 is deposited both on the cover layer and in the holes.
At this stage, the SiO 2 film is not flat at the hole, so photoresist is applied evenly over the entire surface of the SiO 2 film, and sputter etching is performed in the final step.
The speed of sputter etching is almost the same regardless of the type of material for insulating films such as SiO 2 and photoresists, but this speed is unique in that it is significantly higher than the speed for polycrystalline silicon. Therefore, it is easy to stop sputter etching when the polycrystalline silicon is exposed in the final step, and a buried structure with a flat top surface can be obtained. In this way, in the present invention, before filling the trench with an insulating material, an insulating film that serves as a substrate protection film is placed outside the trench, and when the filling insulating material is etched back by sputter etching, a coating made of a laminated polycrystalline Si film is formed. By adopting a structure in which layers are formed, polycrystalline Si
acts as an etching stopper, so it is possible to etch back and planarize using sputter etching, which has better control than wet etching, without damaging the substrate.Also, an insulating protective film is formed under this polycrystalline Si. Therefore, the substrate will not be damaged or contaminated during the removal of polycrystalline Si or during subsequent heat treatment.
以下、本発明の実施態様を図面により説明す
る。 Embodiments of the present invention will be described below with reference to the drawings.
第１図において１はシリコン基板である。シリ
コン基板１上に熱酸化法により生成されたSiO2
膜２、CVD法により生成された窒化（Si3N4）膜
３及び多結晶シリコン膜４が逐次形成され、これ
らが本発明の被覆層１０として用いられている。
窒化膜３は後述の熱処理工程での保護膜として使
用され、またSiO2膜２は窒化シリコン膜の密着
強度を高めるために形成されたものである。 In FIG. 1, 1 is a silicon substrate. SiO 2 generated by thermal oxidation method on silicon substrate 1
A film 2, a nitride (Si 3 N 4 ) film 3 produced by the CVD method, and a polycrystalline silicon film 4 are successively formed, and these are used as the covering layer 10 of the present invention.
The nitride film 3 is used as a protective film in a heat treatment step to be described later, and the SiO 2 film 2 is formed to increase the adhesion strength of the silicon nitride film.
第１図に示されている被覆膜１０をシリコン基
板１の上面に形成した後、常法によりウエツトエ
ツチ又はドライエツチの何れかを用いて埋込孔５
をシリコン基板１に巾約１ミクロンとして穿設す
る。なおこの以前に、多結晶シリコン膜４の表面
を酸化してもよい。 After forming the coating film 10 shown in FIG. 1 on the upper surface of the silicon substrate 1, the buried holes 5 are etched using either wet etching or dry etching according to a conventional method.
A hole with a width of about 1 micron is formed in the silicon substrate 1. Note that before this, the surface of the polycrystalline silicon film 4 may be oxidized.
続いて、第２図に示すように、埋込孔５の内部
を熱酸化法により薄く酸化して、酸化膜６を形成
することが好ましい。しかる後に、熱酸化法又は
CVD法により酸化膜（SiO2）膜を形成する。こ
の熱酸化法とCVD法とでは、後者の法が、厚膜
形成が可能であり、又深い孔の中にも均一に且つ
密にSiO2が沈積する点で好ましい。なお上記酸
化膜６が基板１と酸化膜７の間に介在していると
これらの界面における結晶・電気的特製が良好に
なる。 Subsequently, as shown in FIG. 2, it is preferable to thinly oxidize the inside of the buried hole 5 by thermal oxidation to form an oxide film 6. After that, thermal oxidation method or
An oxide film (SiO 2 ) film is formed using the CVD method. Of the thermal oxidation method and the CVD method, the latter method is preferable because it allows the formation of a thick film and allows SiO 2 to be deposited uniformly and densely even in deep holes. Note that when the oxide film 6 is interposed between the substrate 1 and the oxide film 7, the crystal and electrical characteristics at the interface between these will be improved.
酸化膜７の上にホトレジスト８を塗布した後、
スパツタエツチを行ない、次に第３図の矢印の方
向からスパツタエツチを行なうとイオンにより、
ホトレジスト８及び酸化膜７が除去され、第３図
に示された如き構造が得られる。この状態で多結
晶シリコン層４が表出されると、スパツタエツチ
の速度は急速に低下するから、上面に平坦な構造
が得られた時点でスパツタエツチを停止すること
ができる。 After coating the photoresist 8 on the oxide film 7,
If you perform a sputter etch and then perform a sputter etch from the direction of the arrow in Figure 3, the ions will cause
Photoresist 8 and oxide film 7 are removed, resulting in a structure as shown in FIG. When the polycrystalline silicon layer 4 is exposed in this state, the sputter etching speed is rapidly reduced, so that the sputter etching can be stopped when a flat structure is obtained on the top surface.
続いて、多結晶シリコン膜４ウエツトエツチ又
はドライエツチにより除去し、第４図の構造を得
る。この状態で900〜1100℃にて30分以上の熱処
理をドライ酸素又はウエツト酸素雰囲気中で行な
い、酸化膜７の構造をち密にする。なお窒化膜３
はシリコン基板１を酸化雰囲気から保護する機能
を担う。 Subsequently, the polycrystalline silicon film 4 is removed by wet etching or dry etching to obtain the structure shown in FIG. In this state, heat treatment is performed at 900 to 1100 DEG C. for 30 minutes or more in a dry oxygen or wet oxygen atmosphere to make the structure of the oxide film 7 dense. Note that the nitride film 3
has the function of protecting the silicon substrate 1 from an oxidizing atmosphere.
最後に、ウエツトエツチ又はドライエツチで窒
化膜３を除去し、またSiO2膜２も除去してMOS
の絶縁膜、その他の活性領域を形成する。 Finally, the nitride film 3 is removed by wet etching or dry etching, and the SiO 2 film 2 is also removed to form the MOS.
Insulating films and other active regions are formed.
以上の説明より、巾の狭い素子分離領域が平坦
に且つち密に生成されるので本発明によると半導
体装置の高集積化及び高信頼度化が格段と推進さ
れることが理解されよう。 From the above description, it will be understood that the present invention significantly promotes higher integration and reliability of semiconductor devices because narrow element isolation regions are formed flat and densely.
第１図ないし第５図は本発明方法の一具体例に
よる埋込型素子分離領域形成の工程を示してい
る。
１……シリコン基板、２……SiO2膜、３……
窒化膜、４……多結晶シリコン膜、７……酸化
膜、８……ホトレジスト、１０……被覆層。
1 to 5 show the steps of forming a buried type isolation region according to a specific example of the method of the present invention. 1...Silicon substrate, 2...SiO 2 film, 3...
Nitride film, 4... Polycrystalline silicon film, 7... Oxide film, 8... Photoresist, 10... Covering layer.
Claims (1)
相互に分離する素子分離領域を形成する方法であ
つて、 前記半導体基板の絶縁物埋込部を包含する領域
に少なくとも絶縁物からなる保護層と多結晶シリ
コン層とを順次積層して被覆層を形成し、前記被
覆層を選択的に除去して前記半導体基板の絶縁物
埋込部を表出し続いて絶縁物埋込用孔部を前記基
板に穿設し、前記基板上に絶縁物を被着して該絶
縁物の表面が前記多結晶シリコン層の上面より高
くなるように前記絶縁物埋込用孔部内に沈着さ
せ、そして前記絶縁物上にレジストを平坦に塗布
し、しかる後に、前記絶縁物およびレジストの除
去速度がそれぞれ略同一であり、かつ前記多結晶
シリコンの除去速度に比し大なるスパツタエツチ
により、前記多結晶シリコン層が表出するまで前
記レジスト、前記絶縁物を逐次除去し、ついで、
前記保護層が表出するまで前記多結晶シリコン層
を除去する工程を有することを特徴とする半導体
装置の製造方法。[Scope of Claims] 1. A method for forming an element isolation region for separating semiconductor elements from each other by embedding an insulator in a semiconductor substrate, the method comprising: at least insulating a region of the semiconductor substrate that includes an insulator-embedded portion; A protective layer made of silicon and a polycrystalline silicon layer are sequentially laminated to form a covering layer, and the covering layer is selectively removed to expose the insulating material buried portion of the semiconductor substrate. A hole is formed in the substrate, an insulator is deposited on the substrate, and the insulator is deposited in the hole for embedding the insulator so that the surface of the insulator is higher than the upper surface of the polycrystalline silicon layer. Then, a resist is applied flatly on the insulator, and then the insulator and the resist are removed at substantially the same rate, and the removal rate of the polycrystalline silicon is higher than that of the polycrystalline silicon by sputter etching. The resist and the insulator are sequentially removed until the polycrystalline silicon layer is exposed, and then,
A method for manufacturing a semiconductor device, comprising the step of removing the polycrystalline silicon layer until the protective layer is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17807380A JPS57102045A (en) | 1980-12-18 | 1980-12-18 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17807380A JPS57102045A (en) | 1980-12-18 | 1980-12-18 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57102045A JPS57102045A (en) | 1982-06-24 |
| JPH0330300B2 true JPH0330300B2 (en) | 1991-04-26 |
Family
ID=16042139
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17807380A Granted JPS57102045A (en) | 1980-12-18 | 1980-12-18 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57102045A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59215741A (en) * | 1983-05-24 | 1984-12-05 | Mitsubishi Electric Corp | Manufacture of semiconductor integrated circuit device |
| JPS59225543A (en) * | 1983-06-06 | 1984-12-18 | Mitsubishi Electric Corp | Formation of inter-element isolation region |
| US5229316A (en) * | 1992-04-16 | 1993-07-20 | Micron Technology, Inc. | Semiconductor processing method for forming substrate isolation trenches |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54589A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Burying method of insulator |
-
1980
- 1980-12-18 JP JP17807380A patent/JPS57102045A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54589A (en) * | 1977-06-03 | 1979-01-05 | Hitachi Ltd | Burying method of insulator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57102045A (en) | 1982-06-24 |
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