JPS5849027B2 - Manufacturing method for semiconductor integrated circuit devices - Google Patents

Manufacturing method for semiconductor integrated circuit devices

Info

Publication number
JPS5849027B2
JPS5849027B2 JP7336379A JP7336379A JPS5849027B2 JP S5849027 B2 JPS5849027 B2 JP S5849027B2 JP 7336379 A JP7336379 A JP 7336379A JP 7336379 A JP7336379 A JP 7336379A JP S5849027 B2 JPS5849027 B2 JP S5849027B2
Authority
JP
Japan
Prior art keywords
mask layer
silicon substrate
laminated
oxidation
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP7336379A
Other languages
Japanese (ja)
Other versions
JPS55165637A (en
Inventor
和雄 今井
一茂 峰岸
一秀 木内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP7336379A priority Critical patent/JPS5849027B2/en
Publication of JPS55165637A publication Critical patent/JPS55165637A/en
Publication of JPS5849027B2 publication Critical patent/JPS5849027B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Description

【発明の詳細な説明】 本発明は多数の半導体素子がそれ等に共通なシリコン基
板を用いて所要の回路を形成すべく集積形成され、この
場合シリコン基板の主面側に相隣る半導体素子間に延長
せる態様を以ってシリコン酸化物膜(例えば素子間分離
用絶縁層として利用し得る)が形成されてなるという構
成の半導体集積回路装置の製法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device in which a large number of semiconductor devices are integrated to form a required circuit using a common silicon substrate, and in this case, semiconductor devices adjacent to each other on the main surface side of the silicon substrate are integrated. The present invention relates to a method for manufacturing a semiconductor integrated circuit device in which a silicon oxide film (which can be used, for example, as an insulating layer for isolation between elements) is formed in a manner that extends between the elements.

斯種半導体集積回路装置として従来、第1図に示す如く
、予め用意された第1図Aにで一般的に符号1で示され
ているシリコン基板の主面2上に所謂CVD法によって
第1図Bに示す如くSi3N+でなる耐酸化性被膜3を
形成し、次にこの耐酸化性被膜3に対する選択的エッチ
ング処理により第1図Cに示す如く耐酸化性被膜3によ
るマスク層4の多数を形威し、次にそれ等マスク層4を
マスクとせるシリコン基板1に対する熱酸化処理により
第1図Dに示す如くシリコン基板1の主百2側のマスク
層4下以外の領域に比較的厚いSi02でなるシリコン
酸化物膜5を形成し、然る后シリコン基板1のマスク層
4下の領域を半導体素子形成領域6としてその半導体素
子形成領域6内に、マスク層4を第1図Eに示す如くシ
リコン基板1の主面2上より除去して后、所要の半導体
素子を構成する所要の半導体領域(図示せず)を主面2
側より形成するという工程を含んで目的とせる半導体集
積回路装置を得るという製法が提案されている。
Conventionally, as shown in FIG. 1, this type of semiconductor integrated circuit device has been manufactured using a so-called CVD method to deposit a first layer on the main surface 2 of a silicon substrate, which is generally indicated by the reference numeral 1 in FIG. 1A, prepared in advance. As shown in FIG. 1C, an oxidation-resistant film 3 made of Si3N+ is formed, and then the oxidation-resistant film 3 is selectively etched, as shown in FIG. Then, by thermal oxidation treatment of the silicon substrate 1 using the mask layer 4 as a mask, as shown in FIG. A silicon oxide film 5 made of Si02 is formed, and then the area under the mask layer 4 of the silicon substrate 1 is used as a semiconductor element formation area 6, and the mask layer 4 is formed in the semiconductor element formation area 6 as shown in FIG. 1E. As shown, after removing from the main surface 2 of the silicon substrate 1, a required semiconductor region (not shown) constituting a required semiconductor element is removed from the main surface 2.
A manufacturing method has been proposed that includes a step of forming from the side to obtain a desired semiconductor integrated circuit device.

然し乍ら斯る従来の製法による場合、マスク層4が耐酸
化性被膜によるマスク層であってシリコン基板1との間
に比較的犬なる熱膨張係数の差を有する為、シリコン酸
化物膜5の形成時に半導体素子形成領域6に結晶歪を生
せしめ、依ってその半導体素子形成領域6を用いて構成
される半導体素子が予期せる良好な特性を有するものと
して得られないという欠点を有していた。
However, in the case of the conventional manufacturing method, since the mask layer 4 is a mask layer made of an oxidation-resistant film and has a relatively small difference in coefficient of thermal expansion from the silicon substrate 1, it is difficult to form the silicon oxide film 5. This method sometimes causes crystal distortion in the semiconductor element forming region 6, which has the disadvantage that a semiconductor element constructed using the semiconductor element forming region 6 cannot have expected good characteristics.

又従来第2図に示す如く、予め用意された第2図Aにて
一般的に符号1で示されているシリコン基板の主而2上
に所謂CVD法によって第2図Bに示す如<Si02で
なるシリコン酸化物被膜7及びSi3N4でなる耐酸化
性被膜3をそれ等の順に積層形成し、次にそれ等耐酸化
性被膜3及びシリコン酸化物被膜7に対する選択的エッ
チング処理により第2図Cに示す如くシリコン酸化物被
膜7によるマスク層8及びそれと丁度重なっている耐酸
化性被膜3によるマスク層9のそれ等の順に積層層され
てなる積層マスク層10の複数を形成し、次にそれ等積
層マスク層10をマスクとせるシリコン基板1に対する
熱酸化処理により第2図Dに示ス如くシリコン基板1の
主面2側の積層マスク層10下以外の領域に比較的厚い
シリコン酸化物膜5を形成し、然る后シリコン基板1の
積層マスク層10下の領域を半導体素子形成領域6とし
てその半導体素子形成領域6内に、積層マスク層10を
第2図Eに示す如くシリコン基板1の主面2上より除去
して后、所要の半導体素子を構成する所要の半導体領域
(図示せず)を主面2側より形成するという工程を含ん
で目的とせる半導体集積回路装置を得るという製法も提
案されている。
Furthermore, as shown in FIG. 2, a silicon substrate 2 (generally indicated by reference numeral 1 in FIG. 2A) prepared in advance is coated with <Si02> as shown in FIG. A silicon oxide film 7 made of the above and an oxidation resistant film 3 made of Si3N4 are laminated in that order, and then the oxidation resistant film 3 and the silicon oxide film 7 are selectively etched to form the structure shown in FIG. 2C. As shown in FIG. 2, a plurality of laminated mask layers 10 are formed by laminating a mask layer 8 made of a silicon oxide film 7 and a mask layer 9 made of an oxidation-resistant film 3 exactly overlaid thereon in this order, and then By thermal oxidation treatment of the silicon substrate 1 using the uniform laminated mask layer 10 as a mask, a relatively thick silicon oxide film is formed in the area other than under the laminated mask layer 10 on the main surface 2 side of the silicon substrate 1, as shown in FIG. 2D. After that, the area under the laminated mask layer 10 of the silicon substrate 1 is set as a semiconductor element formation area 6, and the laminated mask layer 10 is formed on the silicon substrate 1 within the semiconductor element formation area 6 as shown in FIG. 2E. The desired semiconductor integrated circuit device is obtained by removing the semiconductor device from the main surface 2, and then forming a required semiconductor region (not shown) constituting a required semiconductor element from the main surface 2 side. A manufacturing method has also been proposed.

然し乍ら斯る従来の製法による場合、積層マスク層10
がシリコン酸化物被膜によるマスク層8及び耐酸化性被
膜によるマスク層9のそれ等の順にシリコン基板1上に
積層されてなる構成を有し、而して耐酸化性被膜による
マスク層9とシリコン基板1との間の熱膨張係数の差が
比較的犬であるとしてもシリコン酸化物被膜によるマス
ク層8とシリコン基板1との間の熱膨張係数の差が十分
小であることによりシリコン酸化物膜5の形の時に半導
体素子形成領域6に結晶歪を生せしめるという第1図に
て上述せる従来の場合の欠点はこれを回避し得るも、シ
リコン酸化物膜によるマスク層8の存在の為にシリコン
酸化物膜5の形成時シリコン酸化物膜がシリコン基板1
の積層マスク層10下迄延長して形成され、従ってシリ
コン酸化物膜5が積層マスク層10下迄延長せる所謂バ
ースビークを有するものとして形或され、依ってシリコ
ン酸化物膜5を微細化すること、従って半導体集積回路
装置を全体として高密度化するに大きな妨げとなってい
るという欠点を有していた。
However, in the case of such a conventional manufacturing method, the laminated mask layer 10
has a structure in which a mask layer 8 made of a silicon oxide film and a mask layer 9 made of an oxidation-resistant film are laminated on the silicon substrate 1 in that order, and the mask layer 9 made of the oxidation-resistant film and the silicon Even if the difference in thermal expansion coefficient between the silicon oxide film and the silicon substrate 1 is relatively small, the difference in thermal expansion coefficient between the silicon oxide film mask layer 8 and the silicon substrate 1 is sufficiently small. Although it is possible to avoid the drawback of the conventional case described above in FIG. 1 that crystal distortion occurs in the semiconductor element formation region 6 when the film 5 is in the form of a silicon oxide film, the presence of the mask layer 8 made of a silicon oxide film When the silicon oxide film 5 is formed on the silicon substrate 1, the silicon oxide film is formed on the silicon substrate 1.
Therefore, the silicon oxide film 5 is formed to have a so-called birth beak that extends to below the laminated mask layer 10, thereby making the silicon oxide film 5 finer. Therefore, it has the disadvantage that it is a major hindrance to increasing the density of semiconductor integrated circuit devices as a whole.

更に従来第3図に示す如く、予め用意された第3図Aに
て一般的に符号1で示されているシリコン基板の主面2
上に所謂CVD法によって第3図Bに示す如くSiO2
でなる1シリコン酸化物被膜7を形威し、次にそのシリ
コン酸化物被膜7に対する選択的エッチング処理により
第3図Cに示す如くシリコン酸化物被膜7によるマスク
層8の複数を形或し、次にシリコン基板1の主面2に所
謂CVD法によって第3図Dに示す如くマスク層8上を
覆って連続延長せるSi3N,でなる耐酸化性被膜3を
形成し、次にその耐酸化性被膜3に対する選択的エッチ
ング処理により第3図Eに示す如く耐酸化性被膜3によ
るマスク層8のシリコン基板1側とは反対側の面上の部
9a、これと連接せるマスク層8の側面上の部9b及び
これと連接せるシリコン基板1の主面上の部9Cよりな
るマスク層8の複数を夫々覆ってなるマスク層9の複数
を形成し、次にそれ等マスク層9をマスクとせるシリコ
ン基板1に対する熱酸化処理により第3図Fに示す如く
シリコン基板1の主面2側のマスク層9下以外の領域に
比較的厚いシリコン酸化物膜5を形成し、然る后シリコ
ン基板1のマスク層9下の領域を半導体素子形成領域6
としてその半導体素子形成領域6内に、マスク層9及び
8を第3図Gに示す如く除去して后、所要の半導体素子
を構成する所要の半導体領域(図示せず)を主面2側よ
り形成するという工程を含んで目的とせる半導体集積回
路装置を得るという製法も提案されている。
Furthermore, as conventionally shown in FIG. 3, a main surface 2 of a silicon substrate, generally indicated by reference numeral 1 in FIG. 3A, prepared in advance.
As shown in FIG. 3B, SiO2
A silicon oxide film 7 is formed, and then a plurality of mask layers 8 are formed by the silicon oxide film 7 as shown in FIG. 3C by a selective etching process on the silicon oxide film 7. Next, as shown in FIG. 3D, an oxidation-resistant film 3 made of Si3N is formed on the main surface 2 of the silicon substrate 1 by a so-called CVD method, covering the mask layer 8 and continuously extending. By selectively etching the coating 3, as shown in FIG. 3E, the oxidation-resistant coating 3 forms a portion 9a on the surface of the mask layer 8 opposite to the silicon substrate 1 side, and a side surface of the mask layer 8 connected thereto. A plurality of mask layers 9 are formed each covering a plurality of mask layers 8 consisting of a portion 9b and a portion 9C on the main surface of the silicon substrate 1 connected thereto, and then these mask layers 9 are used as a mask. As shown in FIG. 3F, a relatively thick silicon oxide film 5 is formed on the main surface 2 of the silicon substrate 1 by thermal oxidation treatment on the silicon substrate 1 in a region other than under the mask layer 9, and then the silicon substrate 1 is heated. The area under the mask layer 9 is the semiconductor element forming area 6.
After removing the mask layers 9 and 8 as shown in FIG. A manufacturing method including a step of forming a semiconductor integrated circuit device to obtain a desired semiconductor integrated circuit device has also been proposed.

斯る従来の製法による場合、耐酸化性被膜によるマスク
層9がシリコン基板1上に形戒されたシリコン酸化物被
膜によるマスク層8上に形或され、そしてそれがマスク
層8を覆ってシリコン基板1上迄延長して形成されてい
ることにより、シリコン酸化物膜5が第2図につき上述
せる従来の製法の場合の如くに所謂バーズビークを有す
るものとして形成されるという欠点はこれを回避し得、
又マスク層9がシリコン基板1の主而2上に延長せる部
9cを有することにより半導体素子形成領域60部9c
下の領域に結晶歪を生せしめるとしても部9cの面積を
十分小として半導体素子形成領域60部9c下に占める
領域の面積を他の領域の面積に比し十分小とすれば、半
導体素子形成領域6での結晶歪の問題はこれを実質的に
回避し得るものである。
In the conventional manufacturing method, a mask layer 9 made of an oxidation-resistant film is formed on a mask layer 8 made of a silicon oxide film formed on a silicon substrate 1, and this mask layer 8 is covered with a silicon oxide film. By extending the silicon oxide film 5 to the top of the substrate 1, the drawback that the silicon oxide film 5 is formed with a so-called bird's beak as in the case of the conventional manufacturing method described above with reference to FIG. 2 can be avoided. Gain,
Furthermore, since the mask layer 9 has a portion 9c that can be extended over the main body 2 of the silicon substrate 1, a semiconductor element forming region 60 portion 9c is formed.
Even if crystal distortion occurs in the region below, if the area of the portion 9c is made sufficiently small and the area of the region occupied under the semiconductor element forming region 60 portion 9c is made sufficiently small compared to the area of other regions, the semiconductor element can be formed. The problem of crystal distortion in region 6 can be substantially avoided.

然し乍らシリコン基板1の主面上に形成されたマスク層
8を覆ってシリコン基板1上に延長せるマスク層9を形
成するを要する為、選択エッチング処理によりマスク層
8を得る工程即ちマスクを用いたパターンニングにより
マスク層8を得る工程と、同様にパターンニングにより
マスク層9を得る工程とを要し、しかも後者のマスク層
9をパターンニングにより得るにつきそのパターンニン
グにマスク層8との位置合せを要し、依ってシリコン酸
化物膜5を微細に得ることが困難であるという欠点を有
していた。
However, since it is necessary to form a mask layer 9 that covers the mask layer 8 formed on the main surface of the silicon substrate 1 and extends onto the silicon substrate 1, the process of obtaining the mask layer 8 by selective etching treatment, that is, using a mask, is necessary. It requires a step of obtaining the mask layer 8 by patterning and a step of obtaining the mask layer 9 by patterning, and when obtaining the latter mask layer 9 by patterning, alignment with the mask layer 8 is required during the patterning. Therefore, it has the disadvantage that it is difficult to obtain a fine silicon oxide film 5.

依って本発明は上述せる欠点のない新規な半導体集積回
路装置の製法を提案せんとするもので以下詳述する所よ
り明らかとなるであろう。
Therefore, the present invention proposes a novel method for manufacturing a semiconductor integrated circuit device free from the above-mentioned drawbacks, which will become clear from the detailed description below.

第4図は本発明による半導体集積回路装置の製法の一例
を示し、第1図〜第3図との対応部分には同一符号を附
して示すも、予め用意された第4図Aにて一般的に符号
1で示されているシリコン基板1の主面2上に例えばC
VD法によって第4図Bに示す如<Sin2でなるシリ
コン酸化物被膜T及びSi3N4でなる耐酸化性被膜3
をそれ等の順に積層して形成し、次に耐酸化性被膜3及
びシリコン酸化物被膜7に対する、それ等に対して共通
のマスクを用いた、各別の又はそれ等に対して共通の選
択的エッチング処理により第4図Cに示す如くシリコン
酸化物被膜7によるマスク層8及びそれと丁度重なって
いる耐酸化性被膜3によるマスク層9のそれ等の順に積
層されてなる積層マスク層10の複数を形成する。
FIG. 4 shows an example of a method for manufacturing a semiconductor integrated circuit device according to the present invention. Corresponding parts to those in FIGS. 1 to 3 are denoted by the same reference numerals. For example, C
A silicon oxide film T made of <Sin2 and an oxidation-resistant film 3 made of Si3N4 are formed by the VD method as shown in FIG. 4B.
are formed by stacking them in that order, and then the oxidation-resistant coating 3 and the silicon oxide coating 7 are formed using a common mask for each separate or common selection for them. A plurality of laminated mask layers 10 are formed by laminating, in this order, a mask layer 8 made of a silicon oxide film 7 and a mask layer 9 made of an oxidation-resistant film 3 exactly overlapping with the mask layer 8, as shown in FIG. 4C, by selective etching treatment. form.

次に第4図Dに示す如く積層マスク層10のシリコン基
板1側とは反対側の而及び側向上、及びシリコン基板1
の主面2上の積層マスク層10下以外の領域上に連続延
長せるSi3N4でなる耐酸化性被膜11を一挙に形成
し、次にその耐酸化性被膜11に対するスパツタエッチ
ング処理、反応性スパツタエッチング処理等による方向
性エッチング処理をなせば、耐酸化性被膜11のシリコ
ン基板1の主面2と平行に延長せる面を有する部従つて
積層マスク層10のシリコン基板1側とは反対側の面及
びシリコン基板1の主面2上に延長せる部がシリコン基
板1の主面2と垂直に延長せる面を有する部従って積層
マスク層10の側面上に延長せる部に比し大なる速度を
以ってエッチングされることに鑑み耐酸化性被膜11に
対するパターンニングなしの方向性エッチング処理をな
して耐酸化性被膜11を積層マスク層10の側面上の部
のみを残し他部を除去し、斯くて第4図Eに示す如き積
層マスク層10の側面上に耐酸化性被膜11によるシリ
コン基板1の主面2上に達するマスク層12を連続延長
せしめてなる構成の積層マスク層13の複数を形成する
Next, as shown in FIG.
An oxidation-resistant film 11 made of Si3N4 that is continuously extended on the main surface 2 of the main surface 2 other than under the laminated mask layer 10 is formed all at once, and then the oxidation-resistant film 11 is subjected to sputter etching treatment and reactive spacing. If directional etching treatment such as ivy etching treatment is performed, the portion of the oxidation-resistant coating 11 having a surface extending parallel to the main surface 2 of the silicon substrate 1, that is, the side opposite to the silicon substrate 1 side of the laminated mask layer 10 , and the portion that extends onto the main surface 2 of the silicon substrate 1 has a higher speed than the portion that has the surface that extends perpendicularly to the main surface 2 of the silicon substrate 1, and thus the portion that extends onto the side surface of the laminated mask layer 10. In view of the fact that the oxidation-resistant film 11 is etched by the process, a directional etching process is performed on the oxidation-resistant film 11 without patterning, leaving only the part on the side surface of the laminated mask layer 10 and removing the other part. Thus, a laminated mask layer 13 having a structure as shown in FIG. form a plurality.

次にそれ等積層マスク層13をマスクとするシリコン基
板1に対する熱酸化処理により第4図Fに示す如くシリ
コン基板1の主面2側の積層マスク層13下以外の領域
にシリコン酸化物膜5を形成し、然る后シリコン基板1
の積層マスク層13下の領域を半導体素子形成領域6と
してその半導体素子形成領域6内に、積層マスク層13
を第4図Gに示す如くシリコン基板1の主面2上より除
去して后、所要の半導体素子を構成する所要の半導体領
域(図示せず)を主面2側より形成する工程を含んで目
的とせる半導体集積回路装置を得る。
Next, by thermal oxidation treatment of the silicon substrate 1 using the laminated mask layer 13 as a mask, a silicon oxide film 5 is formed on the area other than under the laminated mask layer 13 on the main surface 2 side of the silicon substrate 1, as shown in FIG. 4F. After that, a silicon substrate 1 is formed.
The area under the laminated mask layer 13 is defined as a semiconductor element formation area 6, and the laminated mask layer 13 is formed in the semiconductor element formation area 6.
as shown in FIG. 4G from the main surface 2 of the silicon substrate 1, and then forming a required semiconductor region (not shown) constituting a required semiconductor element from the main surface 2 side. A desired semiconductor integrated circuit device is obtained.

以上が本発明による半導体集積回路装置の製法の一例で
あるが、斯る製法によれば、シリコン酸化物膜5の形成
時にマスクとして用いられる積層マスク層13が、シリ
コン酸化物被膜によるマスク層8及び耐酸化性被膜によ
るマスク層9のそれ等の順に積層されてなる積層マスク
層10の側面上にシリコン基板1の主面2に達する耐酸
化性被膜によるマスク層12を連続延長せしめてなる構
成を有し、従って積層マスク層13を構成せる耐酸化性
被膜によるマスク層9及び12よりなる構成が第3図に
て上述せる従来の製法に於けるマスク層9に対応してい
るので、第3図にて上述せる従来の製法の場合と同様に
、シリコン酸化物膜5が第2図にて上述せる従来の製法
の場合の如くに所謂バーズビークを有するものとして形
成されるという欠点はこれを回避し得ると共に、シリコ
ン酸化物膜5の形或時に於ける半導体素子形成領域6で
の結晶歪の問題もこれを実質的に回避し得るものである
The above is an example of the manufacturing method of the semiconductor integrated circuit device according to the present invention. According to this manufacturing method, the laminated mask layer 13 used as a mask when forming the silicon oxide film 5 is the mask layer 8 made of a silicon oxide film. A structure in which a mask layer 12 made of an oxidation-resistant film is continuously extended to reach the main surface 2 of the silicon substrate 1 on the side surface of a laminated mask layer 10 formed by laminating the mask layer 9 made of an oxidation-resistant film and the mask layer 9 made of an oxidation-resistant film. Therefore, the configuration of the mask layers 9 and 12 made of the oxidation-resistant coating that constitutes the laminated mask layer 13 corresponds to the mask layer 9 in the conventional manufacturing method described above in FIG. Similar to the conventional manufacturing method shown in FIG. 3, the drawback that the silicon oxide film 5 is formed with a so-called bird's beak as in the conventional manufacturing method shown in FIG. This can be avoided, and the problem of crystal distortion in the semiconductor element forming region 6 due to the shape of the silicon oxide film 5 can also be substantially avoided.

然し乍ら第3図にて上述せる従来の製法に於けるマスク
層9に対応せる耐酸化性被膜によるマスク層9及び12
よりなる構成を有する積層マスク層13が、積層マスク
層10を得、次で耐酸化性被膜11を形成し、然る后こ
れに対する方向性エッチング処理をなすという簡易な工
程で得られ、そしてその工程には積層マスク層10を得
る場合に選択エッチング処理をなす即ちパターンニング
処理をなすという1回のパターンニング処理を含む丈ゆ
であるので、第3図にて上述せる従来の製法の欠点なし
にシリコン酸化物膜5を微細に容易に得ることが出来る
犬なる特徴を有するものである。
However, as shown in FIG. 3, mask layers 9 and 12 made of an oxidation-resistant film corresponding to mask layer 9 in the conventional manufacturing method described above are shown in FIG.
The laminated mask layer 13 having the following structure can be obtained by a simple process of obtaining the laminated mask layer 10, then forming the oxidation-resistant coating 11, and then subjecting it to a directional etching treatment. Since the process includes a single patterning process in which a selective etching process is performed to obtain the laminated mask layer 10, the process does not have the drawbacks of the conventional manufacturing method described above in FIG. This method has the unique feature that the silicon oxide film 5 can be easily obtained in a fine structure.

同上述に於いては、シリコン酸化物膜5を形成する為の
マスクに用いられる積層マスク層13が積層マスク層1
0の側面に耐酸化性被膜11によるマスク層12を連続
延長せしめてなる構成を有するとする、その積層マスク
層10を、それを構成せるシリコン基板1側のマスク層
8をしてマスク層9と丁度重なる大いさを有するものと
して得た場合につき述べたが、詳細説明はこれを省略す
るも、第4図Cに対応せる第5図Aに示す如く積層マス
ク層10を、そのマスク層8をしてマスク層9に対して
サイドエッチングされたものとして得、次に第4図Dに
対応する第5図Bに示す如く耐酸化性被膜11を形成し
、次にその耐酸化性被膜11に対するパターンニングな
しの方向性エッチング処理により第4図Eに対応せる第
5図Cに示す如く積層マスク層13な、それを構成せる
マスク層12のマスク層8の側向上の部をして他の部よ
り厚さの大なるものとして得又は耐酸化性被膜11に対
する方向性を有さざる勿論パターンニングなしのエッチ
ング処理により第4図Eに対応せる第6図Aに示す如く
積層シリコン層13を、それを構成せるマスク層12を
してマスク層8の側面上にはシリコン基板1の主面2に
達して延長せるもマスク層9の側面上には延長せざるも
のとして得、次に第4図Fに対応せる第5図D又は第6
図Bに示す如く第4図Fにて上述せると同様にシリコン
酸化物膜5を形成し、然る后第4図Gに対応せる第5図
E又は第6図Cに示す如く積層マスク層13を除去して
目的とせる半導体集積回路装置を得る様になすことも出
来、斯くしても第4図に上述せると同様の特徴の得られ
ること明らかであろう。
In the above description, the laminated mask layer 13 used as a mask for forming the silicon oxide film 5 is different from the laminated mask layer 1.
The laminated mask layer 10 has a structure in which a mask layer 12 formed by an oxidation-resistant coating 11 is continuously extended on the side surface of the mask layer 9. Although the detailed explanation is omitted, as shown in FIG. 5A corresponding to FIG. Then, as shown in FIG. 5B corresponding to FIG. 4D, an oxidation-resistant coating 11 is formed, and then the oxidation-resistant coating 11 is By directional etching without patterning, as shown in FIG. 5C corresponding to FIG. The laminated silicon layer 13 is formed as shown in FIG. 6A, which corresponds to FIG. , the mask layer 12 constituting it can be extended onto the side surface of the mask layer 8 to reach the main surface 2 of the silicon substrate 1, but not onto the side surface of the mask layer 9. Figure 5 D or 6 corresponding to Figure 4 F
As shown in FIG. B, a silicon oxide film 5 is formed in the same manner as described above in FIG. 4F, and then a laminated mask layer is formed as shown in FIG. 5E or FIG. It is also possible to obtain the desired semiconductor integrated circuit device by removing 13, and it will be clear that the same characteristics can be obtained as shown in FIG. 4 in this case.

又上述に於ではシリコン酸化物膜5を積層マスク層13
をマスクとせるシリコン基板1に対する熱酸化処理によ
り形成する場合につき述べたが、詳細説明はこれを省略
するも、第4図Eに対応せる第7図Aに示す如くに積層
マスク層13を形成して后、それをマスクとしてシリコ
ン基板1に対する陽極酸化処理をなして第7図Bに示す
如くシリコン基板1の主面2側の積層マスク層13下以
外の領域内に多孔質シリコン膜14を形或し、次に積層
マスク層13をマスクとせる熱酸化処理をなして第7図
Cに示す如く多孔質シリコン層14の酸化されてなるシ
リコン酸化物膜15を第4図にて前述せるシリコン酸化
物膜5に代えたシリコン酸化物膜として形成し、然る后
第4図Gに対応せる第7図Dに示す如く積層マスク層1
3を除去して目的とせる半導体集積回路装置を得る様に
なすことも出来、斯くしても第4図にて上述せると同様
の特徴の得られること明らかであろう。
Furthermore, in the above description, the silicon oxide film 5 is laminated as a mask layer 13.
Although we have described the case in which the mask layer 13 is formed by thermal oxidation treatment on the silicon substrate 1 which serves as a mask, the detailed explanation thereof will be omitted, but the laminated mask layer 13 is formed as shown in FIG. 7A corresponding to FIG. 4E. After that, using this as a mask, the silicon substrate 1 is anodized to form a porous silicon film 14 in a region other than under the laminated mask layer 13 on the main surface 2 side of the silicon substrate 1, as shown in FIG. 7B. Then, a thermal oxidation treatment is performed using the laminated mask layer 13 as a mask to form a silicon oxide film 15 formed by oxidizing the porous silicon layer 14 as shown in FIG. 7C, as described above in FIG. A silicon oxide film is formed in place of the silicon oxide film 5, and then a laminated mask layer 1 is formed as shown in FIG. 7D corresponding to FIG. 4G.
It is also possible to obtain the desired semiconductor integrated circuit device by removing 3, and it will be clear that the same characteristics can be obtained as described above with reference to FIG.

更に上述に於では半導体素子形戒領域6に半導体素子を
形成する前迄の工程に於てシリコン酸化物膜5のみを形
成する場合につき述べたが、詳細説明はこれを省略する
も、第4図Cにて上述せる如〈に積層マスク層10を形
成する工程と、次に第4図Dにて上述せる如くに耐酸化
性被膜11を形成する工程との間で積層マスク層10を
マスクとせるシリコン基板1へのそれと同じ導電型を与
える不純物の導入処理をとって第4図Cにて点線図示の
如くシリコン基板1の主面側の積層マスク層10下以外
の領域にシリコン基板1と同じ導電型を有する半導体領
域20を形成し、又は第4図Eにて上述せる如くに積層
マスク層13を形成する工程と次にシリコン酸化物膜5
を形成する工程との間で積層マスク層13をマスクとせ
るシリコン基板1へのそれと同じ導電型を与える不純物
の導入処理をとって第4図Eにて鎖線図示の如くシリコ
ン基板1の主面側の積層マスク層13下以外の領域にシ
リコン基板1と同じ導電型を有する半導体領域21を形
成し、これにより第4図F及びGにて点線図示又は鎖線
図示の如く半導体素子形戒領域6内に半導体素子を形成
する前迄の工程に於で半導体領域20又は21に基きシ
リコン酸化物膜5のシリコン基板1内に延長せる領域の
周りに所謂チャンネルカット層22又は23の形成され
てなる構成を得る様になすことも出来るものである。
Further, in the above description, the case where only the silicon oxide film 5 is formed in the steps before forming the semiconductor element in the semiconductor element shaped region 6 has been described, but a detailed explanation thereof will be omitted, but the fourth The laminated mask layer 10 is used as a mask between the step of forming the laminated mask layer 10 as described above in FIG. The silicon substrate 1 is introduced into the silicon substrate 1 in a region other than under the laminated mask layer 10 on the main surface side of the silicon substrate 1 as shown by the dotted line in FIG. 4C. A step of forming a semiconductor region 20 having the same conductivity type as , or forming a laminated mask layer 13 as described above with reference to FIG.
During the step of forming the silicon substrate 1, an impurity is introduced into the silicon substrate 1 using the laminated mask layer 13 as a mask, and the main surface of the silicon substrate 1 is formed as shown by the chain line in FIG. 4E. A semiconductor region 21 having the same conductivity type as the silicon substrate 1 is formed in a region other than under the laminated mask layer 13 on the side, thereby forming a semiconductor element shaped region 6 as shown by dotted lines or chain lines in FIGS. 4F and G. A so-called channel cut layer 22 or 23 is formed around the region of the silicon oxide film 5 that can be extended into the silicon substrate 1 based on the semiconductor region 20 or 21 in a step before forming a semiconductor element therein. It can also be done to obtain the configuration.

又図示説明はこれを省略するも、第4図Cにて上述せる
如くに積層マスク層10を形成する工程と次に第4図に
て上述せる如くに耐酸化性被膜11を形成する工程との
間、又は第4図Eにて上述せる如〈に積層マスク層13
を形成する工程と次に第4図Fにて上述せる如〈にシリ
コン酸化物膜5を形成する工程との間で、積層マスク層
10をマスクとせるシリコン基板1に対するエッチング
処理をなして、第4図Fにて上述せる如くにシリコン酸
化物膜5を形成する工程の直前に於でシリコン基板1の
積層マスク層13側の面がその積層マスク層13下以外
の領域の面部をして積層マスク層13下の領域の面部よ
り積層マスク層13側とは反対側に下った面とし、これ
によりシリコン酸化物膜5をそのシリコン基板1側とは
反対側の面と積層マスク層13の領域の面部との間をし
て実質的に段差がないか又はあっても小なる値の段差を
有するものとして形成し、シリコン基板1を用いて形成
される多数の半導体素子中の所要の半導体素子をシリコ
ン基板1上に延長せる配線層を形威して所要の回路を構
成する場合にその配線層が確実に形成される様になす様
にすることも出来るものである。
Although illustrations and explanations are omitted, there are a step of forming the laminated mask layer 10 as described above with reference to FIG. 4C, and a step of forming the oxidation-resistant film 11 as described above with reference to FIG. 4E, or as described above in FIG. 4E.
Between the step of forming the silicon oxide film 5 and the step of forming the silicon oxide film 5 as described above with reference to FIG. As described above in FIG. 4F, immediately before the step of forming the silicon oxide film 5, the surface of the silicon substrate 1 on the side of the laminated mask layer 13 is formed so that the surface of the area other than under the laminated mask layer 13 is The surface of the region below the laminated mask layer 13 is set to the side opposite to the laminated mask layer 13 side, so that the silicon oxide film 5 has a surface opposite to the silicon substrate 1 side and the laminated mask layer 13 side. It is formed so that there is substantially no step difference or a small step difference between the region and the surface portion of the region, and a required semiconductor in a large number of semiconductor elements formed using the silicon substrate 1 is formed. It is also possible to form a wiring layer that extends the elements onto the silicon substrate 1 so that the wiring layer can be reliably formed when configuring a required circuit.

更に上述に於では耐酸化性被膜がSi3N4でなる場合
につき述べたが、これがSiC,Al203でなる場合
でも上述せる本発明の特徴を得ることが出来、その他本
発明の精神を脱することなしに種種の変型変更をなし得
るであろう。
Further, in the above description, the case where the oxidation-resistant film is made of Si3N4 has been described, but even if it is made of SiC or Al203, the above-mentioned features of the present invention can be obtained, and other aspects can be obtained without departing from the spirit of the present invention. Various modifications could be made.

【図面の簡単な説明】[Brief explanation of drawings]

第1図、第2図及び第3図は夫々従来の半導体集積回路
装置の製法を示す順次の工程に於げる略線的断面図、第
4図は本発明による半導体集積回路装置の製法の→りを
示す順次の工程に於ける略線的断面図、第5図、第6図
及び第7図は夫々本発明による半導体集積回路装置の製
法の他の例を示す順次の工程に於ける略線的断面図であ
る。 図中、1はシリコン基板、2は主面、3は耐酸化性被膜
、5及び15はシリコン酸化物膜、6は半導体素子形成
領域、7はシリコン酸化物被膜、8,9及び12はマス
ク層、10及び13は積層マスク層、14は多孔質シリ
コン膜を夫々示す。
1, 2, and 3 are schematic cross-sectional views showing sequential steps of a conventional method for manufacturing a semiconductor integrated circuit device, and FIG. 4 shows a method for manufacturing a semiconductor integrated circuit device according to the present invention. 5, 6, and 7 are schematic cross-sectional views in the sequential steps showing the process of manufacturing the semiconductor integrated circuit device according to the present invention. It is a schematic cross-sectional view. In the figure, 1 is a silicon substrate, 2 is a main surface, 3 is an oxidation-resistant film, 5 and 15 are silicon oxide films, 6 is a semiconductor element formation region, 7 is a silicon oxide film, 8, 9 and 12 are masks Layers 10 and 13 are laminated mask layers, and 14 is a porous silicon film, respectively.

Claims (1)

【特許請求の範囲】[Claims] 1 シリコン基板の主面上にシリコン酸化物被膜及び第
1の耐酸化性被膜をそれ等の順に積層形成する工程と、
上記第1の耐酸化性被膜及びシリコン酸化物被膜に対す
る選択的エッチング処理により上記シリコン酸化物被膜
による第1のマスク層及び上記第1の耐酸化性被膜によ
る第2のマスク層のそれ等の順に積層されてなる第lの
積層マスク層を形成する工程と、上記第1の積層マスク
層の上記シリコン基板側とは反対側の面及び側面上、及
び上記シリコン基板の上記第1の積層マスク層下以外の
領域上に連結延長せる第2の耐酸化性被膜を形成する工
程と、上記第2の耐酸化性被膜に対するパターンニング
なしのエッチング処理により上記第1の積層マスク層の
側面上に上記第2の耐酸化性被膜による上記シリコン基
板の主面上に達スるマスク層を連結延長せしめてなる第
2の積層マスク層を形戒する工程と、上記第2の積層マ
スク層をマスクとせる上記シリコン基板に対する酸化処
理により上記シリコン基板の主面側の上記第2の積層マ
スク層下以外の領域にシリコン酸化物膜を形成する工程
とを含む事を特徴とする半導体集積回路装置の製法。
1. Laminating a silicon oxide film and a first oxidation-resistant film in that order on the main surface of a silicon substrate;
The first oxidation-resistant coating and the silicon oxide coating are selectively etched to form a first mask layer of the silicon oxide coating and a second mask layer of the first oxidation-resistant coating, etc. a step of forming a laminated first laminated mask layer; and on the surface and side surface of the first laminated mask layer opposite to the silicon substrate side, and on the first laminated mask layer of the silicon substrate. A step of forming a second oxidation-resistant film that can be connected and extended on a region other than the bottom, and an etching process without patterning on the second oxidation-resistant film, forms the above-mentioned on the side surface of the first laminated mask layer. forming a second laminated mask layer formed by connecting and extending the mask layers that reach the main surface of the silicon substrate with a second oxidation-resistant film; and forming the second laminated mask layer as a mask. forming a silicon oxide film in a region other than under the second laminated mask layer on the main surface side of the silicon substrate by oxidizing the silicon substrate. .
JP7336379A 1979-06-11 1979-06-11 Manufacturing method for semiconductor integrated circuit devices Expired JPS5849027B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7336379A JPS5849027B2 (en) 1979-06-11 1979-06-11 Manufacturing method for semiconductor integrated circuit devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7336379A JPS5849027B2 (en) 1979-06-11 1979-06-11 Manufacturing method for semiconductor integrated circuit devices

Publications (2)

Publication Number Publication Date
JPS55165637A JPS55165637A (en) 1980-12-24
JPS5849027B2 true JPS5849027B2 (en) 1983-11-01

Family

ID=13516010

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7336379A Expired JPS5849027B2 (en) 1979-06-11 1979-06-11 Manufacturing method for semiconductor integrated circuit devices

Country Status (1)

Country Link
JP (1) JPS5849027B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164550A (en) * 1980-05-21 1981-12-17 Fujitsu Ltd Manufacture of semiconductor device
JPS5875845A (en) * 1981-10-30 1983-05-07 Fujitsu Ltd Manufacture of semiconductor device
JPS6271247A (en) * 1985-09-25 1987-04-01 Toshiba Corp Manufacture of semiconductor device
US4814290A (en) * 1987-10-30 1989-03-21 International Business Machines Corporation Method for providing increased dopant concentration in selected regions of semiconductor devices

Also Published As

Publication number Publication date
JPS55165637A (en) 1980-12-24

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