JPH02132830A - Selective oxidation - Google Patents

Selective oxidation

Info

Publication number
JPH02132830A
JPH02132830A JP28715688A JP28715688A JPH02132830A JP H02132830 A JPH02132830 A JP H02132830A JP 28715688 A JP28715688 A JP 28715688A JP 28715688 A JP28715688 A JP 28715688A JP H02132830 A JPH02132830 A JP H02132830A
Authority
JP
Japan
Prior art keywords
film
semiconductor
substrate
oxidation
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28715688A
Other languages
Japanese (ja)
Inventor
Shinichi Ito
信一 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP28715688A priority Critical patent/JPH02132830A/en
Publication of JPH02132830A publication Critical patent/JPH02132830A/en
Pending legal-status Critical Current

Links

Landscapes

  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To remove a semiconductor film without locally etching away a semiconductor substrate by a method wherein, after thermally oxidizing the semiconductor film into an oxide film, the semiconductor film is removed by removing the oxide film. CONSTITUTION:An oxide mask laminated with an SiO2 film 2, a polycrystalline Si film 3 and an Si3N4 film 5 is formed on an Si substrate 1. Next, the film 3 thermal oxidized after etching away the film 5 is perfectly oxidized and then the surface of the substrate 1 is sacrifice-oxidized to form SiO2 films 7, 8. Furthermore, the SiO2 films 7, 8 are etched away using a fluorine base etchant to expose the surface of the substrate 1. Then, a gate SiO2 film 9 is formed on the surface of the exposed substrate 1 by thermal oxidation. Through these procedures, the semiconductor film 3 can be removed without locally etching away the substrate 1 by thermal oxidizing the film 3 to be changed into the film 7 which is to be etched away later.

Description

【発明の詳細な説明】 (産業上の利用分野〕 本発明は、選択酸化方法に関し、特に、高集積密度の半
導体集積回路装置における素子間分離を〔発明の概要〕 本発明による選択酸化方法は、少なくとも半導体酸化膜
と半導体膜と耐酸化膜とを順次積層させた酸化マスクを
半導体基体上に形成する工程と、上記酸化マスクを用い
て上記半導体基体を選択的に酸化する工程と、上記耐酸
化膜を除去する工程と、上記半導体層及び上記半導体基
体の表面を酸化する工程と、上記半導体層及び上記半導
体基体の表面を酸化することにより形成された酸化膜及
び上記半導体酸化膜を除去する工程とを具備している。
DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a selective oxidation method, and in particular, to isolation between elements in a semiconductor integrated circuit device with high integration density. , a step of forming an oxide mask on a semiconductor substrate in which at least a semiconductor oxide film, a semiconductor film, and an oxidation-resistant film are sequentially laminated; a step of selectively oxidizing the semiconductor substrate using the oxide mask; and a step of selectively oxidizing the semiconductor substrate using the oxide mask; oxidizing the surfaces of the semiconductor layer and the semiconductor substrate; and removing the oxide film formed by oxidizing the surfaces of the semiconductor layer and the semiconductor substrate and the semiconductor oxide film. It is equipped with a process.

これによって、半導体基体の局所的なエッチングを生じ
ることなく、酸化マスクを構成する半導体膜を除去する
ことができる。
Thereby, the semiconductor film constituting the oxidation mask can be removed without causing local etching of the semiconductor substrate.

〔従来の技術〕[Conventional technology]

半導体集積回路装置における素子間分離領域は通常、選
択酸イヒ法(LOCOS法)により形成されている。し
かし、良く知られているように、従?のLOCOS法で
は、フィールド酸化膜の端部に形成されるバーズビーク
の長さが大きく、これが高集積密度化を阻む要因となっ
ていた。
2. Description of the Related Art Interelement isolation regions in semiconductor integrated circuit devices are usually formed by a selective oxidation method (LOCOS method). However, as is well known, follow? In the LOCOS method, the length of the bird's beak formed at the end of the field oxide film is large, which is a factor that prevents high integration density.

そこで、よりバーズビーク長が小さいフィールド酸化膜
を形成する技術が提案されている(例えば、特開昭61
−74350号公報及び特願昭63−220209号)
Therefore, a technique for forming a field oxide film with a smaller bird's beak length has been proposed (for example, JP-A-61
-74350 and Japanese Patent Application No. 63-220209)
.

第2図A〜第2図Fはその一つの方法を示し、耐酸化膜
としてのSt. N.膜の下層に多結晶シリコン(Si
 )膜を含む多N構造の酸化マスクを用いて選択酸化を
行うものである。この方法によれば、第2図Aに示すよ
うに、まずSt基板101の表面に熱酸化により例えば
膜厚50人程度のSin.膜(パッドSift膜)10
2を形成した後、このStO■膜102の全面に例えば
CVD法により例えば膜厚500人程度の多結晶Si膜
103を形成する。次に、この多結晶St膜103の表
面に熱酸化により例えば膜厚80人程度のSing膜1
04を形成した後、このSiO■膜104の全面に例え
ばCVD法により例えば膜厚1000人程度のSin?
4膜105を形成する。この後、これらのSi3N4膜
105、Sin.膜104及び多結晶St膜103をエ
ッチングにより所定形状にパターンニングして第2図A
に示すような形状とする。
FIGS. 2A to 2F show one method, in which St. N. The lower layer of the film is polycrystalline silicon (Si).
) selective oxidation is performed using an oxidation mask with a multi-N structure including a film. According to this method, as shown in FIG. 2A, the surface of the St substrate 101 is first coated with a film of, for example, a Sin. Membrane (Pad Sift membrane) 10
2, a polycrystalline Si film 103 having a thickness of, for example, about 500 wafers is formed on the entire surface of the StO2 film 102 by, for example, the CVD method. Next, a Sing film 1 having a thickness of about 80 mm is formed on the surface of the polycrystalline St film 103 by thermal oxidation.
After forming the SiO2 film 104, a SiO2 film 104 with a thickness of about 1,000 layers is formed on the entire surface of the SiO2 film 104 by, for example, the CVD method.
4 films 105 are formed. After this, these Si3N4 films 105, Sin. The film 104 and the polycrystalline St film 103 are patterned into a predetermined shape by etching as shown in FIG.
Shape as shown in .

次に、この状態で熱酸化を行う。これによって、第2図
Bに示すように、Si基仮101の表面にフィールドS
in.膜106が選択的に形成され、素子間分離が行わ
れる。この熱酸化の際には、Si3N4膜105の両端
部の下方の部分の多結晶Si膜103も酸化されること
がら、フィールドSin.膜106の端部に形成される
バーズビークの長さを小さくすることができる。
Next, thermal oxidation is performed in this state. As a result, as shown in FIG. 2B, a field S is formed on the surface of the Si-based temporary 101.
in. A film 106 is selectively formed to provide isolation between devices. During this thermal oxidation, the polycrystalline Si film 103 below both ends of the Si3N4 film 105 is also oxidized, so that the field Sin. The length of the bird's beak formed at the end of the membrane 106 can be reduced.

次に、Si. N.膜105及びSi02膜104をエ
ッチング除去して、第2図Cに示す状態とする。
Next, Si. N. The film 105 and the Si02 film 104 are removed by etching to obtain the state shown in FIG. 2C.

次に、ドライエッチングにより多結晶Si膜1o3をエ
ッチング除去して、第2図Dに示す状態とする。
Next, the polycrystalline Si film 1o3 is removed by dry etching to obtain the state shown in FIG. 2D.

次に、SiO■膜102をエッチング除去して、第2図
Eに示すようにSi基板101の表面を露出させる。
Next, the SiO2 film 102 is removed by etching to expose the surface of the Si substrate 101 as shown in FIG. 2E.

?に、ゲート耐圧の向上を目的とする前酸化(犠牲酸化
)を行うことにより、露出したSi基板101の表面に
SiO■膜107を形成する.次に、このS i O 
t膜107をエッチング除去した後、再び熱酸化(ゲー
ト酸化)を行うことによりゲートSin.膜(図示せず
)を形成する。この後、目的とする半導体集積回路装置
の製造工程に従って工程を進める. 〔発明が解決しようとする課題〕 本発明者の知見によれば、第2図A〜第2図Fに示す方
法では、熱酸化の際の応力により多結晶Si膜104に
歪みが発生し、この多結晶St膜lO4に微小な穴が形
成される。このため、この多結晶Si膜104をドライ
エッチングにより除去する際に、この多結晶54膜10
4の微小な穴を通じてSt基板101が局所的にエッチ
ングされてしまい、後工程で不都合を生じてしまうとい
う問題があった. 従って本発明の目的は、半導体基体の局所的なエッチン
グを生じることなく、酸化マスクを構成する半導体膜を
除去することができる選択酸化方法を提供することにあ
る。
? Next, a SiO2 film 107 is formed on the exposed surface of the Si substrate 101 by performing pre-oxidation (sacrificial oxidation) for the purpose of improving gate breakdown voltage. Next, this S i O
After removing the T film 107 by etching, thermal oxidation (gate oxidation) is performed again to form the gate Sin. A film (not shown) is formed. After this, the process proceeds according to the manufacturing process of the target semiconductor integrated circuit device. [Problems to be Solved by the Invention] According to the findings of the present inventors, in the methods shown in FIGS. 2A to 2F, distortion occurs in the polycrystalline Si film 104 due to stress during thermal oxidation. A minute hole is formed in this polycrystalline St film lO4. Therefore, when removing this polycrystalline Si film 104 by dry etching, this polycrystalline Si film 104
There was a problem in that the St substrate 101 was locally etched through the minute hole No. 4, causing inconvenience in the subsequent process. Therefore, an object of the present invention is to provide a selective oxidation method that can remove a semiconductor film forming an oxidation mask without causing local etching of a semiconductor substrate.

〔課題を解決するための手段〕[Means to solve the problem]

上記課題を解決するため、本発明による選択酸化方法は
、少な《とも半導体酸化膜(2)と半導体#(3)と耐
酸化膜(5)とを順次積層させた酸化マスクを半導体基
体(1)上に形成する工程と、酸化マスクを用いて半導
体基体(1)を選択的に酸化する工程と、耐酸化膜(5
)を除去する工程と、半導体ff(3)及び半導体基体
(1)の表面を酸化する工程と、半導体膜(3)及び半
導体基体(1)の表面を酸化することにより形成された
酸化膜(7.8)及び半導体酸化膜(2)を除去する工
程とを具備している。
In order to solve the above problems, the selective oxidation method according to the present invention provides an oxidation mask in which at least a semiconductor oxide film (2), a semiconductor # (3), and an oxidation-resistant film (5) are sequentially laminated on a semiconductor substrate (1). ), a step of selectively oxidizing the semiconductor substrate (1) using an oxidation mask, and a step of selectively oxidizing the semiconductor substrate (1) using an oxidation mask;
), a step of oxidizing the surfaces of the semiconductor ff (3) and the semiconductor substrate (1), and an oxide film ( 7.8) and a step of removing the semiconductor oxide film (2).

〔作用〕[Effect]

上記した手段によれば、半導体膜(3)を酸化により酸
化1fi(7)に変えてからこの酸化膜(7)を除去す
ることによりこの半導体膜(3)を除去しているので、
半導体膜(3)をドライエッチングにより除去する場合
のように半導体基体(1)が局所的にエッチングされて
しまう問題がなくなる。すなわち、半導体基体(1)の
局所的なエッチングを生じることなく、半導体膜(3)
を除去することができる. ?実施例〕 以下、本発明の一実施例について図面を参照しながら説
明する. 第1図A〜第1図Eは本発明の一実施例を示す.本実施
例においては、まず第2図A及び第2図Bに示すと同様
に工程を進めて選択酸化を終了する。第1図Aはその状
態を示す.第1図Aにおいて、符号1はSl基板、符号
2はSiO■膜、符号3は多結晶St膜、符号4はSi
Oz膜、符号5はSi3N4膜、符号6はフィールドS
iOz膜を示す。
According to the above-mentioned means, the semiconductor film (3) is removed by converting the semiconductor film (3) into oxidized 1fi (7) by oxidation and then removing this oxide film (7).
This eliminates the problem of the semiconductor substrate (1) being locally etched, which occurs when the semiconductor film (3) is removed by dry etching. That is, the semiconductor film (3) can be etched without causing local etching of the semiconductor substrate (1).
can be removed. ? Embodiment] An embodiment of the present invention will be described below with reference to the drawings. 1A to 1E show an embodiment of the present invention. In this embodiment, the selective oxidation is completed by proceeding with the same steps as shown in FIGS. 2A and 2B. Figure 1A shows this situation. In FIG. 1A, numeral 1 is an Sl substrate, numeral 2 is an SiO2 film, numeral 3 is a polycrystalline St film, and numeral 4 is a Si substrate.
Oz film, code 5 is Si3N4 film, code 6 is field S
An iOz film is shown.

次に、Si3 N.膜5を例えばホットりん酸によりエ
ッチング除去して、第1図Bに示す状態とす?. 次に、この状態で熱酸化を行うことにより、多結晶Si
膜3を完全に酸化し、引き続いてsi基板1の表面を酸
化して犠牲酸化を行う。符号7は多結晶St膜3の酸化
により形成されたSift膜を示す.このSin!膜7
の膜厚は多結晶Si膜3の厚さの約1.5倍である。ま
た、符号8は、Si基板1の表面の酸化により形成され
たSiO■膜を示す。このSing膜8の膜厚は例えば
数百人程度である。
Next, Si3N. The film 5 is etched away using, for example, hot phosphoric acid to obtain the state shown in FIG. 1B. .. Next, by performing thermal oxidation in this state, polycrystalline Si
The film 3 is completely oxidized, and then the surface of the Si substrate 1 is oxidized to perform sacrificial oxidation. Reference numeral 7 indicates a Sift film formed by oxidizing the polycrystalline St film 3. This Sin! Membrane 7
The film thickness is approximately 1.5 times the thickness of the polycrystalline Si film 3. Further, reference numeral 8 indicates a SiO2 film formed by oxidizing the surface of the Si substrate 1. The thickness of this Sing film 8 is, for example, about several hundred.

次に、これらのSiOt膜7,2.8を例えばフッ酸系
のエッチング液によりエッチング除去して、第1図Dに
示すようにSi基板1の表面を露出させる。なお、この
エッチングの際には、フィールドSin.膜6もエッチ
ングされて膜厚が減少するが、これは実際上問題とはな
らない。
Next, these SiOt films 7, 2.8 are removed by etching using, for example, a hydrofluoric acid-based etching solution to expose the surface of the Si substrate 1 as shown in FIG. 1D. Note that during this etching, the field Sin. Although the film 6 is also etched and its thickness is reduced, this is not a problem in practice.

次に、この露出したSt基板1の表面に熱酸化によりゲ
ートSing膜9を形成する。
Next, a gate Sing film 9 is formed on the exposed surface of the St substrate 1 by thermal oxidation.

この後、例えばMOSLSIの製造工程に従って工程を
進める。
After this, the steps are performed according to, for example, a MOSLSI manufacturing process.

以上のように、本実施例によれば、多結晶Si膜3を熱
酸化してSi02膜7に変えた後、このSiO2膜7を
エッチング除去しているので、多結晶Si膜3をドライ
エッチングにより除去する従来技術の場合のようにSi
基仮lが局所的にエッチングされてしまう問題を完全に
解決することができる.しかも、多結晶St膜3の酸化
は犠牲酸化と同時に行うことができるので、工程の増加
はない。
As described above, according to this embodiment, after the polycrystalline Si film 3 is thermally oxidized to change into the Si02 film 7, this SiO2 film 7 is removed by etching, so the polycrystalline Si film 3 is dry etched. As in the case of the prior art, Si
This completely solves the problem of local etching of the base l. Moreover, since the polycrystalline St film 3 can be oxidized simultaneously with the sacrificial oxidation, there is no increase in the number of steps.

以上、本発明の実施例につき具体的に説明したが、本発
明は、上述の実施例に限定されるものではなく、本発明
の技術的思想に基づく各種の変形が可能である。
Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above-described embodiments, and various modifications can be made based on the technical idea of the present invention.

例えば、本発明は、MOSLSIの製造ばかりでなく、
バイボーラ−CMOSLSIやバイボーラLSIの製造
に適用することも可能である.
For example, the present invention is applicable not only to the manufacture of MOSLSI, but also to
It can also be applied to the manufacture of bibolar CMOS LSIs and bibolar LSIs.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図A〜第1図Eは本発明の一実施例を工程順に説明
するための断面図、第2図A〜第2図Fは従来の選択酸
化法を工程順に説明するための断面図である。 図面における主要な符号の説明 1:Si基板、 2,4,7.8 :SiOz膜、3:
多結晶St膜、 6:フィールドSin2膜、9 :ゲ
ートSing  膜。
1A to 1E are sectional views for explaining an embodiment of the present invention in the order of steps, and FIGS. 2A to 2F are sectional views for explaining the conventional selective oxidation method in the order of steps. It is. Explanation of main symbols in the drawings 1: Si substrate, 2, 4, 7.8: SiOz film, 3:
Polycrystalline St film, 6: Field Sin2 film, 9: Gate Sing film.

Claims (1)

【特許請求の範囲】 少なくとも半導体酸化膜と半導体膜と耐酸化膜とを順次
積層させた酸化マスクを半導体基体上に形成する工程と
、 上記酸化マスクを用いて上記半導体基体を選択的に酸化
する工程と、 上記耐酸化膜を除去する工程と、 上記半導体層及び上記半導体基体の表面を酸化する工程
と、 上記半導体層及び上記半導体基体の表面を酸化すること
により形成された酸化膜及び上記半導体酸化膜を除去す
る工程とを具備することを特徴とする選択酸化方法。
[Claims] A step of forming on a semiconductor substrate an oxidation mask in which at least a semiconductor oxide film, a semiconductor film, and an oxidation-resistant film are sequentially laminated, and selectively oxidizing the semiconductor substrate using the oxidation mask. a step of removing the oxidation-resistant film; a step of oxidizing the surfaces of the semiconductor layer and the semiconductor substrate; and an oxide film formed by oxidizing the surfaces of the semiconductor layer and the semiconductor substrate and the semiconductor. A selective oxidation method comprising the step of removing an oxide film.
JP28715688A 1988-11-14 1988-11-14 Selective oxidation Pending JPH02132830A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28715688A JPH02132830A (en) 1988-11-14 1988-11-14 Selective oxidation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28715688A JPH02132830A (en) 1988-11-14 1988-11-14 Selective oxidation

Publications (1)

Publication Number Publication Date
JPH02132830A true JPH02132830A (en) 1990-05-22

Family

ID=17713803

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28715688A Pending JPH02132830A (en) 1988-11-14 1988-11-14 Selective oxidation

Country Status (1)

Country Link
JP (1) JPH02132830A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371035A (en) * 1993-02-01 1994-12-06 Motorola Inc. Method for forming electrical isolation in an integrated circuit device
US6239001B1 (en) 1997-01-10 2001-05-29 Nec Corporation Method for making a semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59115538A (en) * 1982-12-20 1984-07-04 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Method of producing integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59115538A (en) * 1982-12-20 1984-07-04 インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン Method of producing integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371035A (en) * 1993-02-01 1994-12-06 Motorola Inc. Method for forming electrical isolation in an integrated circuit device
US6239001B1 (en) 1997-01-10 2001-05-29 Nec Corporation Method for making a semiconductor device

Similar Documents

Publication Publication Date Title
JPS6174350A (en) Manufacture of semiconductor device
JPH02132830A (en) Selective oxidation
JPH06163528A (en) Fabrication of semiconductor device
JP3853916B2 (en) Manufacturing method of semiconductor device
US6245643B1 (en) Method of removing polysilicon residual in a LOCOS isolation process using an etching selectivity solution
JPS63204746A (en) Manufacture of semiconductor device
JPS6021541A (en) Manufacture of semiconductor device
JPS5849027B2 (en) Manufacturing method for semiconductor integrated circuit devices
JPH0410419A (en) Manufacture of semiconductor device
JPH0334425A (en) Manufacture of semiconductor device
JPH02116131A (en) Manufacture of semiconductor device
JPH01162351A (en) Manufacture of semiconductor device
JPH05218191A (en) Manufacture of semiconductor device having different-width inter-element isolating regions
KR940009578B1 (en) Semiconductor device and manufacturing method thereof
JPH01169941A (en) Forming method for element isolation region in semiconductor integrated circuit
KR100353819B1 (en) Method for manufacturing semiconductor device
JPH1167752A (en) Manufacture of semiconductor device
JPS6020529A (en) Manufacture of semiconductor device
JPH1032264A (en) Semiconductor device and manufacture thereof
JPS6324635A (en) Manufacture of semiconductor device
JPH01283854A (en) Manufacture of semiconductor device
JPS6027144A (en) Manufacture of semiconductor device
JPS61154143A (en) Manufacture of semiconductor device
JPH05160120A (en) Manufacture of semiconductor device
JPH0541376A (en) Formation of semiconductor interelement isolation