JPH0410419A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0410419A JPH0410419A JP11388790A JP11388790A JPH0410419A JP H0410419 A JPH0410419 A JP H0410419A JP 11388790 A JP11388790 A JP 11388790A JP 11388790 A JP11388790 A JP 11388790A JP H0410419 A JPH0410419 A JP H0410419A
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- silicon oxide
- oxide film
- substrate
- porous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- 238000002955 isolation Methods 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 18
- 229910021426 porous silicon Inorganic materials 0.000 claims abstract description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000002048 anodisation reaction Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 12
- 239000002344 surface layer Substances 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 230000001131 transforming effect Effects 0.000 claims 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 3
- 239000001301 oxygen Substances 0.000 abstract description 3
- 229910052760 oxygen Inorganic materials 0.000 abstract description 3
- 238000003487 electrochemical reaction Methods 0.000 abstract description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 abstract 3
- 235000019441 ethanol Nutrition 0.000 abstract 2
- 239000000203 mixture Substances 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 241000293849 Cordylanthus Species 0.000 description 1
- 238000007743 anodising Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法、特に素子分離用シリ
コン酸化膜を形成する技術に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a technique for forming a silicon oxide film for element isolation.
従来の技術
最近の半導体プロセスではホトリソ工程がますます高精
度化しているため半導体基板にマスクを密着させるため
半導体基板の表面の平面度について高い水準が要求され
ている。BACKGROUND OF THE INVENTION In recent semiconductor processes, the photolithography process has become more and more precise, so a high level of flatness of the surface of the semiconductor substrate is required in order to bring the mask into close contact with the semiconductor substrate.
従来、この種の半導体装置の製造方法の一例は、第2図
(a)、 (b)に示すような構成であった。Conventionally, an example of a method for manufacturing this type of semiconductor device has a structure as shown in FIGS. 2(a) and 2(b).
まず、第2図(a)に示すように、P型のシリコン基板
11上にシリコン酸化膜12およびシリコン窒化膜13
を形成した後、素子分離用シリコン酸化膜15を形成す
る領域のシリコン酸化膜12およびシリコン窒化膜13
をエツチングにより取り除(。First, as shown in FIG. 2(a), a silicon oxide film 12 and a silicon nitride film 13 are placed on a P-type silicon substrate 11.
After forming the silicon oxide film 12 and the silicon nitride film 13 in the region where the element isolation silicon oxide film 15 is to be formed.
is removed by etching (.
次に第2図(b)に示すように酸素を含む気体中で熱酸
化し素子分離用シリコン酸化膜15を形成する。Next, as shown in FIG. 2(b), thermal oxidation is performed in a gas containing oxygen to form a silicon oxide film 15 for element isolation.
発明が解決しようとする課題
このような従来の工程では、P型のシリコン基板11上
に素子分離用シリコン酸化膜15を形成する際、素子分
離用シリコン酸化膜15が、先にP型のシリコン基板1
1上に形成されているシリコン酸化膜12の開口端部1
2゛の下方のP型のシリコン基板11上にもぐり込んで
形成されるため、シリコン酸化膜12の開口端部12゛
とその上に形成されているシリコン窒化膜13の開口端
部13゛が押入上げられ、素子表面に凹凸が発生するた
めにその後の微細化工程に不適当であることと、素子分
離用シリコン酸化膜15周辺部にストレスが生じP型の
シリコン基板11に結晶欠陥を引き起こすという問題点
があった。Problems to be Solved by the Invention In such a conventional process, when forming the silicon oxide film 15 for element isolation on the P-type silicon substrate 11, the silicon oxide film 15 for element isolation is first formed on the P-type silicon substrate 11. Board 1
Open end 1 of silicon oxide film 12 formed on 1
Since it is formed by sinking into the P-type silicon substrate 11 below 2', the open end 12' of the silicon oxide film 12 and the open end 13' of the silicon nitride film 13 formed thereon are pushed in. It is said that it is not suitable for the subsequent miniaturization process due to the occurrence of unevenness on the element surface, and that stress is generated around the silicon oxide film 15 for element isolation, causing crystal defects in the P-type silicon substrate 11. There was a problem.
本発明はかかる点に鑑みてなされたもので、前記課題を
解決し素子分離用シリコン酸化膜15の形成にともなう
凹凸の発生を軽減し、なおかつ素子分離用シリコン酸化
膜15からのストレスを軽減できる素子分離用シリコン
酸化膜15を形成する半導体装置の製造方法を提供する
ことを目的とするものである。The present invention has been made in view of these points, and can solve the above problems, reduce the occurrence of unevenness due to the formation of the silicon oxide film 15 for element isolation, and reduce stress from the silicon oxide film 15 for element isolation. It is an object of the present invention to provide a method for manufacturing a semiconductor device in which a silicon oxide film 15 for element isolation is formed.
課題を解決するための手段
この課題を解決するために、本発明の半導体装置の製造
方法は素子分離用シリコン酸化膜を形成する熱酸化を行
なう前に、素子分離用シリコン酸化膜を形成する領域の
シリコン基板の表面層を陽極化成法により多孔質シリコ
ン層に変成し、その多孔質シリコン層を酸化して素子分
離用シリコン酸化膜を形成するものである。Means for Solving the Problem In order to solve this problem, a method for manufacturing a semiconductor device according to the present invention includes a method for manufacturing a semiconductor device of the present invention. The surface layer of the silicon substrate is transformed into a porous silicon layer by anodization, and the porous silicon layer is oxidized to form a silicon oxide film for element isolation.
作用
この構成により、陽極化成法により変成した多孔質シリ
コン層は微小孔を多数含みその表面積が非常に大きいた
め、その多孔質シリコン層に後の工程で熱酸化法により
素子分離用シリコン酸化膜を形成しても、表面層だけで
なく内部の微小孔の表面も酸化されるため、表面層の体
積増加が少ない。Effect With this configuration, the porous silicon layer modified by the anodization method contains many micropores and has a very large surface area, so a silicon oxide film for element isolation is applied to the porous silicon layer by thermal oxidation in a later step. Even if it is formed, not only the surface layer but also the surface of the internal micropores are oxidized, so the volume increase of the surface layer is small.
実施例
以下本発明の半導体装置の一実施例について図面を用い
て説明する。EXAMPLE An example of the semiconductor device of the present invention will be described below with reference to the drawings.
第1図(a)に示すように、P型のシリコン基板1上に
シリコン酸化膜2およびシリコン窒化膜3を形成した後
、素子分離用シリコン酸化膜を形成する領域のシリコン
酸化膜2およびシリコン窒化膜3をエツチングにより取
り除く。As shown in FIG. 1(a), after forming a silicon oxide film 2 and a silicon nitride film 3 on a P-type silicon substrate 1, the silicon oxide film 2 and the silicon The nitride film 3 is removed by etching.
次に第1図(b)に示すように、素子分離用シリコン酸
化膜を形成しようとする領域のP型のシリコン基板1の
表面層を陽極化成法を用い多孔質シリコン層4に変成す
る。多孔質シリコン層4は、シリコン単結晶をフッ酸溶
液中で陽極化成することにより得られ、数〜数10nm
の微小孔を多数含み、その表面積が非常に大きい(20
0〜800+J/cd)ことから、短時間で低い温度で
の酸化が可能である。陽極化成法を用いてP型のシリコ
ン基板の表面層を多孔質シリコン層4に変受成する方法
の一例を示す。P型のシリコン基板1をエタノールを混
合したフッ酸溶液(HF : H2O:C2H50H=
1 : 1 : 2)の中で数m A / c!の電流
を数十秒速じることにより、電気化学的反応によりP型
のシリコン基板1の表面を厚さ数百nmの多孔質シリコ
ン層4に変成する。Next, as shown in FIG. 1(b), the surface layer of the P-type silicon substrate 1 in a region where a silicon oxide film for element isolation is to be formed is transformed into a porous silicon layer 4 using an anodization method. The porous silicon layer 4 is obtained by anodizing a silicon single crystal in a hydrofluoric acid solution, and has a thickness of several to several tens of nm.
It contains many micropores and has a very large surface area (20
0 to 800+J/cd), oxidation can be performed in a short time and at a low temperature. An example of a method for converting the surface layer of a P-type silicon substrate into a porous silicon layer 4 using an anodization method will be described. A P-type silicon substrate 1 was heated in a hydrofluoric acid solution (HF:H2O:C2H50H=
1:1:2), several mA/c! By increasing the current for several tens of seconds, the surface of the P-type silicon substrate 1 is transformed into a porous silicon layer 4 with a thickness of several hundred nm by an electrochemical reaction.
さらに、第1図(C)に示すように酸素に含む気体中で
熱酸化し、多孔質シリコン層4上に素子分離用シリコン
酸化膜5を形成する。Furthermore, as shown in FIG. 1C, thermal oxidation is performed in a gas containing oxygen to form a silicon oxide film 5 for element isolation on the porous silicon layer 4.
第1図(b)、 (C)の工程が従来例第2図(b)の
工程と対応しており、以降の半導体装置形成工程は通常
の工程へとつながれる。The steps shown in FIGS. 1(b) and 1(C) correspond to the steps shown in FIG. 2(b) of the conventional example, and the subsequent semiconductor device forming steps are connected to normal steps.
発明の効果
以上の実施例の説明で明らかなように本発明の半導体装
置の製造方法によれば、素子分離用シリコン酸化膜形成
にともなう凹凸の発生を軽減し、なおかつ素子分離用シ
リコン酸化膜からのストレスを軽減することによりシリ
コン基板の結晶欠陥を軽減できる。Effects of the Invention As is clear from the description of the embodiments above, the method for manufacturing a semiconductor device of the present invention reduces the occurrence of unevenness accompanying the formation of a silicon oxide film for element isolation, and also reduces the unevenness caused by the formation of a silicon oxide film for element isolation. By reducing stress, crystal defects in the silicon substrate can be reduced.
さらに、熱酸化を行なう際に従来より短時間かつ低温で
形成できるため、バーズビークも低減でき、熱的なスト
レスも軽減するという効果が得られる。Furthermore, since thermal oxidation can be performed in a shorter time and at a lower temperature than before, bird's beak can be reduced and thermal stress can also be reduced.
第1図は本発明の一実施例による半導体装置の製造方法
を工程順に示す半導体素子基板の断面図、第2図は従来
の半導体装置の製造方法の一実施例を工程順に示す半導
体素子基板の断面図である。
1・・・・・・シリコン基板、2・・・・・・シリコン
酸化膜、3・・・・・・シリコン窒化膜、4・・・・・
・多孔質シリコン層、5・・・・・・素子分離用シリコ
ン酸化膜。FIG. 1 is a sectional view of a semiconductor element substrate showing a method for manufacturing a semiconductor device according to an embodiment of the present invention in order of steps, and FIG. 2 is a cross-sectional view of a semiconductor element substrate showing an embodiment of a conventional method for manufacturing a semiconductor device in order of steps FIG. 1...Silicon substrate, 2...Silicon oxide film, 3...Silicon nitride film, 4...
・Porous silicon layer, 5...Silicon oxide film for element isolation.
Claims (1)
シリコン酸化膜上にシリコン窒化膜を形成した後、素子
分離用シリコン酸化膜を前記シリコン基板上に形成する
ため、前記素子分離用シリコン酸化膜を形成する領域の
前記シリコン基板上に形成した前記シリコン酸化膜と前
記シリコン窒化膜を除去し、素子分離用シリコン酸化膜
を形成しない領域をマスクした後、素子分離用シリコン
酸化膜を形成する領域のシリコン基板表面層を陽極化成
法により多孔質シリコン層に変成する工程と、前記多孔
質シリコン層を酸化する工程とを有する半導体装置の製
造方法。After forming a silicon oxide film on a silicon substrate and further forming a silicon nitride film on the silicon oxide film, forming the silicon oxide film for element isolation in order to form a silicon oxide film for element isolation on the silicon substrate. After removing the silicon oxide film and the silicon nitride film formed on the silicon substrate in the area where the silicon oxide film is to be formed, and masking the area where the silicon oxide film for element isolation is not to be formed, the silicon oxide film and the silicon nitride film formed on the silicon substrate are removed. A method for manufacturing a semiconductor device, comprising the steps of transforming a substrate surface layer into a porous silicon layer by anodization, and oxidizing the porous silicon layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11388790A JPH0410419A (en) | 1990-04-26 | 1990-04-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11388790A JPH0410419A (en) | 1990-04-26 | 1990-04-26 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0410419A true JPH0410419A (en) | 1992-01-14 |
Family
ID=14623620
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11388790A Pending JPH0410419A (en) | 1990-04-26 | 1990-04-26 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0410419A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10036725A1 (en) * | 2000-07-27 | 2002-02-14 | Infineon Technologies Ag | Production of an insulator used in electronic circuits comprises forming a first conducting pathway and a second conducting pathway on a semiconductor substrate using conducting silicon |
WO2002045146A1 (en) * | 2000-11-30 | 2002-06-06 | Telephus, Inc. | Fabrication method of selectively oxidized porous silicon (sops) layer and multi-chip package using the same |
KR100329751B1 (en) * | 1995-12-16 | 2002-10-25 | 주식회사 하이닉스반도체 | Method for forming oxide layer using porous silicon layer |
-
1990
- 1990-04-26 JP JP11388790A patent/JPH0410419A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100329751B1 (en) * | 1995-12-16 | 2002-10-25 | 주식회사 하이닉스반도체 | Method for forming oxide layer using porous silicon layer |
DE10036725A1 (en) * | 2000-07-27 | 2002-02-14 | Infineon Technologies Ag | Production of an insulator used in electronic circuits comprises forming a first conducting pathway and a second conducting pathway on a semiconductor substrate using conducting silicon |
DE10036725C2 (en) * | 2000-07-27 | 2002-11-28 | Infineon Technologies Ag | Process for producing a porous insulating layer with a low dielectric constant on a semiconductor substrate |
US6713364B2 (en) | 2000-07-27 | 2004-03-30 | Infineon Technologies Ag | Method for forming an insulator having a low dielectric constant on a semiconductor substrate |
WO2002045146A1 (en) * | 2000-11-30 | 2002-06-06 | Telephus, Inc. | Fabrication method of selectively oxidized porous silicon (sops) layer and multi-chip package using the same |
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