JPH0366127A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH0366127A
JPH0366127A JP20360389A JP20360389A JPH0366127A JP H0366127 A JPH0366127 A JP H0366127A JP 20360389 A JP20360389 A JP 20360389A JP 20360389 A JP20360389 A JP 20360389A JP H0366127 A JPH0366127 A JP H0366127A
Authority
JP
Japan
Prior art keywords
silicon nitride
nitride film
silicon oxide
oxide film
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20360389A
Other languages
Japanese (ja)
Inventor
Kenichi Tanaka
研一 田中
Shigeo Onishi
茂夫 大西
Moriya Okayama
盛弥 岡山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP20360389A priority Critical patent/JPH0366127A/en
Publication of JPH0366127A publication Critical patent/JPH0366127A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To manufacture a semiconductor device capable of forming an element isolation region whose pattern accuracy is high by executing a thermal oxidation operation after a mask for thermal oxidation use of a four-layer structure which is composed of a first silicon oxide film, a first silicon nitride film, a second silicon oxide film and a second silicon nitride film has been formed on an element formation region of a semiconductor substrate. CONSTITUTION:In order to increase a width of sidewall parts 7, a third silicon oxide film 6 by a CVD method and by a patterning operation is formed additionally on a second silicon nitride film 5. After the sidewall parts 7 have been formed in this manner, a first silicon nitride film 3 in regions other than lower parts of the sidewall parts 7 is removed by executing an RIE method using a fluorine-based gas; then, a first silicon oxide film 2 and said sidewall parts 7 are removed by a wet etching operation to obtain a mask for thermal oxidation use of a four-layer structure. By this manufacturing method, a semiconductor device provided with an element isolation region which reduces a bird's beak remarkably and whose pattern accuracy is excellent is obtained without exerting an adverse influence by a mechanical stress on a semiconductor substrate.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明は、半導体装置の製造方法に関する。[Detailed description of the invention] (b) Industrial application fields The present invention relates to a method for manufacturing a semiconductor device.

さらに詳しくは、素子分離領域を有する半導体装置の製
造方法に関する。
More specifically, the present invention relates to a method of manufacturing a semiconductor device having an element isolation region.

(ロ)従来の技術 従来から、半導体集積回路の素子分離方法としては半導
体基板上に酸化膜を介してパターニングされた窒・化ケ
イ素膜を熱酸化用マスクとして選択熱酸化に付す方法、
いわゆるロコス法が用いられてきた。第2図にロコス法
の工程図を示す。図中、1はソリコン半導体基板、9は
酸化ケイ素膜、IOはパターニングされた窒化ケイ素膜
である。
(B) Conventional Technology Conventionally, as a method for separating elements of semiconductor integrated circuits, a method is used in which a silicon nitride film patterned on a semiconductor substrate via an oxide film is subjected to selective thermal oxidation using as a mask for thermal oxidation.
The so-called Locos method has been used. Figure 2 shows a process diagram of the Locos method. In the figure, 1 is a silicon semiconductor substrate, 9 is a silicon oxide film, and IO is a patterned silicon nitride film.

第2図1の状態の後、選択灼熱酸化を行うことにより、
窒化ケイ素膜の未被覆部分のシリコン半導体基板上に厚
い酸化ケイ素層8が成長し、素子分離領域が確保される
こととなる。なお、窒化ケイ素膜lOは、通常その後除
去される。そして、上記酸化ケイ素膜9の厚みは通常2
00〜300人とされることが多く、窒化イ素膜IOの
厚みは通常1500〜2500人程度とされている。
After the state shown in FIG. 2, by performing selective scorching oxidation,
A thick silicon oxide layer 8 is grown on the silicon semiconductor substrate in the portion not covered by the silicon nitride film, and an element isolation region is secured. Note that the silicon nitride film IO is usually removed thereafter. The thickness of the silicon oxide film 9 is usually 2
The thickness of the silicon nitride film IO is usually about 1,500 to 2,500.

(ハ)発明が解決しようとする課題 最近の半導体集積回路の高集積化、高密度化に伴い、素
子分離領域をより高精度に形成することが望まれる。そ
して、高精度に形成するには、基2− 本的に熱酸化時に窒化ケイ素膜の側端から回り込んで、
該窒化ケイ素膜の下に形成される酸化ケイ素の層の幅(
いわゆるバーズビークの長さ;第4図12.)をできる
だけ少なくする必要がある。
(c) Problems to be Solved by the Invention With the recent increase in the integration and density of semiconductor integrated circuits, it is desired to form element isolation regions with higher precision. In order to form the silicon nitride film with high precision, it is basically necessary to wrap around from the side edges of the silicon nitride film during thermal oxidation.
The width of the silicon oxide layer formed under the silicon nitride film (
Length of the so-called bird's beak; Fig. 4 12. ) should be minimized as much as possible.

従来のロコス法でかかるバーズビークの長さを減少させ
る方法として、下地層となる酸化ケイ素膜9の厚さを薄
く(通常100〜200人程度)、かつ窒化ケイ素膜1
0の厚さを厚<シ(通常2000〜3000人程度)、
さらに熱酸化温度を高くする方法が採られている。
As a method for reducing the length of the bird's beak in the conventional LOCOS method, the thickness of the silicon oxide film 9 serving as the underlying layer is made thin (usually about 100 to 200 layers), and the silicon nitride film 1 is made thinner.
Thickness of 0 to thickness < shi (usually around 2000 to 3000 people),
Furthermore, a method of increasing the thermal oxidation temperature has been adopted.

しかしこのように窒化ケイ素膜lOを厚くする方法は、
基本的に屈曲や変形し難い厚みを採用することでその端
部への酸化ケイ素の回り込み形成を防止するものゆえ、
この膜の下部の半導体基板に大きな機械的ストレスが加
わり、その結果、半導体基板内に結晶欠陥を発生させて
半導体素子とした際に電流リーク等の不都合を引き起こ
す問題があった。
However, this method of increasing the thickness of the silicon nitride film IO is
Basically, by adopting a thickness that is difficult to bend or deform, it prevents silicon oxide from forming around the edges.
A large mechanical stress is applied to the semiconductor substrate under this film, and as a result, crystal defects are generated in the semiconductor substrate, which causes problems such as current leakage when used as a semiconductor device.

この発明はかかる状況に鑑みなされたものであり、半導
体基板に機械的ストレスを与えることな3− くバーズビークが減少されパターン精度の高い素子分離
領域を形成できる半導体装置の製造方法を提供しようと
するものである。
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce bird's beak and form element isolation regions with high pattern accuracy without applying mechanical stress to the semiconductor substrate. It is something.

(ニ)課・題を解決するための手段 かくしてこの発明によれば、シリコン半導体基板上に、
第1の酸化ケイ素膜を介して薄膜の第1の窒化ケイ素膜
を形成しかつこの上に第2の酸化ケイ素膜を介して厚膜
の第2の窒化ケイ素膜を形成し、この第2の窒化ケイ素
膜を第2の酸化ケイ素膜と共に素子形成領域に対応する
形状にパターニングすると共に、上記第1の窒化ケイ素
膜を上記形状よりも幅広の形状にパターニングし、次い
で、この半導体基板を熱酸化条件に付すことにより該半
導体基板の窒化ケイ素膜未被覆部分に素子分離用酸化ケ
イ素層を形成することを特徴とする半導体装置の製造方
法が提供される。
(d) Means for solving problems/problems Thus, according to the present invention, on a silicon semiconductor substrate,
A thin first silicon nitride film is formed through the first silicon oxide film, and a thick second silicon nitride film is formed thereon through the second silicon oxide film. The silicon nitride film is patterned together with the second silicon oxide film into a shape corresponding to the element formation region, and the first silicon nitride film is patterned into a shape wider than the above shape, and then this semiconductor substrate is thermally oxidized. There is provided a method for manufacturing a semiconductor device, characterized in that a silicon oxide layer for element isolation is formed on a portion of the semiconductor substrate not covered with a silicon nitride film by subjecting the semiconductor substrate to certain conditions.

この発明は、半導体基板の素子形成領域上に、第1の酸
化ケイ素膜、第1の窒化ケイ素膜、第2の酸化ケイ素膜
、第2の窒化ケイ素膜からなる4層構造の熱酸化用マス
クを形成して熱酸化を行う− 点を一つの特徴とするものである。そして、さらに上記
第1の窒化ケイ素膜として薄膜でかつ素子形成領域より
も広幅のものを採用し、かつ上記第2の窒化・ケイ素膜
として厚膜でかつ素子形成領域に対応するパターンのも
のを用いた点を更なる特徴とするものである。
This invention provides a thermal oxidation mask having a four-layer structure consisting of a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a second silicon nitride film on an element formation region of a semiconductor substrate. One of the features is that thermal oxidation is carried out by forming . Furthermore, the first silicon nitride film is thin and wider than the element formation area, and the second silicon nitride film is thick and has a pattern corresponding to the element formation area. The points used here are additional features.

この発明において、第1酸化ケイ素膜は、例えば熱酸化
法やCVD法で形成することができ、その厚みは通常約
50〜200人程度で充分である。
In the present invention, the first silicon oxide film can be formed by, for example, a thermal oxidation method or a CVD method, and a thickness of about 50 to 200 is usually sufficient.

この第1酸化ケイ素膜は、第1窒化ケイ素膜の半導体基
板への悪影響の防止及びエツチング除去性の向上の点で
形成される。
This first silicon oxide film is formed to prevent the first silicon nitride film from having an adverse effect on the semiconductor substrate and to improve etching removability.

第1窒化ケイ素膜は、例えばCVD法等により形成する
ことができ、その厚みは通常約500−1500人とす
るのが適しており、第2窒化ケイ素膜よりも薄い膜厚が
採用される。
The first silicon nitride film can be formed, for example, by a CVD method, and its thickness is usually suitably about 500-1500, and is thinner than the second silicon nitride film.

一方、第2酸化ケイ素膜は、例えばCVD法で形成する
ことができ、その厚みは通常約100〜300人程度で
充分である。また、第2の窒化ケイ素も例えばCVD法
で形成することができ、厚みは第1窒化ケイ素膜よりも
厚くされ、通常2000〜3000人が適している。
On the other hand, the second silicon oxide film can be formed by, for example, a CVD method, and a thickness of about 100 to 300 people is usually sufficient. Further, the second silicon nitride film can also be formed by, for example, the CVD method, and the thickness is made thicker than the first silicon nitride film, and the thickness is usually suitable for 2,000 to 3,000 people.

かかる4層からなる熱酸化用マスクは、半導体基板上に
第1酸化ケイ素膜、第1窒化ケイ素膜、第2酸化ケイ素
膜、第2窒化ケイ素膜をこの順に積層形成した後、パタ
ーニングを行うことにより形成することができる。より
具体的には、4層積層形成後、(a)最上層の第2窒化
ケイ素膜を素子形tc@域と略同寸法の形状にパターニ
ングする工程、(b) CV Dによる酸化ケイ素層の
堆積及び異方性エツチングにより、上記第2窒化ケイ素
膜のパターンの側部にサイドウオール部を形成し、かつ
この第2窒化ケイ素膜及びサイドウオール部の下部以外
の第2酸化ケイ素膜を除去して第1窒化ケイ素膜を露出
させる工程、(c)露出した第1窒化ケイ素膜をエツチ
ングすることにより第2窒化ケイ素膜よりもサイドウオ
ール分幅広の形状にパターニングし、かつサイドウオー
ル部を除去する工程、によって形成することができる。
Such a four-layer thermal oxidation mask is formed by laminating a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a second silicon nitride film in this order on a semiconductor substrate, and then patterning the film. It can be formed by More specifically, after forming the four-layer stack, (a) patterning the uppermost second silicon nitride film into a shape with approximately the same dimensions as the device shape tc@ region, (b) patterning the silicon oxide layer by CVD. Forming a sidewall part on the side of the pattern of the second silicon nitride film by deposition and anisotropic etching, and removing the second silicon nitride film and the second silicon oxide film other than the lower part of the sidewall part. (c) etching the exposed first silicon nitride film to pattern it into a shape wider than the second silicon nitride film by the amount of the sidewall, and removing the sidewall portion; It can be formed by a process.

なお、上記工程(a)のパターニングは例えば、RrE
法により窒化ケイ素の選択エツチング条件下で行うこと
ができる。工程(b)の異方性エツチングは、例えば、
RIE法による酸化ケイ素の選択エッチ・ング条件下で
行うことかできる。なお、第2酸化ケイ素膜の除去はC
VDによる酸化ケイ素層の形成前に行ってもよいが、C
VDによる酸化ケイ素層の堆積後にこの酸化ケイ素層の
エツチングの進行と同時に行うことができる。工程(c
)のエツチングは前記と同様な窒化ケイ素のエツチング
条件下で行うことができる。この際、第1窒化ケイ素膜
の表面も若干エツチングされるが膜厚が大きいのでとく
に不都合は生じない。なお、工程(c)によって露出す
る部位の第1酸化ケイ素膜はとくに除去する必要はない
が、前述のごとく薄膜であるので湿式エツチング等の等
方性エツチングによるサイドウオール部の除去と共に工
程(c)の過程で除去される。
Note that the patterning in the above step (a) is performed using, for example, RrE.
The process can be carried out under selective etching conditions for silicon nitride. The anisotropic etching in step (b) is performed by, for example,
This can be carried out under selective etching conditions for silicon oxide using the RIE method. Note that the removal of the second silicon oxide film is performed using C.
Although it may be performed before forming the silicon oxide layer by VD, C
This can be done simultaneously with the progress of etching of the silicon oxide layer after deposition of the silicon oxide layer by VD. Process (c
) can be carried out under the same silicon nitride etching conditions as described above. At this time, the surface of the first silicon nitride film is also slightly etched, but since the film thickness is large, no particular inconvenience occurs. Note that there is no particular need to remove the first silicon oxide film in the area exposed in step (c), but since it is a thin film as described above, it is necessary to remove the sidewall portion by isotropic etching such as wet etching and remove the first silicon oxide film in step (c). ) are removed during the process.

上述のごとく、第1窒化ケイ素膜の幅広形状のパターン
は、サイドウオール部の幅によって決定される。ここで
サイドウオール部は、第2窒化ケイ素膜の厚みによって
決定されるため、その膜厚を調整することにより制御す
ることができる。但し、第2窒化ケイ素膜の膜厚に比し
て広幅のサイドウオー・ル部を形成する場合は、第2窒
化ケイ素膜形威後にこの窒化ケイ素膜上に第3の酸化ケ
イ素膜を形成し、これを素子形成領域対応形状にパター
ニングし次いで同形状に第2窒化ケイ素膜のパターニン
グを行って二層構造の素子形成領域対応パターンを構威
し、この側部に工程(b)と同様にしてサイドウオール
部を形成処理を行えばよい。
As described above, the wide pattern of the first silicon nitride film is determined by the width of the sidewall portion. Here, since the sidewall portion is determined by the thickness of the second silicon nitride film, it can be controlled by adjusting the film thickness. However, when forming a sidewall portion that is wider than the thickness of the second silicon nitride film, a third silicon oxide film is formed on this silicon nitride film after forming the second silicon nitride film. This is patterned into a shape corresponding to the element formation area, and then a second silicon nitride film is patterned in the same shape to form a two-layer structure pattern corresponding to the element formation area. The sidewall portion may be formed using the following steps.

いずれにせよ、かかるサイドウオール部の幅は通常、2
500〜3500人程度の範囲とするのが適している。
In any case, the width of such sidewall section is usually 2
A range of approximately 500 to 3,500 people is suitable.

なお、この発明において半導体基板の熱酸化は公知の条
件下で行うことができ、通常H,O10゜ガス雰囲気下
で約950〜1100℃の熱処理によって行うのが適し
ている。
In the present invention, the thermal oxidation of the semiconductor substrate can be carried out under known conditions, and it is usually suitable to carry out heat treatment at about 950 to 1100 DEG C. in a 10 DEG gas atmosphere of H and O.

(ホ)作用 熱酸化条件下で、薄膜の第1窒化ケイ素膜の端部、こと
に幅広部分の下方には酸化ケイ素が回り− 込んで形成されるか、この幅広部分の存在により、厚膜
の第2窒化ケイ素膜によるパターンの端部下方への酸化
ケイ素の回り込み形成が著しく抑制又は防止さ・れるこ
ととなる。その結果、半導体基板への機械的ストレスを
著しく低下しっつ厚膜の第2窒化ケイ素膜パターンに対
するバーズビークを減少させることが可能となる。
(e) Operation Under thermal oxidation conditions, silicon oxide wraps around and forms at the edges of the first silicon nitride film, especially below the wide portion, or the presence of the wide portion causes a thick film to form. The second silicon nitride film significantly suppresses or prevents the formation of silicon oxide that wraps around below the ends of the pattern. As a result, it is possible to significantly reduce the mechanical stress on the semiconductor substrate and to reduce the bird's beak caused by the thick second silicon nitride film pattern.

(へ)実施例 シリコン半導体基板(150mmφ)に、熱酸化法によ
って約100人の第1酸化ケイ素膜を形成し、この上に
減圧CVD法によって、約1000人の第1窒化ケイ素
膜、約280人の第2酸化ケイ素膜、約3000人の第
2窒化ケイ素膜をこの順に形成した。次いで、最上層の
第2窒化ケイ素膜を半導体基板内の索子形成領域に対応
する形状にRIE法(フッ素系ガス使用)でパターニン
グし、続いて第2酸化ケイ素膜を同形状にRIE法(フ
ッ素系ガス使用)でパターニングした。
(f) Example A first silicon oxide film of about 100 layers was formed on a silicon semiconductor substrate (150 mmφ) by thermal oxidation, and a first silicon nitride film of about 1,000 layers was formed on this by low pressure CVD, and a first silicon nitride film of about 280 layers A second silicon oxide film of about 3,000 people and a second silicon nitride film of about 3,000 people were formed in this order. Next, the second silicon nitride film, which is the uppermost layer, is patterned by RIE (using fluorine-based gas) in a shape corresponding to the core formation region in the semiconductor substrate, and then the second silicon oxide film is patterned in the same shape by RIE (using fluorine-based gas). (using fluorine gas).

上記パターン形成領域を被覆するように、減圧CVD法
で厚み約2500〜3500人の酸化ケイ素層を形成し
、フッ素系ガスによる異方性エツチングに付すことによ
り、サイドウオール部(幅約0.26μm)を形成させ
た。
A silicon oxide layer with a thickness of approximately 2,500 to 3,500 layers is formed by low-pressure CVD to cover the pattern formation area, and is subjected to anisotropic etching with fluorine gas to form a sidewall portion (width of approximately 0.26 μm). ) was formed.

この状態を、第1図Aに示した。図中、■はシリコン半
導体基板、2は第1酸化ケイ素膜、3は第1窒化ケイ素
膜、4はパターニングされた第2酸化ケイ素膜、5はパ
ターニングされた第2窒化ケイ素膜、7は酸化ケイ素か
らなるサイドウオール部である。
This state is shown in FIG. 1A. In the figure, ■ is a silicon semiconductor substrate, 2 is a first silicon oxide film, 3 is a first silicon nitride film, 4 is a patterned second silicon oxide film, 5 is a patterned second silicon nitride film, and 7 is an oxide film. This is a sidewall part made of silicon.

なお、第1図Bは、サイドウオール部7の幅を増加すべ
く第2の窒化ケイ素膜5の上部にさらにCVD法及びパ
ターニングによる第3の酸化ケイ素膜6を形成させた状
態を示すものである。
Note that FIG. 1B shows a state in which a third silicon oxide film 6 is further formed by CVD and patterning on the second silicon nitride film 5 in order to increase the width of the sidewall portion 7. be.

このようにサイドウオール部7を形成させた後、フッ素
系ガスを用いるRrE法に付すことにより、サイドウオ
ール部7の下部以外の領域の第1窒化ケイ素膜3を除去
し、次いで第1酸化ケイ素膜2並びに該サイドウオール
部7を湿式エツチングにより除去してこの発明の4層構
造の熱酸化用マスクを得た。この状態を第1図Cに示し
た。
After forming the sidewall part 7 in this way, the first silicon nitride film 3 in the area other than the lower part of the sidewall part 7 is removed by subjecting it to the RrE method using fluorine gas, and then the first silicon oxide film 3 is removed from the area other than the lower part of the sidewall part 7. The film 2 and the sidewall portion 7 were removed by wet etching to obtain a thermal oxidation mask having a four-layer structure according to the present invention. This state is shown in FIG. 1C.

9− G− この後、半導体基板をHtO10!ガス雰囲気下、温度
〜1050℃下で熱酸化条件に付すことにより、第1図
りに示すごとく半導体基板露出部分に厚さ約eooo大
の酸化ケイ素層8からなる素子分離領域が形成された。
9-G- After this, the semiconductor substrate was heated with HtO10! By subjecting the semiconductor substrate to thermal oxidation conditions in a gas atmosphere at a temperature of 1050 DEG C., an element isolation region made of a silicon oxide layer 8 having a thickness of approximately eooo was formed in the exposed portion of the semiconductor substrate, as shown in the first diagram.

この素子分離領域とマスクの端部の拡大図を第3図に示
した。
FIG. 3 shows an enlarged view of the element isolation region and the edge of the mask.

このように、本実施例の方法によれば、バーズビーク長
Q、は約0.18μmであり、第4図に示す従来法(ロ
コス法)のQ1約0.44μmに比して半減以下に減少
できていることが判る。なお、第3図及び第4図中の矢
印は、各膜に発生する機械的ストレスの大きさであり、
従来のLOCO8法ではバーズビーク下部の半導体基板
に集中していたが第3図の実施例ではストレスが分散さ
れている事を示している。
As described above, according to the method of this embodiment, the bird's beak length Q is approximately 0.18 μm, which is reduced by more than half of Q1 of approximately 0.44 μm in the conventional method (Locos method) shown in FIG. It turns out that it is done. Note that the arrows in FIGS. 3 and 4 indicate the magnitude of mechanical stress generated in each film,
In the conventional LOCO8 method, the stress was concentrated on the semiconductor substrate below the bird's beak, but the embodiment shown in FIG. 3 shows that stress is dispersed.

(ト)発明の効果 この発明の製造方法によれば、半導体基板に機械的スト
レスによる悪影響を与えることなく、バーズビークが著
しく減少されパターン精度に優れた素子分離領域を有す
る半導体装置を得ることができる。
(G) Effects of the Invention According to the manufacturing method of the present invention, it is possible to obtain a semiconductor device having an element isolation region with significantly reduced bird's beak and excellent pattern accuracy without adversely affecting the semiconductor substrate due to mechanical stress. .

従って、半導体基板内に微細化され高集積化された素子
を有する半導体装置の製造分野においてその有用・性は
極めて大なるものである。
Therefore, its usefulness and usefulness are extremely great in the field of manufacturing semiconductor devices having miniaturized and highly integrated elements within a semiconductor substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図A−Dは、各々この発明の製造方法の工程説明図
、第2図A及びBは従来法の工程説明図、第3図はこの
発明によって形成された素子分離領域とマスク端部との
関係を示す拡大断面図、第4図は従来法による第3図対
応図である。 1・・・・・シリコン半導体基板、 2・・・・・・第1酸化ケイ素膜、 3・・・・・・第1窒化ケイ素膜、 4・・・・・第2酸化ケイ素膜、 5・・・・・・第2窒化ケイ素膜、 6・・・・・第3酸化ケイ素膜 7・・・・・・サイドウオール部、 8・・・・・・酸化ケイ素層。 第1図A 図B 第2図A 0 第1 図C 第2図B
1A to 1D are process explanatory diagrams of the manufacturing method of the present invention, FIGS. 2A and B are process explanatory diagrams of the conventional method, and FIG. 3 is an element isolation region and mask edge formed by the present invention. FIG. 4 is an enlarged cross-sectional view showing the relationship with FIG. 4, and is a diagram corresponding to FIG. 3 according to the conventional method. 1... Silicon semiconductor substrate, 2... First silicon oxide film, 3... First silicon nitride film, 4... Second silicon oxide film, 5. ...Second silicon nitride film, 6...Third silicon oxide film 7...Side wall portion, 8...Silicon oxide layer. Figure 1 A Figure B Figure 2 A 0 Figure 1 C Figure 2 B

Claims (1)

【特許請求の範囲】[Claims] 1、シリコン半導体基板上に、第1の酸化ケイ素膜を介
して薄膜の第1の窒化ケイ素膜を形成しかっこの上に第
2の酸化ケイ素膜を介して厚膜の第2の窒化ケイ素膜を
形成し、この第2の窒化ケイ素膜を第2の酸化ケイ素膜
と共に素子形成領域に対応する形状にパターニングする
と共に、上記第1の窒化ケイ素膜を上記形状よりも幅広
の形状にパターニングし、次いで、この半導体基板を熱
酸化条件に付すことにより該半導体基板の窒化ケイ素膜
未被覆部分に素子分離用酸化ケイ素層を形成することを
特徴とする半導体装置の製造方法。
1. A thin first silicon nitride film is formed on a silicon semiconductor substrate via a first silicon oxide film. A thick second silicon nitride film is formed on the bracket via a second silicon oxide film. This second silicon nitride film is patterned together with a second silicon oxide film into a shape corresponding to the element formation region, and the first silicon nitride film is patterned into a shape wider than the above shape, and then . A method of manufacturing a semiconductor device, comprising: forming a silicon oxide layer for element isolation on a portion of the semiconductor substrate not covered with a silicon nitride film by subjecting the semiconductor substrate to thermal oxidation conditions.
JP20360389A 1989-08-04 1989-08-04 Manufacture of semiconductor device Pending JPH0366127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20360389A JPH0366127A (en) 1989-08-04 1989-08-04 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20360389A JPH0366127A (en) 1989-08-04 1989-08-04 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0366127A true JPH0366127A (en) 1991-03-20

Family

ID=16476783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20360389A Pending JPH0366127A (en) 1989-08-04 1989-08-04 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0366127A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799190A (en) * 1993-05-21 1995-04-11 Hyundai Electron Ind Co Ltd Preparation of semiconductor element field oxide film

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0799190A (en) * 1993-05-21 1995-04-11 Hyundai Electron Ind Co Ltd Preparation of semiconductor element field oxide film

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