JPS5854651A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5854651A
JPS5854651A JP15324281A JP15324281A JPS5854651A JP S5854651 A JPS5854651 A JP S5854651A JP 15324281 A JP15324281 A JP 15324281A JP 15324281 A JP15324281 A JP 15324281A JP S5854651 A JPS5854651 A JP S5854651A
Authority
JP
Japan
Prior art keywords
film
silicon
forming
groove
oxide film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15324281A
Other languages
Japanese (ja)
Other versions
JPH0258778B2 (en
Inventor
Fujiki Tokuyoshi
徳「よし」 藤樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15324281A priority Critical patent/JPS5854651A/en
Publication of JPS5854651A publication Critical patent/JPS5854651A/en
Publication of JPH0258778B2 publication Critical patent/JPH0258778B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76227Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials the dielectric materials being obtained by full chemical transformation of non-dielectric materials, such as polycristalline silicon, metals

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To suppress the oxidation of a silicon substrate under a silicon nitrided film at the selectively oxidizing time and to prevent the distortion of the substrate by forming a silicon etching groove and then forming a polycrystalline silicon film layer on the side surface of the groove. CONSTITUTION:A silicon oxidized film 12 is formed by a thermal oxidation method on the surface of an N type silicon substrate 11, and a silicon nitrided film 13 is covered by a vapor growth method on the film 12. Then, the films 13, 12 are selectively etched and removed by a photoprocess method, and the surface of the exposed substrate 11 is etched bya plasma etching, thereby forming a groove 14. Subsequently, a polycrystalline silicon film 16 is formed by a vapor growth method, and the film 16 is then etched to remove the film 16 except the side surface of the groove 14. Thereafter, a buried silicon oxidized film 15 is formed by a thermal oxidation method.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法に係)、脣に素子分離用
の堀設シリコン酸化膜の形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming a trenched silicon oxide film for element isolation.

集積回路等の半導体装置の製造方法において、集積度の
向上、および製作工程の簡素化のために埋設酸化膜によ
る誘電体分離、さらには該埋設酸化膜を用いた自己整合
(8elf−allgnment )技術による素子形
成がさかんに行なわれている。この埋設酸化膜を形成す
る方法としては、最も容易に使用できる、シリコン窒化
膜を耐酸化膜とした熱酸化による選択酸化法が主に用い
られている。
In the manufacturing method of semiconductor devices such as integrated circuits, dielectric isolation using a buried oxide film and self-alignment (8elf-allgnment) technology using the buried oxide film are used to improve the degree of integration and simplify the manufacturing process. Element formation using this method is being actively carried out. As a method for forming this buried oxide film, a selective oxidation method using thermal oxidation using a silicon nitride film as an oxidation-resistant film, which is the easiest to use, is mainly used.

従来の選択酸化法の1例を第1図〜第3図により説明す
る。まず、n型シリコン基板11表面にシリコン酸化膜
12及びシリコン窒化膜13t−。
An example of a conventional selective oxidation method will be explained with reference to FIGS. 1 to 3. First, a silicon oxide film 12 and a silicon nitride film 13t- are formed on the surface of an n-type silicon substrate 11.

順次、形成する(第1図)。次にフォトプロセス法を用
い、選択エツチングを行なりて、素子分離領域上のシリ
コン窒化膜13.シリコン酸化膜12’e除去し、露出
したシリコン基板表面をエツチングして溝14f:形成
する(第2図)、シかる後、熱酸化法を用いて埋設シリ
コ/酸化膜15を形成し、溝14を埋める。
Form them sequentially (Fig. 1). Next, using a photo process method, selective etching is performed to etch the silicon nitride film 13 on the element isolation region. The silicon oxide film 12'e is removed and the exposed silicon substrate surface is etched to form a groove 14f (FIG. 2). After etching, a buried silicon/oxide film 15 is formed using a thermal oxidation method to form the groove. Fill in 14.

こうして素子分離が行なわれ、それぞれ分離された島状
領域に所望の素子を形成することになる。
Element isolation is thus performed, and desired elements are formed in each isolated island region.

しかし、この製造方法によると埋設シリコン酸化膜を形
成する時に、酸素(Os)が酸化膜中を、シリコン窒化
膜の下にも拡散して行く為、横方向酸化が生じ、シリコ
/窒化膜下のシリコン基板も少し酸化され、いわゆる’
 bird beak″lが形成される。この為に、パ
ターン幅の減少が生ずる。たとえば、シリコン酸化膜約
20 OA、シリコン窒化膜約100OA、シリコンエ
ツチング溝深さ約α6fi*埋設シリコン酸化膜膜厚約
L2Jmとするとパターン幅は約2μm減少することと
な夛、このような大きなパターン幅減少は、集積度を向
上する上で大きな問題となる。その上、窒化膜下にシリ
コン酸化膜が部分的に形成されることによシ、シリコン
基板内に大きな歪が加えられることとなシ、しいては結
晶欠陥の発生となる等、素子形成を行なう上での大きな
欠点となっている。
However, according to this manufacturing method, when forming a buried silicon oxide film, oxygen (Os) diffuses into the oxide film and under the silicon nitride film, resulting in lateral oxidation and The silicon substrate is also slightly oxidized, so-called '
A bird beak''l is formed. Therefore, the pattern width is reduced.For example, silicon oxide film is approximately 20 OA, silicon nitride film is approximately 100 OA, silicon etching groove depth is approximately α6fi* buried silicon oxide film thickness is approximately If L2Jm is used, the pattern width will be reduced by about 2 μm, and such a large pattern width reduction will be a big problem in improving the degree of integration.Furthermore, the silicon oxide film under the nitride film will partially When formed, a large strain is applied to the silicon substrate, resulting in the generation of crystal defects, which is a major drawback in device formation.

本発明は上記の点に鑑み、埋設シリコン酸化膜層を形成
する際の横方向酸化を抑えて、基板内での歪発生を防止
すると共に、素子分離領域の占有面積を小さくして集積
度向上を可能とした半導体装置の製造方法を提供するも
のである。
In view of the above points, the present invention suppresses lateral oxidation when forming a buried silicon oxide film layer, prevents strain from occurring within the substrate, and improves the degree of integration by reducing the area occupied by the element isolation region. The present invention provides a method for manufacturing a semiconductor device that makes it possible to perform the following steps.

本発明の主たる所は、シリコン・エツチング溝金形成し
た後に、溝の側面に多結晶シリコン膜層を形成する工程
を加えることにより、選択酸化時にシリコ/窒化膜下の
シリコン基板が酸化されることを防止することにある。
The main feature of the present invention is that by adding a step of forming a polycrystalline silicon film layer on the sides of the trench after forming the silicon etching trench, the silicon substrate under the silicon/nitride film is oxidized during selective oxidation. The goal is to prevent

次に実施例に従かい本発明の詳細な説明する。Next, the present invention will be explained in detail according to examples.

第4図〜第8図は、シリコン基板内に約1.1μmの深
さで埋設された埋設酸化膜の製造工程の主な断面図であ
る。
4 to 8 are main cross-sectional views of the manufacturing process of a buried oxide film buried in a silicon substrate to a depth of about 1.1 μm.

ts4図は、n型シリコン基板11表面に、熱酸化法に
よシ、シリコン酸化膜を約200^の膜厚で形成し、そ
の上にシリコン窒化膜13t″、気相成長(C0V、D
)ffiK!り、膜厚的100OAで、被層した所であ
る。次にフォトプロセス法を用いて選択的に、埋設酸化
膜形成領域上のシリコン窒化膜13.シリコン酸化膜1
2をエツチング除去し、露出したシリコン基板表面を、
CCJ14  i3系によるプラズマエツチングを用い
て食刻し、溝14t−10,6μmの深さで、形成する
(第5図)。
In the ts4 diagram, a silicon oxide film with a thickness of about 200^ is formed on the surface of an n-type silicon substrate 11 by a thermal oxidation method, and a silicon nitride film 13t'' is formed on it by vapor phase growth (C0V, D
)ffiK! It is coated with a film thickness of 100 OA. Next, using a photo process method, the silicon nitride film 13. Silicon oxide film 1
2 was removed by etching, and the exposed silicon substrate surface was
A groove 14t-10.6 .mu.m deep is formed by etching using plasma etching using CCJ14 i3 system (FIG. 5).

しかる後に多結晶シリコン膜16t−気相成長法によに
形成する(第6図)。この時の膜厚は、埋設シリコン酸
化膜の所望の膜厚によって変化し、埋設シリコン酸化膜
の膜厚が約t2μ泗であれば、多結晶シリコン膜の膜厚
はα5μm11度が適轟である。
Thereafter, a polycrystalline silicon film 16t is formed by vapor phase growth (FIG. 6). The film thickness at this time varies depending on the desired thickness of the buried silicon oxide film, and if the film thickness of the buried silicon oxide film is about t2 μm, the appropriate thickness of the polycrystalline silicon film is α5 μm 11 degrees. .

次に多結晶シリコン膜16のエツチングを行なう。Next, polycrystalline silicon film 16 is etched.

このとき、エツチング方法としては、CCJ24系ガス
による異方性プラズマエツチングを用い、基板表面食菌
をエツチングガスにさらす。すると、エツチングに方向
性があ〉、基板表面に働直な方向からしかエツチングさ
れない為に、シリコン・エツチング溝14の側面以外の
多結晶シリコ/膜を除去することとなる(第7図)、こ
の時、多結晶シリコン膜エツチング後、露出し九シリコ
ン基板を再度エツチングしても良い、しかる後、熱酸化
法を用いて埋設シリコン酸化膜15を形成する(第8図
)。すると、選択酸化時に、溝14の下面は従来通〉に
酸化されるが、側面は、多結晶シリコン膜16が酸化さ
れ、シリコン基板11自体は酸化されない。
At this time, as the etching method, anisotropic plasma etching using CCJ24 gas is used, and the phagocytic bacteria on the substrate surface are exposed to the etching gas. Then, since the etching is directional and etching is performed only from the direction that is perpendicular to the substrate surface, the polycrystalline silicon/film other than the side surfaces of the silicon etching groove 14 must be removed (FIG. 7). At this time, after etching the polycrystalline silicon film, the exposed silicon substrate may be etched again. Thereafter, a buried silicon oxide film 15 is formed using a thermal oxidation method (FIG. 8). Then, during selective oxidation, the bottom surface of the groove 14 is oxidized as in the conventional manner, but on the side surface, the polycrystalline silicon film 16 is oxidized and the silicon substrate 11 itself is not oxidized.

従がって、シリコン窒化膜16の下に、選択酸化時に、
シリコン酸化膜が形成されることは無い。
Therefore, under the silicon nitride film 16, during selective oxidation,
No silicon oxide film is formed.

その結果、選択酸化によるノくターン幅の減少や、結晶
歪の発生を防止することが可能となる。
As a result, it is possible to prevent a reduction in the turn width and generation of crystal distortion due to selective oxidation.

以上、詳細に説明した様に、本発明によると、選択酸化
法によシ埋設シリコン酸化膜を形成する時に、シリコン
・エツチング溝形成後、溝の側面のみに多結晶シリコン
膜層を形成することにより、熱酸化時の横方向酸化を防
止する。これによ)、選択酸化時のパターン幅細化や結
晶歪の発生を防止することが可能となり、シいては集積
度の向上や、歩留向上が期待できる。
As described in detail above, according to the present invention, when forming a buried silicon oxide film by selective oxidation, after forming a silicon etching groove, a polycrystalline silicon film layer is formed only on the side surfaces of the groove. This prevents lateral oxidation during thermal oxidation. This makes it possible to prevent thinning of the pattern width and generation of crystal distortion during selective oxidation, and is therefore expected to improve the degree of integration and yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第3図に従来の製造方法を工程順に示した断面
図であり、第4図〜第8図に本発明の実施例の製造方法
の主たる工St−示す断面図である。 伺、図中の記号は下記の事物と対応している。
FIGS. 1 to 3 are cross-sectional views showing the conventional manufacturing method in the order of steps, and FIGS. 4 to 8 are cross-sectional views showing the main process St of the manufacturing method of the embodiment of the present invention. Please note that the symbols in the diagram correspond to the following items.

Claims (1)

【特許請求の範囲】[Claims] 半導体基板表両に耐酸化性膜を用いて埋設シリコン酸化
膜を形成する半導体装置の製造方法において、耐酸化性
膜パターノ設けられていない半導体基板表面を食刻し、
溝を形成する工程と、該溝の儒■に多結晶シリコン膜層
を形成する工程と、しかる後に 埋設シリ:1y酸化膜
を形成する工程とを含むことを特徴とする半導体装置の
製造方法。
In a method for manufacturing a semiconductor device in which a buried silicon oxide film is formed using an oxidation-resistant film on both surfaces of a semiconductor substrate, etching a surface of the semiconductor substrate on which an oxidation-resistant film pattern is not provided,
A method for manufacturing a semiconductor device, comprising the steps of forming a trench, forming a polycrystalline silicon film layer in the trench, and then forming a buried silicon oxide film.
JP15324281A 1981-09-28 1981-09-28 Manufacture of semiconductor device Granted JPS5854651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15324281A JPS5854651A (en) 1981-09-28 1981-09-28 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15324281A JPS5854651A (en) 1981-09-28 1981-09-28 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5854651A true JPS5854651A (en) 1983-03-31
JPH0258778B2 JPH0258778B2 (en) 1990-12-10

Family

ID=15558160

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15324281A Granted JPS5854651A (en) 1981-09-28 1981-09-28 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5854651A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4551911A (en) * 1982-12-28 1985-11-12 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US5084413A (en) * 1986-04-15 1992-01-28 Matsushita Electric Industrial Co., Ltd. Method for filling contact hole
US5472903A (en) * 1994-05-24 1995-12-05 United Microelectronics Corp. Isolation technology for sub-micron devices

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0620028A (en) * 1992-06-29 1994-01-28 Honda Motor Co Ltd On-vehicle ecu device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54589A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Burying method of insulator

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54589A (en) * 1977-06-03 1979-01-05 Hitachi Ltd Burying method of insulator

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4551911A (en) * 1982-12-28 1985-11-12 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device
US5084413A (en) * 1986-04-15 1992-01-28 Matsushita Electric Industrial Co., Ltd. Method for filling contact hole
US5472903A (en) * 1994-05-24 1995-12-05 United Microelectronics Corp. Isolation technology for sub-micron devices

Also Published As

Publication number Publication date
JPH0258778B2 (en) 1990-12-10

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