JPS6231492B2 - - Google Patents
Info
- Publication number
- JPS6231492B2 JPS6231492B2 JP386480A JP386480A JPS6231492B2 JP S6231492 B2 JPS6231492 B2 JP S6231492B2 JP 386480 A JP386480 A JP 386480A JP 386480 A JP386480 A JP 386480A JP S6231492 B2 JPS6231492 B2 JP S6231492B2
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- silicon oxide
- oxidation
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000003647 oxidation Effects 0.000 claims description 28
- 238000007254 oxidation reaction Methods 0.000 claims description 28
- 239000004065 semiconductor Substances 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 20
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 38
- 229910052814 silicon oxide Inorganic materials 0.000 description 38
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
- Weting (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、写真食
刻技術の限界にほぼ等しい微細なパターン巾を有
する酸化硅素膜を半導体基板に選択的に形成可能
な半導体装置の製造方法を提供することを目的と
する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and a method for manufacturing a semiconductor device in which a silicon oxide film having a fine pattern width approximately equal to the limit of photolithography can be selectively formed on a semiconductor substrate. The purpose is to provide
従来、半導体装置の製造において、同一半導体
基板上に形成した素子間の分離を行なうために素
子間に厚い酸化硅素膜いわゆるフイールド酸化膜
を形成することが行なわれている。前記酸化硅素
膜と半導体基板との段差を少なくする方法とし
て、第１図に示すように半導体基板１上に窒化硅
素膜等の耐酸化性絶縁膜２を形成した後Ａ、耐酸
化性絶縁膜２を選択的にエツチングしＢ、残存す
る耐酸化性絶縁膜２をマスクとして前記半導体基
板１を選択的に酸化硅素膜３に変換するＣ方法が
ある。かかる方法では通常の写真食刻法により前
記耐酸化性絶縁膜２に所定のパターンを形成する
手法をとつていることから、前記パターンの最小
寸法は写真食刻法に依存し、写真食刻技術の限界
以下の寸法は形成できない。 Conventionally, in the manufacture of semiconductor devices, a thick silicon oxide film, so-called field oxide film, is formed between the elements in order to isolate the elements formed on the same semiconductor substrate. As a method of reducing the level difference between the silicon oxide film and the semiconductor substrate, as shown in FIG. 1, after forming an oxidation-resistant insulating film 2 such as a silicon nitride film on the semiconductor substrate 1, There is a method B in which the semiconductor substrate 1 is selectively etched into a silicon oxide film 3, and a method C in which the semiconductor substrate 1 is selectively converted into a silicon oxide film 3 using the remaining oxidation-resistant insulating film 2 as a mask. Since this method uses a method of forming a predetermined pattern on the oxidation-resistant insulating film 2 by a normal photo-etching method, the minimum dimension of the pattern depends on the photo-etching method. Dimensions below the limit cannot be formed.
また形成された酸化硅素膜３は、その形成深さ
ｄとほぼ同じ寸法で前記耐酸化性絶縁膜２のパタ
ーンの下部にも形成される。したがつて第１図Ｃ
に示すように酸化硅素膜３のパターン巾ａは、前
記耐酸化性絶縁膜のパターン巾ｌより広くなり、
酸化硅素膜３の厚さをｄとするとａ＝ｌ＋2dと
なる。前記酸化硅素膜３は素子間分離が目的であ
り、素子の能動領域ではないため、パターン巾は
小さい方が好ましい。しかし従来法では前述のよ
うに写真食刻法の限界パターン寸法ｌより、必ず
広くなるという欠点があり、高密度化のさまたげ
となつている。 Furthermore, the formed silicon oxide film 3 is also formed under the pattern of the oxidation-resistant insulating film 2 with approximately the same dimensions as its formation depth d. Therefore, Figure 1C
As shown in , the pattern width a of the silicon oxide film 3 is wider than the pattern width l of the oxidation-resistant insulating film,
If the thickness of the silicon oxide film 3 is d, then a=l+2d. Since the purpose of the silicon oxide film 3 is to isolate devices and not to form an active region of the device, it is preferable that the pattern width be small. However, as mentioned above, the conventional method has the disadvantage that the pattern size always becomes wider than the limit pattern size l of the photolithography method, which is an obstacle to increasing the density.
本発明は、耐酸化性絶縁膜上に多結晶半導体膜
よりなるパターンを形成し、これを酸化してパタ
ーン間隔を縮め、この酸化により形成された酸化
膜にて選択酸化用の耐酸化性絶縁膜パターンを形
成するものであつて、従来に比べより微細で高密
度な選択酸化膜を半導体基板に形成するものであ
る。以下、本発明の方法を図面とともに説明す
る。 The present invention forms a pattern made of a polycrystalline semiconductor film on an oxidation-resistant insulating film, oxidizes the pattern to reduce the pattern interval, and uses the oxide film formed by this oxidation to form an oxidation-resistant insulator for selective oxidation. This method forms a film pattern, and forms a finer, higher-density selective oxide film on a semiconductor substrate than conventional methods. The method of the present invention will be explained below with reference to the drawings.
本発明の第１の実施例を第２図に従つて説明す
る。一導電型のたとえばシリコン半導体基板１１
上にたとえばシリコン窒化膜（Si3N4膜）よりな
る耐酸化性絶縁膜１２を例えば1000Å、多結晶硅
素膜１３を例えば5000Åを順に形成するＡ。通常
の写真食刻法により前記多結晶硅素膜１３に所定
のパターンを形成するＢ。次に高温酸素雰囲気中
で前記多結晶硅素膜１３をすべて酸化硅素膜１４
に変換するＣ。この場合、酸化硅素膜１４の体積
は、多結膜硅素膜１３のほぼ２倍程度に膨張す
る。したがつて、多結晶硅素膜１３の膜厚をｄと
すれば１４のパターン間が縮まりその間隔の巾も
最初のパターン間隔ｌよりも2dだけ細くなり
（ｌ−2d）となる。 A first embodiment of the present invention will be described with reference to FIG. For example, a silicon semiconductor substrate 11 of one conductivity type.
An oxidation-resistant insulating film 12 made of, for example, a silicon nitride film (Si 3 N 4 film) is formed thereon to a thickness of, for example, 1000 Å, and a polycrystalline silicon film 13 is formed to a thickness of, for example, 5000 Å in this order. Step B: A predetermined pattern is formed on the polycrystalline silicon film 13 by a normal photolithography method. Next, in a high-temperature oxygen atmosphere, all the polycrystalline silicon film 13 is removed from the silicon oxide film 14.
Convert to C. In this case, the volume of the silicon oxide film 14 expands to approximately twice the volume of the multi-conjunctival silicon film 13. Therefore, if the thickness of the polycrystalline silicon film 13 is d, the distance between the patterns 14 will be reduced and the width of the interval will be 2d narrower than the initial pattern interval l (l-2d).
次に前記酸化硅素膜１４を食刻マスクとして、
耐酸化性絶縁膜１２をリン酸あるいはCF4等のガ
スプラズマ雰囲気中で選択的に食刻し、（ｌ−
2d）のパターン巾（間隔）を有する耐酸化性絶
縁膜パターンを形成するＤ。その後、酸化硅素膜
１４を、例えば弗酸と水の混合比が２：10の弗酸
系水溶液で除去するＥ。さらに、（ｌ−2d）のパ
ターン巾を有する耐酸化性絶縁膜１２をマスクと
して基板１１を選択酸化し、基板１１の露出領域
に酸化硅素膜１５を多結晶硅素膜１３とほぼ等し
い厚さｄ（例えば5000Å）で形成する。この際、
酸化硅素膜１５は耐酸化性絶縁膜１２のパターン
巾に比べて横方向に2dだけ広がりを持つが、耐
酸化性絶縁膜１２のパターン巾が（ｌ−2d）で
あることから、酸化硅素膜１５の全体巾は、多結
晶硅素膜１３のパターン巾と等しい値ｌとなる。
この様に、多結晶硅素膜１３を酸化硅素膜１４に
変換し多結晶硅素膜１３のパターン巾（間隔）を
縮小するという工程を設けることにより、多結晶
硅素膜１３のパターン巾に忠実な酸化硅素膜１５
が形成できる。 Next, using the silicon oxide film 14 as an etching mask,
The oxidation-resistant insulating film 12 is selectively etched in a gas plasma atmosphere of phosphoric acid or CF4 , etc.
D) forming an oxidation-resistant insulating film pattern having a pattern width (interval) of 2d). Thereafter, the silicon oxide film 14 is removed using, for example, a hydrofluoric acid-based aqueous solution with a mixing ratio of hydrofluoric acid and water of 2:10. Furthermore, the substrate 11 is selectively oxidized using the oxidation-resistant insulating film 12 having a pattern width of (l-2d) as a mask, and a silicon oxide film 15 is formed on the exposed region of the substrate 11 to a thickness d that is approximately equal to that of the polycrystalline silicon film 13. (for example, 5000 Å). On this occasion,
The silicon oxide film 15 has a width of 2d in the lateral direction compared to the pattern width of the oxidation-resistant insulating film 12, but since the pattern width of the oxidation-resistant insulating film 12 is (l-2d), the silicon oxide film The overall width of the polycrystalline silicon film 13 is equal to the pattern width of the polycrystalline silicon film 13 .
In this way, by providing the process of converting the polycrystalline silicon film 13 into the silicon oxide film 14 and reducing the pattern width (interval) of the polycrystalline silicon film 13, oxidation that is faithful to the pattern width of the polycrystalline silicon film 13 can be performed. Silicon film 15
can be formed.
以上の如く、本発明の方法によれば、写真食刻
の限界パターン寸法にほぼ等しい酸化硅素膜が形
成でき、よりいつそう半導体装置の高密度化が可
能となる。 As described above, according to the method of the present invention, it is possible to form a silicon oxide film that is approximately equal to the critical pattern size of photolithography, thereby making it possible to increase the density of semiconductor devices more quickly.
なお、前記多結晶硅素膜１２の膜厚は、前記基
板に形成する酸化硅素膜１５と同等以上の膜厚を
また多結晶硅素膜を変換して形成する酸化硅素膜
１４の膜厚は、基板に形成する酸化硅素膜１５の
２倍以上の膜厚に形成すれば、基板への酸化硅素
膜の形成巾を小さくすることができる。 The thickness of the polycrystalline silicon film 12 is equal to or greater than the thickness of the silicon oxide film 15 formed on the substrate, and the thickness of the silicon oxide film 14 formed by converting the polycrystalline silicon film is If the silicon oxide film 15 is formed to have a thickness twice or more than that of the silicon oxide film 15, the width of the silicon oxide film formed on the substrate can be reduced.
また素子間分離のため、酸化硅素膜１５下にイ
オン注入法等により高濃度のチヤンネルストツパ
等の拡散層（図示せず）を形成する場合、多結晶
硅素膜を変換した酸化硅素膜１４のパターンをマ
スクとして不純物拡散することによりこの不純物
拡散層の巾も酸化硅素膜１５と同様に多結晶硅素
膜１３のパターンとのずれを少なく形成できる。 In addition, when forming a highly concentrated diffusion layer (not shown) such as a channel stopper under the silicon oxide film 15 by ion implantation or the like for isolation between elements, the silicon oxide film 14 converted from a polycrystalline silicon film may be used. By diffusing impurities using the pattern as a mask, the width of this impurity diffusion layer can be formed with less deviation from the pattern of the polycrystalline silicon film 13, similar to the silicon oxide film 15.
さらに、第２図Ｄの耐酸化性絶縁膜１２の選択
食刻と同時に基板１１を食刻する様な場合にも本
発明は適用できる。この場合、スパタツタエツチ
ング法等により第３図Ａに示すように、耐酸化性
絶縁膜１２のパターンに忠実に食刻できるとき
は、１２のパターン間隔は前記と同様（ｌ−
2d）でよい。しかしながら、一般的にはアンダ
ーカツトにより第３図Ｂに示すように基板のエツ
チング部分のパターン巾が2t分広くなり、したが
つて基板中での酸化硅素膜巾は2d＋2tだけ増加す
るので、耐酸化性絶縁膜１２のパターン間隔が
（ｌ−2d−2t）となるように多結晶硅素膜１３お
よび酸化硅素膜１４の膜厚を選ぶことが好まし
い。 Furthermore, the present invention can be applied to a case where the substrate 11 is etched at the same time as the selective etching of the oxidation-resistant insulating film 12 shown in FIG. 2D. In this case, if the pattern of the oxidation-resistant insulating film 12 can be faithfully etched by sputter etching or the like as shown in FIG.
2d) is fine. However, in general, due to undercutting, the pattern width of the etched portion of the substrate increases by 2t as shown in Figure 3B, and therefore the silicon oxide film width in the substrate increases by 2d + 2t. It is preferable to select the thicknesses of the polycrystalline silicon film 13 and the silicon oxide film 14 so that the pattern spacing of the silicon oxide film 12 is (l-2d-2t).
第２の実施例を第４図に従つて説明する。半導
体基板での欠陥発生を防止する目的で、半導体基
板１１と耐酸化性絶縁膜１２の間に例えば500〜
1000Åの酸化硅素膜１６を形成する。第２図Ｄま
での工程は、第１の実施例と同様に用いる。第２
図Ｄののち、酸化硅素膜１４をマスクにして、イ
オン注入法等により半導体基板に前記基板１１と
同じ導電型の不純物層１７を高濃度に形成する
（第４図Ａ）。次に酸化硅素膜１４を除去する。こ
のとき耐酸化性絶縁膜１２と基板１１間に形成し
た酸化硅素膜１６も同時に選択的に食刻される
Ｂ。つづいて前記耐酸化硅素膜をマスクとして厚
い酸化硅素膜１８を形成するＣ。 A second embodiment will be described with reference to FIG. For the purpose of preventing the occurrence of defects in the semiconductor substrate, a layer of, for example, 500~
A silicon oxide film 16 of 1000 Å is formed. The steps up to FIG. 2D are used in the same manner as in the first embodiment. Second
After FIG. D, using the silicon oxide film 14 as a mask, an impurity layer 17 of the same conductivity type as the substrate 11 is formed at a high concentration on the semiconductor substrate by ion implantation or the like (FIG. 4A). Next, the silicon oxide film 14 is removed. At this time, the silicon oxide film 16 formed between the oxidation-resistant insulating film 12 and the substrate 11 is also selectively etched at the same time. Next, a thick silicon oxide film 18 is formed using the oxidation-resistant silicon film as a mask.
この場合、酸化硅素膜１８のパターン巾は第４
図Ｂの工程での酸化硅素膜１６のアンダーカツト
２０のために第１の実施例よりもパターン巾が広
くなるが、酸化硅素膜１８形成後の高濃度不純物
層１７は膜１４のパターンにて形成されるため、
そのパターン巾は第１の実施例のパターン寸法ｌ
以内に微少に形成できる。したがつて、従来と異
なり能動素子を形成する領域１９のパターン巾の
減少は少なく半導体装置の高密度化、高集積化が
可能である。 In this case, the pattern width of the silicon oxide film 18 is the fourth
Although the pattern width is wider than that in the first embodiment due to the undercut 20 of the silicon oxide film 16 in the step of FIG. Because it is formed,
The pattern width is the pattern dimension l of the first embodiment.
can be formed minutely within Therefore, unlike the prior art, the pattern width of the region 19 in which active elements are formed is less reduced, and it is possible to increase the density and integration of the semiconductor device.
以上のように、本発明は微細な素子間分離用等
の絶縁膜を半導体基板に選択形成することができ
高密度な半導体集積回路の製造に大きく寄与する
ものである。 As described above, the present invention can selectively form an insulating film for fine isolation between elements on a semiconductor substrate, and greatly contributes to the production of high-density semiconductor integrated circuits.
第１図Ａ，Ｂ，Ｃは従来の選択酸化工程図、第
２図Ａ〜Ｆは本発明の一実施例にかかる選択酸化
工程図、第３図Ａ，Ｂは基板をエツチングした状
態の断面図、第４図Ａ，Ｂ，Ｃは本発明の他の実
施例にかかる選択酸化工程図である。
１１……半導体基板、１２……耐酸化性絶縁物
膜、１３……多結晶硅素膜、１４……酸化硅素
膜、１５，１８……酸化硅素膜、１７……拡散
層。
Figures 1A, B, and C are diagrams of a conventional selective oxidation process, Figures 2A to F are diagrams of a selective oxidation process according to an embodiment of the present invention, and Figures 3A and B are cross sections of the etched substrate. 4A, B, and C are selective oxidation process diagrams according to other embodiments of the present invention. 11... Semiconductor substrate, 12... Oxidation-resistant insulating film, 13... Polycrystalline silicon film, 14... Silicon oxide film, 15, 18... Silicon oxide film, 17... Diffusion layer.
Claims (1)
硅素膜を順に形成する工程と、前記多結晶硅素膜
に、所定のパターンを形成し、かつ前記多結晶硅
素膜をすべて酸化膜に変換して第１の酸化膜を形
成する工程と、前記第１の酸化膜をマスクとして
前記耐酸化性絶縁膜を食刻する工程と、前記第１
の酸化膜を除去する工程とを含んでなる半導体装
置の製造方法。 ２ 耐酸化性絶縁膜パターンをマスクとして前記
半導体基板を酸化し、第２の酸化膜を形成する工
程を含む特許請求の範囲第１項に記載の半導体装
置の製造方法。 ３ 耐酸化性絶縁膜パターンをマスクとして、前
記半導体基板を食刻する工程を含む特許請求の範
囲第１項に記載の半導体装置の製造方法。[Claims] 1. A step of sequentially forming an oxidation-resistant insulating film and a polycrystalline silicon film on a semiconductor substrate, forming a predetermined pattern on the polycrystalline silicon film, and removing all the polycrystalline silicon films. converting into an oxide film to form a first oxide film; etching the oxidation-resistant insulating film using the first oxide film as a mask;
A method for manufacturing a semiconductor device, the method comprising: removing an oxide film of the semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, comprising the step of oxidizing the semiconductor substrate using an oxidation-resistant insulating film pattern as a mask to form a second oxide film. 3. The method of manufacturing a semiconductor device according to claim 1, including the step of etching the semiconductor substrate using an oxidation-resistant insulating film pattern as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP386480A JPS56100443A (en) | 1980-01-16 | 1980-01-16 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP386480A JPS56100443A (en) | 1980-01-16 | 1980-01-16 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56100443A JPS56100443A (en) | 1981-08-12 |
| JPS6231492B2 true JPS6231492B2 (en) | 1987-07-08 |
Family
ID=11569056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP386480A Granted JPS56100443A (en) | 1980-01-16 | 1980-01-16 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56100443A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60117866A (en) * | 1983-11-29 | 1985-06-25 | Toshiba Corp | Picture information reader |
| JPS60128636A (en) * | 1983-12-16 | 1985-07-09 | Toshiba Corp | Manufacture of semiconductor device |
| JP2603238B2 (en) * | 1987-02-17 | 1997-04-23 | キヤノン株式会社 | Paper feeder |
| JP2632829B2 (en) * | 1987-02-17 | 1997-07-23 | キヤノン株式会社 | Paper feeder |
-
1980
- 1980-01-16 JP JP386480A patent/JPS56100443A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56100443A (en) | 1981-08-12 |
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