JPH01179431A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH01179431A
JPH01179431A JP103088A JP103088A JPH01179431A JP H01179431 A JPH01179431 A JP H01179431A JP 103088 A JP103088 A JP 103088A JP 103088 A JP103088 A JP 103088A JP H01179431 A JPH01179431 A JP H01179431A
Authority
JP
Japan
Prior art keywords
oxide film
mask material
forming
semiconductor substrate
element isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP103088A
Other languages
Japanese (ja)
Other versions
JPH0666385B2 (en
Inventor
Kuniyoshi Yoshikawa
吉川 邦良
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63001030A priority Critical patent/JPH0666385B2/en
Publication of JPH01179431A publication Critical patent/JPH01179431A/en
Publication of JPH0666385B2 publication Critical patent/JPH0666385B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE:To form an element isolating region in the dimension as designed thereby avoiding the disconnection of wiring etc., by a method wherein, after implanting oxygen ion, an element isolating oxide film is formed in a semiconductor substrate. CONSTITUTION:After forming a surface protective film 12 on the main surface of a semiconductor substrate 11, the first masking material 13 is formed on the protective film 12. The second masking material 14 is formed on the first masking material 13 and then both of the masking materials 13, 14 are selectively removed by anisotropical etching process. The substrate 11 is implanted with oxygen ion using the third masking material 16 as a mask only on the sidewall parts of the pattern comprising the masking materials 13, 14. The masking materials 14, 16 are removed and after converting the oxygen ion implanted region into an oxide film 18 by annealing process, the masking material 13 and the protective film 12 are removed. Through these procedures, an element isolating region in narrow width can be formed in the dimension as designed to avoid the disconnection of wiring etc.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は半導体装置の製造方法に関し、特に半導体基板
上に形成される半導体素子の分離技術に係わる。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a technique for separating semiconductor elements formed on a semiconductor substrate.

(従来の技術) 従来、素子分離技術としてはしocos法が広く知られ
ている。この方法は、第2図に示すように、半導体基板
21上に絶縁g122を介して耐酸化性膜、たとえばシ
リコン窒化膜23を形成してパターニングを行なった後
、上記シリコン窒化1123を選択酸化用マスク材とし
て選択酸化を行なうことにより素子分離用酸化膜24を
形成するものである。
(Prior Art) Conventionally, the ocos method is widely known as an element isolation technique. In this method, as shown in FIG. 2, an oxidation-resistant film, for example, a silicon nitride film 23, is formed on a semiconductor substrate 21 via an insulating layer 122 and patterned, and then the silicon nitride 1123 is selectively oxidized. The element isolation oxide film 24 is formed by performing selective oxidation as a mask material.

ところで、上記LOCO8法では、バーズビークと呼ば
れる素子分離用酸化膜24の横方向への成長現象によっ
て、選択酸化用マスク材(シリコン窒化M23)のパタ
ーン寸法と形成された素子分離用酸化膜24の寸法との
間に寸法誤差E(第2図においてE−E1+E2で表わ
す)を生じる。たとえば、絶縁M22の膜厚を1500
人、シリコン窒化膜23の膜厚を2500人、選択酸化
時の素子分離用酸化I!I24の厚さを8000人、出
来上がり素子分離用酸化膜24の厚さを5000〜60
00人とすると、上記寸法誤差Eは1.2〜1.6譚と
なる。従って、実用的な素子分離用酸化膜24の寸法は
2−程度となり、それ以下の狭い素子分離領域の形成に
は向かないという問題がある。また、上記しocos法
で形成された素子分離用酸化膜24は、その厚さの約半
分が半導体基板21の主表面より上方に凸型の段差をも
って形成されるため、上層に配線を通すと断切れしやす
くなり、特に、微細な素子分離領域を形成して高集積化
を図る場合にはこの問題が顕著となる。
By the way, in the above-mentioned LOCO8 method, due to the horizontal growth phenomenon of the element isolation oxide film 24 called bird's beak, the pattern dimension of the selective oxidation mask material (silicon nitride M23) and the dimension of the formed element isolation oxide film 24 are changed. A dimensional error E (represented by E-E1+E2 in FIG. 2) occurs between the two. For example, set the film thickness of insulation M22 to 1500
The film thickness of the silicon nitride film 23 is 2,500 people, and the oxidation I for element isolation during selective oxidation! The thickness of I24 is 8,000 mm, and the thickness of the completed element isolation oxide film 24 is 5,000 to 60 mm.
If there are 00 people, the above-mentioned dimensional error E will be 1.2 to 1.6 tan. Therefore, the practical dimension of the element isolation oxide film 24 is about 2-2, and there is a problem that it is not suitable for forming a narrower element isolation region. Furthermore, since about half of the thickness of the element isolation oxide film 24 formed by the above-mentioned OCOS method is formed with a convex step above the main surface of the semiconductor substrate 21, it is difficult to pass wiring through the upper layer. This problem becomes particularly noticeable when high integration is achieved by forming fine element isolation regions.

(発明が解決しようとする課題) 上述したように従来の半導体装置の製造方法では、素子
分離用酸化膜がバーズビークにより寸法誤差を生じ、狭
い素子分離領域を形成するのが困難であり、また半導体
基板の上方へ凸型の段差をもって形成される為に、微細
化すると配線の断切れ等が顕著となる欠点がある。
(Problems to be Solved by the Invention) As described above, in the conventional semiconductor device manufacturing method, the element isolation oxide film has dimensional errors due to bird's beaks, making it difficult to form a narrow element isolation region, and Since it is formed with a convex step above the substrate, it has the disadvantage that when it is miniaturized, disconnection of wiring becomes noticeable.

従って、本発明の目的は、設計どうりの寸法で形成でき
、しかも活性領域と段差のない平坦な素子分離用酸化膜
を形成できる半導体装置の製造方法を提供することであ
る。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can be formed with designed dimensions and that can form a flat element isolation oxide film with no step difference from the active region.

[発明の構成] (課題を解決するための手段と作用) すなわち、本発明においては、上記の発明の目的を達成
する為に、半導体基板の主表面上に表面保myを形成し
た後、上記表面保5t#!上に第1のマスク材を形成し
、上記第1のマスク材上に第2のマスク材を形成し、上
記第1、第2のマスク材を異方性エツチング法を用いて
選択的に除去する。その後、第1、第2のマスク材から
なるパターンの側壁部のみに第3のマスク材を形成し、
上記第1、第2、第3のマスク材をマスクにして半導体
基板に酸素をイオン注入する。そして、上記第2、第3
のマスク材を除去し、続いてアニールを行なって、上記
酸素のイオン注入領域を酸化膜に転換した後に、上記第
1のマスク材及び表面保護膜を除去することを特徴とし
ている。
[Structure of the Invention] (Means and Effects for Solving the Problems) That is, in the present invention, in order to achieve the above-mentioned object of the invention, after forming a surface adhesive on the main surface of a semiconductor substrate, the above-mentioned Surface protection 5t#! forming a first mask material on top, forming a second mask material on the first mask material, and selectively removing the first and second mask materials using an anisotropic etching method; do. After that, a third mask material is formed only on the side wall portion of the pattern made of the first and second mask materials,
Oxygen ions are implanted into the semiconductor substrate using the first, second, and third mask materials as masks. And the above second and third
The method is characterized in that the first mask material and the surface protection film are removed after the first mask material is removed, and then annealing is performed to convert the oxygen ion implantation region into an oxide film.

また、半導体基板に酸素をイオン注入した後、上記第1
、第2、及び第3のマスク材を除去し、続いてアニール
を行なって上記酸素のイオン注入領域を酸化膜に転換し
、表面保護膜を除去してもよい。
Further, after ion-implanting oxygen into the semiconductor substrate, the first
, the second and third mask materials may be removed, and then annealing may be performed to convert the oxygen ion implantation region into an oxide film and the surface protective film may be removed.

このような製造方法によれば、酸素をイオン注入した後
で、アニールを行なって、半導体基板中に素子分離用酸
化膜を形成しているので、寸法誤差や半導体基板の上方
へ凸型の段差を持つことはなく、幅の狭い素子分離領域
を設計通りの寸法で形成でき、配線の断切れ等の心配も
ない。また、第3のマスク材の幅(第1図(C)におい
てhで表わす)を制御することによってリソグラフィー
の限界以上に狭い素子分離用酸化膜を形成することがで
きる。
According to this manufacturing method, after oxygen ion implantation, annealing is performed to form an oxide film for element isolation in the semiconductor substrate. Therefore, a narrow element isolation region can be formed with the designed dimensions, and there is no need to worry about wiring breakage. Furthermore, by controlling the width of the third mask material (represented by h in FIG. 1C), it is possible to form an oxide film for element isolation that is narrower than the limit of lithography.

(実施例) 以下、本発明の一実施例について図面を参照して説明す
る。第1図(a)〜(e)は本発明の半導体装置の製造
方法について説明する為の製造工程を示している。まず
、(a)図に示すように、シリコン基板11の1表7面
上に熱酸化法により、膜厚1000人程度0シリコン酸
化膜(表面保護膜)12を形成する。続いて、前記シリ
コン酸化膜上に多結晶シリコン層(第1のマスク材)1
3を3000人程度1シリコン酸化11(第2のマスク
材)14を4000人程度1の膜厚で堆積形成する。次
に(b)図に示すように、PEP法を用いてレジストパ
ターン15を形成し、異方性エツチングにより上記多結
晶シリコン層13、及びシリコン酸化膜14を選択的に
除去づる。その後、(C)図に示すように、レジストパ
ターン15を除去し、全面にCVD法を用いてシリコン
酸化膜を7000人程度0膜厚で堆積形成してから、R
IE法によりエッチバックすると上記多結晶シリコン層
13、及びシリコン酸化膜14の側壁部に幅りが500
0人程度0シリコン酸化膜(第3のマスク材)16が残
存する。続いて、上記多結晶シリコン層13、シリコン
酸化膜14、及びシリコン酸化ll116をマスクにし
て、イオン注入法により酸素をドーズff11018c
m4程度イオン注入する。
(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(e) show manufacturing steps for explaining the method for manufacturing a semiconductor device of the present invention. First, as shown in FIG. 1A, a silicon oxide film (surface protection film) 12 having a thickness of about 1000 is formed on one and seven surfaces of a silicon substrate 11 by thermal oxidation. Subsequently, a polycrystalline silicon layer (first mask material) 1 is formed on the silicon oxide film.
A silicon oxide layer 11 (second mask material) 14 is deposited to a thickness of about 4000 layers. Next, as shown in FIG. 3B, a resist pattern 15 is formed using the PEP method, and the polycrystalline silicon layer 13 and silicon oxide film 14 are selectively removed by anisotropic etching. Thereafter, as shown in FIG.
When etched back by the IE method, the side walls of the polycrystalline silicon layer 13 and silicon oxide film 14 have a width of 500 mm.
Approximately 0 silicon oxide films (third mask material) 16 remain. Next, using the polycrystalline silicon layer 13, silicon oxide film 14, and silicon oxide 116 as masks, oxygen is dosed by ion implantation ff11018c.
Ion implantation is performed to approximately m4.

次に、(d)図に示すように、シリコン酸化膜14、及
びシリコン酸化11i16を除去し、1100℃、N2
ガス中で7ニールして、半導体基板11中の酸素イオン
注入ffi域17を素子分離用酸化膜18に転換する。
Next, as shown in the figure (d), the silicon oxide film 14 and the silicon oxide film 11i16 are removed, and
The oxygen ion-implanted ffi region 17 in the semiconductor substrate 11 is converted into an element isolation oxide film 18 by annealing in a gas atmosphere for 7 hours.

最後に(e)図に示すように、多結晶シリコン層13、
及びシリコン酸化膜12を除去して素子分離領域を完成
する。
Finally, as shown in the figure (e), a polycrystalline silicon layer 13,
Then, the silicon oxide film 12 is removed to complete the element isolation region.

このような製造方法によれば、酸素イオンを半導体基板
中へ注入して、アニールを行なうことにより素子分離用
酸化膜を形成しているので、活性領域との段差がなく、
しかも設計どうりの素子分離領域を得ることができる。
According to this manufacturing method, an oxide film for element isolation is formed by injecting oxygen ions into the semiconductor substrate and performing annealing, so there is no step difference with the active region.
Furthermore, it is possible to obtain a device isolation region as designed.

たとえば、アニール工程で素子分離領域が拡大しないと
仮定すると、素子分離用酸化膜の寸法は、原理的に「半
導体基板へのイオン注入幅+イオン注入時の横方向分散
幅J 2500人程度0実現できる。ここで、半導体基
板へのイオン注入幅は、PEP幅(第1図(b)におい
でAで表わす)と側壁部のシリコン酸化膜の幅(h)よ
りrA−hX2Jで設定される。よって、リソグラフィ
ーの限界以上に小さい素子分離用酸化膜の形成も可能で
ある。
For example, assuming that the element isolation region does not expand during the annealing process, the dimensions of the element isolation oxide film are, in principle, "Ion implantation width into the semiconductor substrate + Lateral dispersion width J during ion implantation". Here, the width of ion implantation into the semiconductor substrate is set as rA-hX2J from the PEP width (represented by A in FIG. 1(b)) and the width (h) of the silicon oxide film on the side wall. Therefore, it is also possible to form an oxide film for element isolation that is smaller than the limit of lithography.

なお、(d)図において、除去するマスク材をシリコン
酸化膜14、及びシリコン酸化I!!1Gとしたが、こ
れに加えて多結晶シリコン層14も除去して、アニール
を行なった後にシリコン酸化膜12のみを除去してもよ
い。また、上記実施例において第3のマスク材としてシ
リコン酸化膜を用いたが、これに限らずシリコン窒化膜
でもよい。また、第1のマスク材として多結晶シリコン
層を用いたがシリコン窒化膜でもよい。
In the figure (d), the mask material to be removed is the silicon oxide film 14 and the silicon oxide film I! ! 1G, but in addition, the polycrystalline silicon layer 14 may also be removed, and only the silicon oxide film 12 may be removed after annealing. Further, although a silicon oxide film is used as the third mask material in the above embodiment, the third mask material is not limited thereto, and a silicon nitride film may also be used. Furthermore, although a polycrystalline silicon layer is used as the first mask material, a silicon nitride film may also be used.

[発明の効果] 以上説明したように、本発明によれば、設計どうりの寸
法で形成でき、しかも活性領域と段差のない平坦な素子
分離用酸化膜を形成できる半導体装置の製造方法を提供
できる。
[Effects of the Invention] As described above, the present invention provides a method for manufacturing a semiconductor device that can be formed with designed dimensions and that can form a flat element isolation oxide film with no step difference from the active region. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例に係わる半導体装置の製造方
法について説明するための断面図、第2図は従来の半導
体装置の製造方法について説明するための断面図である
。 11・・・シリコン基板、12・・・シリコン酸化膜(
表面保護膜)、13・・・多結晶シリコン層(第1のマ
スク材)、14・・・シリコン酸化膜(第2のマスク材
)、15・・・レジストパターン、16・・・シリコン
酸化膜(第3のマスク材)、17・・・イオン注入領域
、18・・・素子分離用酸化膜。 出願人代理人 弁理士 鈴江武彦 第1図
FIG. 1 is a cross-sectional view for explaining a method of manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining a conventional method of manufacturing a semiconductor device. 11...Silicon substrate, 12...Silicon oxide film (
surface protective film), 13... polycrystalline silicon layer (first mask material), 14... silicon oxide film (second mask material), 15... resist pattern, 16... silicon oxide film (Third mask material), 17... Ion implantation region, 18... Oxide film for element isolation. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板の主表面上に表面保護膜を形成する第
1の工程と、上記表面保護膜上に第1のマスク材を形成
する第2の工程と、上記第1のマスク材上に第2のマス
ク材を形成する第3の工程と、上記第1、第2のマスク
材を異方性エッチング法を用いて選択的に除去する第4
の工程と、この第4の工程で形成したパターンの側壁部
のみに第3のマスク材を形成する第5の工程と、上記第
1、第2、第3のマスク材をマスクにして半導体基板に
酸素をイオン注入する第6の工程と、上記第2、第3の
マスク材を除去する第7の工程と、アニールを行なつて
、上記酸素のイオン注入領域を酸化膜に転換する第8の
工程と、上記第1のマスク材及び表面保護膜を除去する
第9の工程とを具備することを特徴とする半導体装置の
製造方法。
(1) A first step of forming a surface protective film on the main surface of a semiconductor substrate, a second step of forming a first mask material on the surface protective film, and a second step of forming a first mask material on the first mask material. a third step of forming a second mask material; and a fourth step of selectively removing the first and second mask materials using an anisotropic etching method.
a fifth step of forming a third mask material only on the sidewalls of the pattern formed in the fourth step; and a step of forming a semiconductor substrate using the first, second, and third mask materials as masks. a sixth step of ion-implanting oxygen into the area; a seventh step of removing the second and third mask materials; and an eighth step of converting the oxygen ion-implanted region into an oxide film by annealing. and a ninth step of removing the first mask material and the surface protective film.
(2)前記第7の工程で、さらに第1のマスク材を除去
し、前記第9の工程で表面保護膜を除去することを特徴
とする請求項1記載の半導体装置の製造方法。
2. The method of manufacturing a semiconductor device according to claim 1, wherein the first mask material is further removed in the seventh step, and the surface protection film is removed in the ninth step.
JP63001030A 1988-01-06 1988-01-06 Method for manufacturing semiconductor device Expired - Fee Related JPH0666385B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63001030A JPH0666385B2 (en) 1988-01-06 1988-01-06 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63001030A JPH0666385B2 (en) 1988-01-06 1988-01-06 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH01179431A true JPH01179431A (en) 1989-07-17
JPH0666385B2 JPH0666385B2 (en) 1994-08-24

Family

ID=11490168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63001030A Expired - Fee Related JPH0666385B2 (en) 1988-01-06 1988-01-06 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JPH0666385B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4212503A1 (en) * 1991-04-15 1992-10-22 Gold Star Electronics SEMICONDUCTOR MODULE AND METHOD FOR THE PRODUCTION THEREOF
US5441899A (en) * 1992-02-18 1995-08-15 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing substrate having semiconductor on insulator
KR100248818B1 (en) * 1992-12-30 2000-03-15 김영환 Semiconductor element isolating method
KR100447326B1 (en) * 1996-12-28 2004-11-03 주식회사 하이닉스반도체 Method for forming isolation layer of semiconductor device using n2o annealing

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60147132A (en) * 1984-01-12 1985-08-03 Nec Corp Manufacture of semiconductor device
JPS60210849A (en) * 1984-04-03 1985-10-23 Mitsubishi Electric Corp Formation of insulation film buried into semiconductor substrate
JPS61191046A (en) * 1985-02-20 1986-08-25 Sanyo Electric Co Ltd Method of isolating mos semiconductor integrated circuit
JPS61271866A (en) * 1985-05-27 1986-12-02 Toshiba Corp Manufacture of cmos semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60147132A (en) * 1984-01-12 1985-08-03 Nec Corp Manufacture of semiconductor device
JPS60210849A (en) * 1984-04-03 1985-10-23 Mitsubishi Electric Corp Formation of insulation film buried into semiconductor substrate
JPS61191046A (en) * 1985-02-20 1986-08-25 Sanyo Electric Co Ltd Method of isolating mos semiconductor integrated circuit
JPS61271866A (en) * 1985-05-27 1986-12-02 Toshiba Corp Manufacture of cmos semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4212503A1 (en) * 1991-04-15 1992-10-22 Gold Star Electronics SEMICONDUCTOR MODULE AND METHOD FOR THE PRODUCTION THEREOF
US5441899A (en) * 1992-02-18 1995-08-15 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing substrate having semiconductor on insulator
US5616507A (en) * 1992-02-18 1997-04-01 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing substrate having semiconductor on insulator
KR100248818B1 (en) * 1992-12-30 2000-03-15 김영환 Semiconductor element isolating method
KR100447326B1 (en) * 1996-12-28 2004-11-03 주식회사 하이닉스반도체 Method for forming isolation layer of semiconductor device using n2o annealing

Also Published As

Publication number Publication date
JPH0666385B2 (en) 1994-08-24

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