JPS60210849A - Formation of insulation film buried into semiconductor substrate - Google Patents
Formation of insulation film buried into semiconductor substrateInfo
- Publication number
- JPS60210849A JPS60210849A JP6792184A JP6792184A JPS60210849A JP S60210849 A JPS60210849 A JP S60210849A JP 6792184 A JP6792184 A JP 6792184A JP 6792184 A JP6792184 A JP 6792184A JP S60210849 A JPS60210849 A JP S60210849A
- Authority
- JP
- Japan
- Prior art keywords
- ions
- semiconductor substrate
- oxide film
- implanted
- buried
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は半導体基板に、選択的に埋込み絶縁膜を形成
する方法の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a method for selectively forming a buried insulating film in a semiconductor substrate.
第１図Ａ−Ｆは従来の方法の主要段階における状態を示
す断面図である。まず、第１図人に示すように、シリコ
ン基板（１）に熱酸化膜（２）を形成し、その上に減圧
ＯＶＤ法で窒化膜（３）を形成し、更にその土にレジス
ト膜（４）を塗布し、埋込み絶縁膜を作シたい場所のレ
ジスト膜（４）、窒化膜（３）、および熱酸化膜（２）
を順次除去し、開口部（５）を形成する。次に第１図Ｂ
Ｋ示すように１開口部（５）に露出したシリコン基板（
１）にスパッタエツチングを施して、凹部（６）を形成
する。次に第１図Ｃに示すように、レジスト膜（４）、
窒化膜（３）、熱酸化膜（２）を除去した後に、第１図
りに示すように、減圧ＣＶＤ法で、凹部（６）内を含め
てシリコン基板（１）上に酸化膜（７）を形成する０つ
づいて、第１１ＮＥに示す−ように全上面にレジスト層
（８）を塗布形成し酸化膜（７）表面の凹みを埋める。1A-1F are cross-sectional views showing the main stages of the conventional method. First, as shown in Figure 1, a thermal oxide film (2) is formed on a silicon substrate (1), a nitride film (3) is formed on it by low pressure OVD, and a resist film ( 4) and place the resist film (4), nitride film (3), and thermal oxide film (2) where you want to create the buried insulating film.
are sequentially removed to form an opening (5). Next, Figure 1B
As shown in K, the silicon substrate (
1) is subjected to sputter etching to form a recess (6). Next, as shown in FIG. 1C, a resist film (4),
After removing the nitride film (3) and the thermal oxide film (2), as shown in the first diagram, an oxide film (7) is formed on the silicon substrate (1) including the inside of the recess (6) by low pressure CVD. Next, as shown in the 11th NE, a resist layer (8) is coated on the entire upper surface to fill in the depressions on the surface of the oxide film (7).
続いて、第１図Ｆに示すように、レジスト層（８）と酸
化膜（７）とのエツチングレートが等しいような条件で
エツチングを施して所望の埋込み酸化膜（７ａ）を得る
。Subsequently, as shown in FIG. 1F, etching is performed under conditions such that the etching rates of the resist layer (8) and the oxide film (7) are equal to obtain a desired buried oxide film (7a).
しかし、上述の従来の方法は、工程数が非常に多い０ま
た、第１図Ｅに示すレジスト層（８）と酸化膜（７）と
のエツチングレートが等しくなる条件を見い出さなけれ
ばならず、さらに１工ツチング時間の大小により、埋込
み酸化膜（マａ）の厚さが減少したり、凹部（６）以外
の領域に酸化膜（７）が残るので、エツチング時間を正
確に決定する必要があるなどの欠点があった。However, the conventional method described above requires a very large number of steps. In addition, it is necessary to find a condition in which the etching rates of the resist layer (8) and the oxide film (7) shown in FIG. 1E are equal. Furthermore, depending on the size of the etching time, the thickness of the buried oxide film (ma) may decrease or the oxide film (7) may remain in areas other than the recesses (6), so it is necessary to accurately determine the etching time. There were some drawbacks.
この発明は以上のような点に鑑みてなされたもので、半
導体基板に酸素または窒素のイオンを選択的に注入する
ことによって容易に埋込み絶縁膜を形成する方法を提供
するものである。The present invention has been made in view of the above points, and provides a method for easily forming a buried insulating film by selectively implanting oxygen or nitrogen ions into a semiconductor substrate.
第２図Ａ−Ｃｉはこの発明の一実施例を説明するだめの
図である。第２図Ａはシリコン基板（１）の平面図で、
破線で囲んだ領域（９）が埋込み酸化膜を形成すべき領
域である。第２図Ｂ、Ｏはこの発明の一実施例の各段階
での状態を示す断面図で、イオン注入装置（図示せず）
の偏向電圧を制御することによって、マスクを用いるこ
となく、上記領域に第２図ＢＫ矢印Ｉで示すように酸素
イオンを注入し、酸素イオン注入領域ｍを形成する。つ
づいて、これを熱処理して第２図Ｏに示すように埋込み
酸化膜（ロ）を形成する。FIG. 2A-Ci is a diagram for explaining one embodiment of the present invention. Figure 2A is a plan view of the silicon substrate (1).
A region (9) surrounded by a broken line is a region where a buried oxide film is to be formed. FIGS. 2B and 2O are cross-sectional views showing the state at each stage of an embodiment of the present invention, in which an ion implanter (not shown) is shown.
By controlling the deflection voltage of , oxygen ions are implanted into the above region as shown by arrow I in FIG. 2B without using a mask, thereby forming an oxygen ion implantation region m. Subsequently, this is heat treated to form a buried oxide film (b) as shown in FIG.
上記実施例は選択的にイオン注入可能な装置を用いたが
、選択的如イオン注入できない装置でも、この発明は実
施可能で、第３図Ａ−Ｄはこのようなこの発明の他の実
施例の各工程段階での断面図で、まず、第３図Ａに示す
ように、シリコン基板（１）の上に、従来方法と同様に
熱酸化膜（２）、窒化膜（３）およびレジスト膜（４）
を順次形成し、埋込み酸化膜を形成すべき領域のレジス
ト膜（４）および窒化膜（３）を除去して開口部（５ａ
）を形成する。次に、第３図Ｂに矢印Ｉで示すように、
全上面に酸素イオンを注入し、レジスト膜（４）および
窒化膜（３）をマスクとして、開口部（５ａ）からシリ
コン基板（１）内に酸素イオンを注入し、イオン注入領
域Ｑｌを形成する０つづいて、第３図Ｃに示すように、
レズスト膜（４）、窒化膜（３）および熱酸化膜（２）
を除去し、更に、このシリコン基板（」）を熱処理して
、第３図りに示すように埋込み酸化膜θηを形成する。Although the above embodiment used an apparatus capable of selectively implanting ions, the present invention can be practiced even with an apparatus that cannot selectively implant ions, and FIGS. 3A to 3D show other embodiments of the present invention. First, as shown in FIG. 3A, a thermal oxide film (2), a nitride film (3) and a resist film are deposited on a silicon substrate (1) in the same way as in the conventional method. (4)
are sequentially formed, and the resist film (4) and nitride film (3) in the area where the buried oxide film is to be formed are removed to form the opening (5a).
) to form. Next, as shown by arrow I in Figure 3B,
Oxygen ions are implanted into the entire top surface, and using the resist film (4) and nitride film (3) as masks, oxygen ions are implanted into the silicon substrate (1) from the opening (5a) to form an ion implantation region Ql. 0Continuing, as shown in Figure 3C,
Resist film (4), nitride film (3) and thermal oxide film (2)
This silicon substrate ('') is further heat-treated to form a buried oxide film θη as shown in the third diagram.
以上実施例では酸素イオンを注入して埋込み酸化膜を形
成する場合を示したが、窒素イオンを注入して埋込み窒
化膜を形成することも同様に可能である。In the above embodiments, the case where a buried oxide film is formed by implanting oxygen ions has been shown, but it is also possible to form a buried nitride film by implanting nitrogen ions.
以上説明したように、この発明の方法では、半導体基板
に選択的に酸素イオンまたは窒素イオンを注入して熱処
理を施すことによって、埋込み絶縁膜を形成するようＫ
したので、従来方法に比して工程数が減少し、埋込み絶
縁膜形成領域の精密制御が可能であり、更に、注入イオ
ンの加速電圧の制御によって埋込み絶縁膜の深さを容易
に制御できる。As explained above, in the method of the present invention, a buried insulating film is formed by selectively implanting oxygen ions or nitrogen ions into a semiconductor substrate and performing heat treatment.
Therefore, compared to the conventional method, the number of steps is reduced, the region where the buried insulating film is to be formed can be precisely controlled, and furthermore, the depth of the buried insulating film can be easily controlled by controlling the acceleration voltage of implanted ions.
第１図Ａ −Ｆｌ’は従来の埋込み絶縁膜形成方法の主
要段階での状態を示す断面図、第２図Ａ［埋込み絶縁膜
を形成すべきシリコン基板の平面図、第２図ＢおよびＣ
はこの発明の一実施例の各工程段階での状態を示す断面
図、第３図Ａ−Ｄはこの発明の他の実施例の主要工程段
階での状態を示す断面図である。
図において、（１）は半導体（シリコン）基板、（３）
および（４）はそれぞれマスクを構成する窒化膜および
レジスト膜、（ｌＩは（酸素）イオン注入領域、（ロ）
は埋込み絶縁（酸化膜）、工は注入イオンである０なお
、同中同−符号は同一または相当部分を示す。
代理人 大岩増雄
手続補正書（自発）
２０発明の名称
半導体基板への埋込み絶縁膜の形式方法３、補正をする
者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号名 称
（６０１）三菱電機株式会社
代表者片山仁八部
４、ｆ（埋入
６、 補正の対象
明細書の発明の詳細な説明の欄および図面の簡単な説明
の欄
６、 補正の内容
明細書をつぎのとおり訂正する。Figure 1A-Fl' is a sectional view showing the main stages of a conventional method for forming a buried insulating film, Figure 2A is a plan view of a silicon substrate on which a buried insulating film is to be formed, Figures 2B and C
FIGS. 3A and 3B are cross-sectional views showing the state of one embodiment of the present invention at each process step, and FIGS. 3A-3D are cross-sectional views showing the state of another embodiment of the present invention at main process steps. In the figure, (1) is a semiconductor (silicon) substrate, (3)
and (4) are the nitride film and resist film constituting the mask, (lI is the (oxygen) ion implantation region, and (b)
1 is a buried insulator (oxide film), and 1 is an implanted ion. Note that the same or similar symbols in the middle indicate the same or equivalent parts. Agent: Masuo Oiwa Procedural amendment (spontaneous) 20 Title of the invention Format of insulating film embedded in a semiconductor substrate Method 3, Relationship with the case of the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name
(601) Mitsubishi Electric Corporation Representative Hitoshi Katayama Section 4, f (embedding 6, column 6 for detailed explanation of the invention and brief explanation of drawings in the specification subject to amendment, and statement of contents of the amendment) The following corrections are made.
Claims (1)
オンを注入した後、当該半導体基板を熱処理して上記所
望領域に半導体酸化膜または半導体窒化膜からなる埋込
み絶縁膜を形成することを特徴とする半導体基板への埋
込み絶縁膜の形成方法。 （２）注入イオンビームを偏向制御して所望領域にイオ
ン注入することを特徴とする特許請求の範囲第１項記載
の半導体基板への埋込み絶縁膜の形成方法。 （３） マスクを用いて所望領域にイオン注入すること
を特徴とする特許請求の範囲第１項記載の半導体基板へ
の埋込み絶縁膜の形成方法。[Claims] (11) After implanting oxygen or nitrogen ions into a desired region of the main surface of a semiconductor substrate, the semiconductor substrate is heat-treated to form a buried insulating film made of a semiconductor oxide film or a semiconductor nitride film in the desired region. A method for forming a buried insulating film in a semiconductor substrate, comprising: (2) controlling the deflection of an implanted ion beam to implant ions into a desired region; Method for forming a buried insulating film in a semiconductor substrate (3) A method for forming a buried insulating film in a semiconductor substrate according to claim 1, wherein ions are implanted into a desired region using a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6792184A JPS60210849A (en) | 1984-04-03 | 1984-04-03 | Formation of insulation film buried into semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6792184A JPS60210849A (en) | 1984-04-03 | 1984-04-03 | Formation of insulation film buried into semiconductor substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60210849A true JPS60210849A (en) | 1985-10-23 |
Family
ID=13358855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6792184A Pending JPS60210849A (en) | 1984-04-03 | 1984-04-03 | Formation of insulation film buried into semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60210849A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01179431A (en) * | 1988-01-06 | 1989-07-17 | Toshiba Corp | Manufacture of semiconductor device |
-
1984
- 1984-04-03 JP JP6792184A patent/JPS60210849A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01179431A (en) * | 1988-01-06 | 1989-07-17 | Toshiba Corp | Manufacture of semiconductor device |
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