JPS63205944A - Manufacture of mos integrated circuit - Google Patents
Manufacture of mos integrated circuitInfo
- Publication number
- JPS63205944A JPS63205944A JP62039452A JP3945287A JPS63205944A JP S63205944 A JPS63205944 A JP S63205944A JP 62039452 A JP62039452 A JP 62039452A JP 3945287 A JP3945287 A JP 3945287A JP S63205944 A JPS63205944 A JP S63205944A
- Authority
- JP
- Japan
- Prior art keywords
- region
- oxide film
- gate oxide
- mos transistor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 230000003647 oxidation Effects 0.000 claims abstract description 22
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 17
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- -1 nitrogen ion Chemical class 0.000 claims abstract description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 14
- 229910052710 silicon Inorganic materials 0.000 abstract description 14
- 239000010703 silicon Substances 0.000 abstract description 14
- 239000012535 impurity Substances 0.000 abstract description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 5
- 241001012508 Carpiodes cyprinus Species 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002829 nitrogen Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明はゲートにかかる動作電圧（以後動作電圧と記す
）の異なる２種類以上のＭＯＳ）ランジスタを同一半導
体基板に形成するＭＯＳ集積回路の製造方法に関するも
のである。Detailed Description of the Invention Field of the Invention The present invention relates to a method for manufacturing a MOS integrated circuit in which two or more types of MOS transistors having different operating voltages applied to their gates (hereinafter referred to as operating voltages) are formed on the same semiconductor substrate. It is something.
従来の技術
同一半導体基板上に動作電圧が互いに異なるＭＯＳトラ
ンジスタを形成するＭＯＳ集積回路において、高電圧動
作回路部のトランジスタと低電圧動作回路部のトランジ
スタにそれぞれ最適な厚さのゲート酸化膜を二度の酸化
処理工程により形成している。この従来の工程を第３図
の断面図を参照して説明する。2. Description of the Related Art In a MOS integrated circuit in which MOS transistors with different operating voltages are formed on the same semiconductor substrate, two gate oxide films with optimal thicknesses are formed for the transistors in the high-voltage operating circuit section and the transistors in the low-voltage operating circuit section. It is formed through a multiple oxidation treatment process. This conventional process will be explained with reference to the sectional view of FIG.
まず、シリコン半導体基板１の表面に選択的に素子分離
用のフィールド酸化膜２を形成する。なお、図において
低電圧動作回路部のＭＯＳトランジスタの形成領域をＡ
領域、高電圧動作回路部のＭＯＳトランジスタの形成領
域をＢ領域で示す６次に、シリコン半導体基板１の表面
に第１回目のゲート酸化膜３を形成した後、Ｂ領域をフ
ォトレジスト膜４でマスクし、Ａ領域のゲート酸化膜を
通常のエツチング方法で除去する（第３図ａ）。First, a field oxide film 2 for element isolation is selectively formed on the surface of a silicon semiconductor substrate 1. In the figure, the formation area of the MOS transistor in the low voltage operation circuit section is indicated by A.
6. Next, after forming the first gate oxide film 3 on the surface of the silicon semiconductor substrate 1, the B region is covered with a photoresist film 4. Using a mask, the gate oxide film in area A is removed by a normal etching method (FIG. 3a).
さらにフォトレジスト膜４を取除いた後に第２回目の熱
酸化工程を行い、Ａ領域に新たなゲート酸化膜５を形成
する。この時、Ｂ領域のゲート酸化膜３は、すでに第１
回目の酸化で形成したゲート酸化膜に２回目の酸化でさ
らに、酸化膜を増加した膜厚となる。次に、ゲート酸化
膜３と５の上に多結晶シリコン膜６を形成した後、これ
らを選択的に除去し、不純物をシリコン半導体基板１中
に拡散して、Ａ領域とＢ領域にそれぞれソース領域７と
ドレイン領域８を形成する（第３図ｂ）。以上の工程に
よりＡ領域にはゲート酸化膜の薄いトランジスタがＢ領
域にはゲート酸化膜の厚いトランジスタが形成される。Further, after removing the photoresist film 4, a second thermal oxidation step is performed to form a new gate oxide film 5 in the A region. At this time, the gate oxide film 3 in the B region has already been exposed to the first layer.
The thickness of the gate oxide film formed in the second oxidation is increased by the second oxidation. Next, after forming a polycrystalline silicon film 6 on the gate oxide films 3 and 5, these are selectively removed, and impurities are diffused into the silicon semiconductor substrate 1 to form sources in the A region and B region, respectively. A region 7 and a drain region 8 are formed (FIG. 3b). Through the above steps, a transistor with a thin gate oxide film is formed in the A region, and a transistor with a thick gate oxide film is formed in the B region.
発明が解決しようとする問題点
従来の製造方法では、酸化工程を二度行わなければなら
ないため、工程数が増加するばかりでな（第２回目の酸
化直前の酸洗浄処理等で第１回目に形成されたゲート酸
化膜の膜厚が目減りするため、最終的に得るゲート酸化
膜の膜厚の制御が困難となる。さらにＡ領域のゲート酸
化膜の形成において、二度の酸化工程で二度シリコン半
導体基板表面を露出して行うため、シリコン基板表面近
くの不純物が表面から放出される等により、不純物が大
きく再分布してＭＯＳトランジスタのしきい値電圧のば
らつきが太き（なる欠点がある。Problems to be Solved by the Invention In the conventional manufacturing method, the oxidation step has to be carried out twice, which not only increases the number of steps (the acid cleaning treatment immediately before the second oxidation removes the oxidation from the first step). As the thickness of the formed gate oxide film decreases, it becomes difficult to control the thickness of the final gate oxide film.Furthermore, in forming the gate oxide film in region A, two oxidation steps are performed twice. Since the surface of the silicon semiconductor substrate is exposed, impurities near the surface of the silicon substrate are emitted from the surface, resulting in large redistribution of impurities and wide variations in the threshold voltage of MOS transistors. .
本発明は、１回のゲート酸化工程でゲート酸化膜の膜厚
の異なるＭＯＳトランジスタを２種類以上形成する製造
方法を提案することを目的とするものである。An object of the present invention is to propose a manufacturing method for forming two or more types of MOS transistors having different gate oxide film thicknesses in one gate oxidation step.
問題点を解決するための手段
本発明は、半導体基板上の低電圧で動作するＭＯＳトラ
ンジスタの形成領域に窒素イオンを加速注入した後、前
記低電圧より高い高電圧で動作するＭＯＳトランジスタ
の形成領域と前記低電圧で動作するＭＯＳ トランジス
タの形成領域に同時に熱酸化処理を施こし、膜厚の異な
るゲート酸化膜を同時に形成するＭＯＳ集積回路の製造
方法である。Means for Solving the Problems The present invention provides accelerated implantation of nitrogen ions into a formation region of a MOS transistor that operates at a low voltage on a semiconductor substrate, and then implants the formation region of a MOS transistor that operates at a high voltage higher than the low voltage. This is a method of manufacturing a MOS integrated circuit, in which a thermal oxidation process is simultaneously performed on the formation regions of the MOS transistors operating at low voltage, and gate oxide films having different thicknesses are simultaneously formed.
作用
本発明のＭＯＳ集積回路の製造方法によれば、低電圧動
作回路部におけるＭＯＳ）ランジスタのゲート酸化膜を
形成すべき領域に、窒素イオンをイオン注入装置を用い
て注入し、注入した窒素イオンの量により熱酸化処理時
の酸化速度を減速制御することにより、低電圧動作のＭ
ＯＳトランジスタの薄いゲート酸化膜と窒素イオンを注
入していない高電圧動作回路部におけるＭＯＳトランジ
スタの厚いゲート酸化膜を同時に唯一回の酸化で形成す
ることができる。According to the method for manufacturing a MOS integrated circuit of the present invention, nitrogen ions are implanted using an ion implantation device into the region where the gate oxide film of the MOS transistor in the low voltage operation circuit section is to be formed. By controlling the oxidation rate during thermal oxidation treatment by controlling the amount of
A thin gate oxide film of an OS transistor and a thick gate oxide film of a MOS transistor in a high-voltage operation circuit portion in which nitrogen ions are not implanted can be simultaneously formed in a single oxidation process.
実施例
本発明のＭＯ３集積回路の製造方法の実施例を第１図の
断面図を参照して説明する。Embodiment An embodiment of the method for manufacturing an MO3 integrated circuit according to the present invention will be described with reference to the sectional view of FIG.
まず、シリコン半導体基板１の表面に選択的に素子分離
用のフィールド酸化膜２を形成する。なお、低電圧動作
回路部のＭＯＳトランジスタ形成領域をＡ領域、高電圧
動作回路部のＭＯＳ）ランジスタ形成領域をＢ領域で表
わす。フィールド酸化膜２を形成した後、Ｂ領域のシリ
コン半導体基板１の表面を通常の写真食刻法でフォトレ
ジスト膜４でマスクし、Ａ領域のシリコン半導体基板１
の表面に目的とする酸化膜厚に応じた窒素イオンをイオ
ン注入装置を用いて注入して窒素イオン注入層９を形成
する（第１図ａ）。第２図に窒素イオンのドーズ量と熱
酸化による酸化シリコンの膜厚の関係を示す。このよう
に窒素イオンのドーズ量により酸化シリコンの膜厚を制
御することができる。この窒素イオン注入層９を形成し
た後、Ｂ領域に形成されたフォトレジスト膜４を除去し
、この後熱酸化処理を行いＡ領域に膜厚の薄いゲート酸
化膜１０を、Ｂ領域に膜厚の厚いゲート酸化膜１１を形
成する。この後の製造工程は通常の方法でゲート酸化膜
１０と１１の上にゲート電極となる多結晶シリコン膜６
を形成した後、ゲート酸化膜と多結晶シリコン膜６を選
択的に除去し、シリコン半導体基板１の導電性と逆の導
電性の不純物をシリコン半導体基板１中に拡散して、Ａ
領域とＢ領域にそれぞれソース領域７とドレイン領域８
を形成する（第１図ｂ）。以上の工程により異なるゲー
ト酸化膜厚を有するＭＯＳトランジスタがＡ領域とＢ領
域に形成される。First, a field oxide film 2 for element isolation is selectively formed on the surface of a silicon semiconductor substrate 1. Note that the MOS transistor forming region of the low voltage operating circuit section is indicated by region A, and the MOS transistor forming region of the high voltage operating circuit section is indicated by region B. After forming the field oxide film 2, the surface of the silicon semiconductor substrate 1 in the region B is masked with a photoresist film 4 by a normal photolithography method, and the surface of the silicon semiconductor substrate 1 in the region A is masked with a photoresist film 4.
A nitrogen ion implantation layer 9 is formed by implanting nitrogen ions into the surface of the substrate using an ion implantation device according to the desired oxide film thickness (FIG. 1a). FIG. 2 shows the relationship between the dose of nitrogen ions and the thickness of silicon oxide formed by thermal oxidation. In this way, the thickness of the silicon oxide film can be controlled by controlling the dose of nitrogen ions. After forming this nitrogen ion implantation layer 9, the photoresist film 4 formed in the B region is removed, and then thermal oxidation treatment is performed to form a thin gate oxide film 10 in the A region and a thin gate oxide film 10 in the B region. A thick gate oxide film 11 is formed. In the subsequent manufacturing process, a polycrystalline silicon film 6 that will become the gate electrode is placed on the gate oxide films 10 and 11 using the usual method.
After forming A, the gate oxide film and the polycrystalline silicon film 6 are selectively removed, and an impurity having a conductivity opposite to that of the silicon semiconductor substrate 1 is diffused into the silicon semiconductor substrate 1.
A source region 7 and a drain region 8 are provided in the region and B region, respectively.
(Fig. 1b). Through the above steps, MOS transistors having different gate oxide film thicknesses are formed in the A region and the B region.
次に、数字で示した具体例を示す。Ａ領域に形成するＭ
ＯＳトランジスタのゲート酸化膜を４０ｎｍ、Ｂ領域に
形成するＭＯＳトランジスタのゲート酸化膜を８０ｎｍ
形成する場合、Ａ領域に５０Ｋｅｙの加速エネルギーで
２Ｘ１０ｃ＋＋＋ のドーズ量の窒素イオンを注入し
た後、９００℃の温度で水素と酸素を１：２の割合で燃
焼させたｒクエット酸化雰囲気中で１時間熱酸化する事
により目的とする２種の異なる膜厚のゲート酸化膜を同
時に形成することができる。Next, a specific example shown in numbers will be shown. M formed in area A
The gate oxide film of the OS transistor is 40 nm, and the gate oxide film of the MOS transistor formed in the B region is 80 nm.
In the case of formation, nitrogen ions are implanted into region A at a dose of 2X10c+++ with an acceleration energy of 50 keys, and then at a temperature of 900°C, hydrogen and oxygen are burned at a ratio of 1:2 in an r Couette oxidation atmosphere for 1 hour. By thermal oxidation, it is possible to simultaneously form two desired gate oxide films with different thicknesses.
本発明の製造方法を採用することにより、例えば、ＭＯ
Ｓ集積回路の内部回路では動作電圧が５Ｖ（ボルト）で
周辺回路では動作電圧が２０ＶのＭＯＳトランジスタの
設計及び製造が容易になる。以上動作電圧の異なるＭＯ
Ｓトランジスタを同一基板上に２種類以上を同時に形成
するときには、有効である。By adopting the manufacturing method of the present invention, for example, MO
It becomes easy to design and manufacture a MOS transistor whose operating voltage is 5 V (volts) in the internal circuit of the S integrated circuit and 20 V in the peripheral circuit. MOs with different operating voltages
This is effective when two or more types of S transistors are simultaneously formed on the same substrate.
発明の効果
本発明のＭＯＳ集積回路の製造方法によれば目的とする
ゲート酸化膜の膜厚に応じて窒素イオンの所定量をゲー
ト酸化膜形成前にシリコン基板中に選択的にイオン注入
しておくことにより、１回の酸化工程で２種以上の異な
るゲート酸化膜を目的とする場所に形成することができ
る。このため、従来の方法の２回の酸化工程と比べて、
工程時間が短かくなり工程費用が安（なるばかりでなく
、ゲート酸化膜の膜厚の制御が容易となる。さらにシリ
コン基板中の不純物の再分布によるしきい値電圧のばら
つきが小さくなる利点もある。Effects of the Invention According to the method for manufacturing a MOS integrated circuit of the present invention, a predetermined amount of nitrogen ions is selectively implanted into the silicon substrate before forming the gate oxide film, depending on the thickness of the intended gate oxide film. By depositing two or more different types of gate oxide films in one oxidation step, it is possible to form two or more different types of gate oxide films at desired locations. Therefore, compared to the two oxidation steps of the conventional method,
This not only shortens process time and lowers process costs, but also makes it easier to control the thickness of the gate oxide film.Furthermore, it has the advantage of reducing variations in threshold voltage due to redistribution of impurities in the silicon substrate. be.
第１図は本発明のＭＯＳ集積回路の製造方法を示す断面
図、第２図は熱酸化による窒素イオンのドーズ量と酸化
シリコンの膜厚の関係を示した図、第３図は従来のＭＯ
Ｓ集積回路の製造方法を示す断面図である。
１・・・・・・シリコン半導体基板、２・・・・・・フ
ィールド酸化膜、４・・・・・・フォトレジスト膜、６
・・・・・・多結晶シリコン膜、７・・・・・・ソース
領域、８・・・・・・ドレイン領域、９・・・・・・窒
素イオン注入層、１０・・・・・・低電圧動作ＭＯＳト
ランジスタのゲート酸化膜、１１・・・・・・高電圧動
作Ｍ ＯＳ ）’ランジスタのゲート酸化膜。
代理人の氏名 弁理士 中尾敏男 ほか１名Ｎ１ｔｒｏ
ｃ１ｅｎ Ｄｏｓｅ （ｃｍ−りＡ頗↑ぺ
ト傾成 ゛
４僧１べ ５領域FIG. 1 is a cross-sectional view showing the method of manufacturing a MOS integrated circuit according to the present invention, FIG. 2 is a diagram showing the relationship between the dose of nitrogen ions by thermal oxidation and the film thickness of silicon oxide, and FIG.
FIG. 3 is a cross-sectional view showing a method for manufacturing an S integrated circuit. 1... Silicon semiconductor substrate, 2... Field oxide film, 4... Photoresist film, 6
...Polycrystalline silicon film, 7...Source region, 8...Drain region, 9...Nitrogen ion implantation layer, 10... Gate oxide film of low voltage operation MOS transistor, 11... High voltage operation MOS)' gate oxide film of transistor. Name of agent: Patent attorney Toshio Nakao and one other person N1tro
c1en Dose (cm-riA頗↑pe
゛4 monks 1be 5 areas
Claims (1)
形成領域に窒素イオンを加速注入した後、前記低電圧よ
り高い高電圧で動作するＭＯＳトランジスタ形成領域と
前記低電圧で動作するＭＯＳトランジスタ形成領域に同
時に熱酸化処理を行い、膜厚の異なるゲート酸化膜を同
時に形成することを特徴とするＭＯＳ集積回路の製造方
法。After accelerated nitrogen ions are implanted into a formation region of a MOS transistor that operates at a low voltage on a semiconductor substrate, they are simultaneously implanted into a MOS transistor formation region that operates at a high voltage higher than the low voltage and a MOS transistor formation region that operates at a low voltage. A method for manufacturing a MOS integrated circuit, characterized by performing thermal oxidation treatment and simultaneously forming gate oxide films of different thicknesses.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62039452A JPS63205944A (en) | 1987-02-23 | 1987-02-23 | Manufacture of mos integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62039452A JPS63205944A (en) | 1987-02-23 | 1987-02-23 | Manufacture of mos integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63205944A true JPS63205944A (en) | 1988-08-25 |
Family
ID=12553429
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62039452A Pending JPS63205944A (en) | 1987-02-23 | 1987-02-23 | Manufacture of mos integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63205944A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07297298A (en) * | 1994-04-21 | 1995-11-10 | Lg Semicon Co Ltd | Manufacture of memory device |
| GB2327810A (en) * | 1997-02-07 | 1999-02-03 | United Microelectronics Corp | Manufacturing integrated circuit devices with different gate oxide thicknesses |
| NL1006803C2 (en) * | 1997-08-20 | 1999-02-23 | United Microelectronics Corp | Implanting nitride to produce gate oxide with different-thickness in hybrid and insertion ULSI |
| US6140185A (en) * | 1998-05-15 | 2000-10-31 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
| EP0766870B1 (en) * | 1995-04-21 | 2001-10-10 | Koninklijke Philips Electronics N.V. | Method of manufacturing a progammable semiconductor device in the form of an anti-fuse |
| US6410991B1 (en) | 1998-06-15 | 2002-06-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| KR100411025B1 (en) * | 2001-12-11 | 2003-12-18 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100473735B1 (en) * | 2002-10-14 | 2005-03-10 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
-
1987
- 1987-02-23 JP JP62039452A patent/JPS63205944A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07297298A (en) * | 1994-04-21 | 1995-11-10 | Lg Semicon Co Ltd | Manufacture of memory device |
| EP0766870B1 (en) * | 1995-04-21 | 2001-10-10 | Koninklijke Philips Electronics N.V. | Method of manufacturing a progammable semiconductor device in the form of an anti-fuse |
| GB2327810A (en) * | 1997-02-07 | 1999-02-03 | United Microelectronics Corp | Manufacturing integrated circuit devices with different gate oxide thicknesses |
| FR2767965A1 (en) * | 1997-02-07 | 1999-03-05 | United Microelectronics Corp | Implanting nitride to produce gate oxide with different-thickness in hybrid and insertion ULSI |
| GB2327810B (en) * | 1997-02-07 | 1999-06-09 | United Microelectronics Corp | Manufacturing integrated circuit devices with different gate oxide thicknesses |
| NL1006803C2 (en) * | 1997-08-20 | 1999-02-23 | United Microelectronics Corp | Implanting nitride to produce gate oxide with different-thickness in hybrid and insertion ULSI |
| US6140185A (en) * | 1998-05-15 | 2000-10-31 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device |
| US6410991B1 (en) | 1998-06-15 | 2002-06-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and method of manufacturing the same |
| KR100411025B1 (en) * | 2001-12-11 | 2003-12-18 | 주식회사 하이닉스반도체 | Method of manufacturing a semiconductor device |
| KR100473735B1 (en) * | 2002-10-14 | 2005-03-10 | 매그나칩 반도체 유한회사 | Method of manufacturing a semiconductor device |
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