JPH05326691A - Method for forming element isolation region - Google Patents

Method for forming element isolation region

Info

Publication number
JPH05326691A
JPH05326691A JP12891292A JP12891292A JPH05326691A JP H05326691 A JPH05326691 A JP H05326691A JP 12891292 A JP12891292 A JP 12891292A JP 12891292 A JP12891292 A JP 12891292A JP H05326691 A JPH05326691 A JP H05326691A
Authority
JP
Japan
Prior art keywords
element isolation
isolation region
silicon substrate
film
oxygen ions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12891292A
Other languages
Japanese (ja)
Inventor
Tomohito Nakamura
智史 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP12891292A priority Critical patent/JPH05326691A/en
Publication of JPH05326691A publication Critical patent/JPH05326691A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable a narrow and high aspect ratio of element isolation region to be formed and materialize high integration by applying heat treatment to a silicon substrate, after selectively implanting oxygen ions into a silicon substrate, so as to selectively form the element isolation area in a silicon substrate. CONSTITUTION:A protective film 2 and a resist film 3 are formed in order on a silicon substrate 1, and then the place in which to form an element isolation region is patterned, and with the patterned resist film 3 as a mask, the protective film 2 is etched to form an opening. Next, oxygen ions are implanted into the silicon substrate 1, and then oxygen ions are implanted into the silicon substrate 1, and then they are heat-treated from three to four hours at about 1200-1300 deg.C in the mixed atmosphere of argon and a very small quantity of oxygen, whereby the oxygen whose ions are implanted into the silicon substrate 1 and silicon are compounded to form an silicon oxide film, thus an element isolation area 6 is formed. Lastly, the protective film 2 used as the protective film is removed lastly, whereby a semiconductor substrate where the element formation region 1a is separated by the insulating film can be gotten.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は素子分離領域形成法に関
する。さらに詳しくは、幅狭でかつ高アスペクト比の素
子分離領域を形成することができ、集積回路の微細化を
図ることができる素子分離領域形成法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation region forming method. More specifically, the present invention relates to a method for forming an element isolation region, which can form an element isolation region having a narrow width and a high aspect ratio and can achieve miniaturization of an integrated circuit.

【0002】[0002]

【従来の技術】従来より、動作時における素子間の電気
的な干渉を防止して個々の素子が完全に独立して制御さ
れるように、素子形成領域を取り巻くようにして素子分
離領域を形成することが行なわれている。図5〜9は、
かかる素子分離技術のうち、現在一般に行なわれている
トレンチ型素子分離領域形成法の工程説明図である。
2. Description of the Related Art Conventionally, an element isolation region is formed so as to surround an element formation region so that electrical interference between the elements during operation is prevented and each element is completely independently controlled. Is being done. 5-9
FIG. 7 is a process explanatory view of a trench type element isolation region forming method which is currently generally performed among the element isolation techniques.

【0003】トレンチ型素子分離領域形成法において
は、図5に示されるように、まずレジスト膜13を形成
し、ついでエッチングによりシリコン基板11上の酸化
膜12のパターニングを行なう(図6参照)。ついで、
酸化膜12をマスクとして異方性エッチングによりシリ
コン基板11にトレンチ14を形成する(図7参照)。
つぎに、表面の酸化膜を除去し、CVD法などによって
別の酸化膜をトレンチ内に埋め込む(図8参照)。最後
に素子形成領域上の酸化膜を除去する(図9参照)。
In the trench type element isolation region forming method, as shown in FIG. 5, a resist film 13 is first formed, and then an oxide film 12 on a silicon substrate 11 is patterned by etching (see FIG. 6). Then,
A trench 14 is formed in the silicon substrate 11 by anisotropic etching using the oxide film 12 as a mask (see FIG. 7).
Next, the oxide film on the surface is removed, and another oxide film is embedded in the trench by the CVD method or the like (see FIG. 8). Finally, the oxide film on the element formation region is removed (see FIG. 9).

【0004】[0004]

【発明が解決しようとする課題】しかしながら、かかる
トレンチを形成する方法は、LOCOS分離よりも幅狭
に素子分離が可能という利点があるものの、形成したト
レンチに絶縁物を埋め込む必要があるため、高アスペク
ト比(本明細書において高アスペクト比とは、開口部の
幅と深さの比が大きいこと、すなわち、トレンチの断面
形状が幅狭で深いことをいう)のばあいや、幅狭のばあ
いには絶縁物を確実にトレンチ内に埋め込むことができ
ないという問題があった。このため、素子分離幅を小さ
くするのに限界があり、集積回路の微細化を図るうえで
障害となっていた。
However, although the method of forming such a trench has an advantage that element isolation can be performed with a narrower width than LOCOS isolation, it is necessary to bury an insulator in the formed trench. In the case of an aspect ratio (a high aspect ratio in this specification means that the ratio of the width and the depth of the opening is large, that is, the cross-sectional shape of the trench is narrow and deep), and the case of the narrow width. However, there is a problem that the insulator cannot be surely buried in the trench. Therefore, there is a limit to reducing the element isolation width, which is an obstacle to miniaturization of integrated circuits.

【0005】本発明は、叙上の事情に鑑み、幅狭でかつ
高アスペクト比の素子分離領域を形成することができる
素子分離領域形成法を提供することを目的とする。
In view of the above circumstances, it is an object of the present invention to provide a device isolation region forming method capable of forming a device isolation region having a narrow width and a high aspect ratio.

【0006】[0006]

【課題を解決するための手段】本発明は、シリコン基板
に選択的に酸素イオンを注入し、ついで前記シリコン基
板に熱処理を施して、シリコン基板中に選択的にシリコ
ン酸化膜を形成することを特徴としている。
According to the present invention, oxygen ions are selectively implanted into a silicon substrate, and then the silicon substrate is subjected to heat treatment to selectively form a silicon oxide film in the silicon substrate. It has a feature.

【0007】[0007]

【実施例】以下、添付図面を参照しつつ本発明の素子分
離領域形成法を説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for forming an element isolation region of the present invention will be described below with reference to the accompanying drawings.

【0008】図1〜4は本発明の素子分離領域形成法の
一実施例の工程説明図である。
1 to 4 are process explanatory views of an embodiment of the element isolation region forming method of the present invention.

【0009】まず、シリコン基板1上にLP−CVD
法、熱酸化法などにより、酸化シリコン、チッ化シリコ
ンなどの保護膜2を形成する。この保護膜2の厚さは、
本発明においてとくに限定されないが、素子形成領域に
対する酸素イオンの注入を確実に防止できるという点か
らは、えようとする素子分離領域の深さの70%以上の
厚さであるのが好ましい。この保護膜2の上にさらにレ
ジスト膜3を形成し、フォトリソグラフィ工程により素
子分離領域形成場所のパターニングを行う(図1参
照)。
First, LP-CVD is performed on the silicon substrate 1.
Method, thermal oxidation method or the like to form the protective film 2 of silicon oxide, silicon nitride or the like. The thickness of this protective film 2 is
Although not particularly limited in the present invention, the thickness is preferably 70% or more of the depth of the element isolation region to be obtained from the viewpoint that oxygen ion implantation into the element formation region can be reliably prevented. A resist film 3 is further formed on the protective film 2, and a patterning of a device isolation region forming place is performed by a photolithography process (see FIG. 1).

【0010】ついで、レジスト膜3をマスクとして保護
膜2をエッチングし開口部4を形成する(図2参照)。
Next, the protective film 2 is etched using the resist film 3 as a mask to form an opening 4 (see FIG. 2).

【0011】この開口部4は酸素イオン打込みのための
開口部で、素子分離領域の幅を決定するもので、0.5
〜1μmの狭い幅の開口が形成される。
The opening 4 is an opening for implanting oxygen ions and determines the width of the element isolation region.
Apertures with a narrow width of ˜1 μm are formed.

【0012】つぎに、酸素イオンをシリコン基板1中に
注入する。酸素イオンのドーズ量は完全な酸化膜形成の
点からは0.2×1018cm-2以上であるのが好まし
い。また、加速エネルギーは、通常50〜80keVで
あるが、深い素子分離領域形成の点からは500〜10
00keVであるのが好ましい。このばあい、形成した
い素子分離領域の深さに応じて、深さ方向に均一なイオ
ン濃度となるように、イオン注入の加速エネルギーを複
数回または無段階に変化させるのが好ましい。具体的に
は、深さ2μmの素子分離領域を形成するのに、ドーズ
量を1×1018cm-2で一定にし、加速エネルギーを9
00keV、400keV、100keVと変化させて
イオン注入を行うと、ほぼ均一な酸素イオン打込み領域
が2μmの深さで形成される。
Next, oxygen ions are implanted into the silicon substrate 1. The dose of oxygen ions is preferably 0.2 × 10 18 cm −2 or more from the viewpoint of complete oxide film formation. The acceleration energy is usually 50 to 80 keV, but 500 to 10 from the viewpoint of forming a deep element isolation region.
It is preferably 00 keV. In this case, it is preferable to change the acceleration energy of ion implantation a plurality of times or steplessly so that the ion concentration is uniform in the depth direction, depending on the depth of the element isolation region to be formed. Specifically, in order to form a device isolation region having a depth of 2 μm, the dose amount is kept constant at 1 × 10 18 cm −2 and the acceleration energy is 9
When ion implantation is performed while changing the pressure to 00 keV, 400 keV, and 100 keV, a substantially uniform oxygen ion implantation region is formed with a depth of 2 μm.

【0013】すなわち、シリコン基板1への酸素イオン
の打込みは、加速エネルギーが900keVのときは2
μm位の深さに最も濃い濃度で正規分布的に分布され、
加速エネルギーを400keVにすると1μm位の深さ
を中心に分布し、100keVにすると0.2μm位の
深さを中心に分布する。したがって、2μm位の深さの
素子分離領域を形成するには、この深さ内に酸素イオン
を打ち込んで酸化させる必要があり、前述のように、加
速エネルギーを変えてイオン打込みをする必要がある。
前述のイオン打込みの深さを変えるという趣旨からは加
速エネルギーを階段的に変化させるよりも連続的に変化
させる方が好ましく、このばあいは、たとえば50〜9
00keVを連続的に変化させるようにし、それを2回
位繰り返すことにより2μmの深さの狭い酸素イオン打
込み領域が形成される。
That is, the implantation of oxygen ions into the silicon substrate 1 is 2 when the acceleration energy is 900 keV.
It is distributed like a normal distribution at the deepest concentration at the depth of μm,
When the acceleration energy is 400 keV, the distribution is centered on a depth of about 1 μm, and when the acceleration energy is 100 keV, the distribution is centered on a depth of about 0.2 μm. Therefore, in order to form a device isolation region having a depth of about 2 μm, it is necessary to implant oxygen ions within this depth to oxidize, and as described above, it is necessary to implant ions by changing the acceleration energy. ..
From the point of changing the depth of ion implantation, it is preferable to change the acceleration energy continuously rather than stepwise, and in this case, for example, 50 to 9
By continuously changing 00 keV and repeating it about twice, an oxygen ion implantation region having a narrow depth of 2 μm is formed.

【0014】なお、イオン注入に際して、イオンが基板
内に入り易くするために基板温度を上げるようにしても
よい。このばあい、基板温度としては500〜600℃
程度が好ましい。
During the ion implantation, the substrate temperature may be raised so that the ions can easily enter the substrate. In this case, the substrate temperature is 500 to 600 ° C.
A degree is preferable.

【0015】ついで、アルゴンと微量の酸素の混合雰囲
気中で1200〜1300℃、3〜4時間の熱処理を行
なうことにより、シリコン基板1中にイオン打込みされ
た酸素とシリコンとが化合して酸化シリコン膜が形成さ
れ、素子分離領域6が形成される。最後にマスクとして
用いた基板表面の保護膜2を除去することにより、素子
形成領域1aが絶縁膜で分離された半導体基板がえられ
る。
Next, heat treatment is performed at 1200 to 1300 ° C. for 3 to 4 hours in a mixed atmosphere of argon and a slight amount of oxygen, whereby the oxygen ion-implanted in the silicon substrate 1 and the silicon are combined to form silicon oxide. The film is formed and the element isolation region 6 is formed. Finally, the protective film 2 on the surface of the substrate used as the mask is removed to obtain a semiconductor substrate in which the element formation region 1a is separated by an insulating film.

【0016】前述の実施例では酸素イオンのイオン打込
みをドーズ量1×1018cm-2の例で説明したが、この
酸素イオンはシリコンの酸化物を形成するためのもので
あり、良質な酸化膜で絶縁性を良くするためにはドーズ
量は0.2×1018cm-2以上であることが望ましい。
すなわち、ドーズ量がこれより少ないと完全な酸化膜が
えられず、絶縁特性が低下する。また、さらに良好な絶
縁特性をうるためには、ドーズ量が1×1018cm-2
上であることが一層好ましい。
In the above-mentioned embodiment, the ion implantation of oxygen ions is explained with an example of a dose amount of 1 × 10 18 cm -2 . However, the oxygen ions are for forming silicon oxide, and are of high quality. In order to improve the insulating property of the film, the dose amount is preferably 0.2 × 10 18 cm -2 or more.
That is, if the dose amount is smaller than this, a perfect oxide film cannot be obtained, and the insulation characteristics deteriorate. Further, in order to obtain better insulating properties, the dose amount is more preferably 1 × 10 18 cm -2 or more.

【0017】また、保護膜2は、酸素イオンの注入の際
に、素子形成領域1aへ酸素イオンが打ち込まれるのを
防止するための膜で、素子形成領域1aへの酸素イオン
の打込みを完全に防ぐ必要があり、充分な厚さが必要と
なる。しかし、シリコン酸化膜やシリコンチッ化膜への
酸素イオンの注入深さは共にシリコン基板への注入深さ
の1/2位であるため、形成する素子分離領域の深さの
70%以上の厚さで保護膜が形成されれば充分である。
また、シリコン酸化膜やシリコンチッ化膜以外に、レジ
スト膜でもよいが、このばあいはイオン注入時の温度上
昇でレジスト膜が変形し易く、しかもイオン衝撃に破壊
され易いため、正確な精度で素子分離領域を形成しにく
いという面はある。
The protective film 2 is a film for preventing oxygen ions from being implanted into the element forming region 1a during implantation of oxygen ions, and completely implants oxygen ions into the element forming region 1a. It must be prevented and a sufficient thickness is required. However, since the implantation depth of oxygen ions into the silicon oxide film or the silicon nitride film is about 1/2 of the implantation depth into the silicon substrate, the thickness of 70% or more of the depth of the element isolation region to be formed. It is sufficient if the protective film is formed.
In addition to the silicon oxide film and the silicon nitride film, a resist film may be used, but in this case, the resist film is easily deformed due to the temperature rise during ion implantation, and moreover, the resist film is easily broken by ion bombardment. It is difficult to form the element isolation region.

【0018】[0018]

【発明の効果】以上説明したとおり、本発明の素子分離
領域形成法では、保護膜をマスクとしてシリコン基板に
酸素イオンを打ち込み、ついでシリコン基板を熱処理し
て素子分離領域を形成するようにしているので、幅狭で
かつ高アスペクト比の素子分離領域を形成することがで
き、これにより集積回路の微細化を図ることができる。
As described above, in the element isolation region forming method of the present invention, oxygen ions are implanted into the silicon substrate using the protective film as a mask, and then the silicon substrate is heat-treated to form the element isolation region. Therefore, it is possible to form an element isolation region having a narrow width and a high aspect ratio, and thereby miniaturization of the integrated circuit can be achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の素子分離形成領域形成法の一実施例の
工程説明図である。
FIG. 1 is a process explanatory view of an example of a method for forming an element isolation formation region of the present invention.

【図2】本発明の素子分離形成領域形成法の一実施例の
工程説明図である。
FIG. 2 is a process explanatory view of an example of an element isolation formation region forming method of the present invention.

【図3】本発明の素子分離形成領域形成法の一実施例の
工程説明図である。
FIG. 3 is a process explanatory view of an example of the element isolation formation region forming method of the present invention.

【図4】本発明の素子分離形成領域形成法の一実施例の
工程説明図である。
FIG. 4 is a process explanatory view of an example of the element isolation formation region forming method of the present invention.

【図5】従来のトレンチ型素子分離領域形成法の工程説
明図である。
FIG. 5 is a process explanatory view of a conventional trench type element isolation region forming method.

【図6】従来のトレンチ型素子分離領域形成法の工程説
明図である。
FIG. 6 is a process explanatory view of a conventional trench type element isolation region forming method.

【図7】従来のトレンチ型素子分離領域形成法の工程説
明図である。
FIG. 7 is a process explanatory view of a conventional trench type element isolation region forming method.

【図8】従来のトレンチ型素子分離領域形成法の工程説
明図である。
FIG. 8 is a process explanatory view of a conventional trench type element isolation region forming method.

【図9】従来のトレンチ型素子分離領域形成法の工程説
明図である。
FIG. 9 is a process explanatory view of a conventional trench type element isolation region forming method.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 保護膜 3 レジスト膜 6 素子分離領域 1 Silicon substrate 2 Protective film 3 Resist film 6 Element isolation region

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板に選択的に酸素イオンを注
入し、ついで前記シリコン基板に熱処理を施して、シリ
コン基板中に選択的に素子分離領域を形成することを特
徴とする素子分離領域形成法。
1. A method for forming an element isolation region, which comprises selectively implanting oxygen ions into a silicon substrate and then subjecting the silicon substrate to a heat treatment to selectively form an element isolation region in the silicon substrate. ..
【請求項2】 選択的に酸素イオンを注入するに際し、
シリコン酸化膜またはシリコンチッ化膜からなる保護膜
をマスクとして用い、その膜厚が素子分離領域の基板垂
直方向の長さの70%以上の厚さである請求項1記載の
素子分離領域形成法。
2. When selectively implanting oxygen ions,
2. The method for forming an element isolation region according to claim 1, wherein a protective film made of a silicon oxide film or a silicon nitride film is used as a mask, and the film thickness is 70% or more of the length of the element isolation region in the direction perpendicular to the substrate. ..
【請求項3】 酸素イオン注入時の加速エネルギーを複
数回または連続的に変化させる請求項1記載の素子分離
領域形成法。
3. The method for forming an element isolation region according to claim 1, wherein the acceleration energy during oxygen ion implantation is changed a plurality of times or continuously.
【請求項4】 酸素イオンのドーズ量が0.2×1018
cm-2以上である請求項1記載の素子分離領域形成法。
4. A dose amount of oxygen ions is 0.2 × 10 18.
The method for forming an element isolation region according to claim 1, wherein the element isolation region is at least cm -2 .
JP12891292A 1992-05-21 1992-05-21 Method for forming element isolation region Pending JPH05326691A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12891292A JPH05326691A (en) 1992-05-21 1992-05-21 Method for forming element isolation region

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12891292A JPH05326691A (en) 1992-05-21 1992-05-21 Method for forming element isolation region

Publications (1)

Publication Number Publication Date
JPH05326691A true JPH05326691A (en) 1993-12-10

Family

ID=14996444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12891292A Pending JPH05326691A (en) 1992-05-21 1992-05-21 Method for forming element isolation region

Country Status (1)

Country Link
JP (1) JPH05326691A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100571412B1 (en) * 2003-12-26 2006-04-14 동부아남반도체 주식회사 Manufacturing Method of Semiconductor Device
KR100763333B1 (en) * 2006-05-16 2007-10-04 삼성전자주식회사 Method of forming an isolation layer of a semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100571412B1 (en) * 2003-12-26 2006-04-14 동부아남반도체 주식회사 Manufacturing Method of Semiconductor Device
KR100763333B1 (en) * 2006-05-16 2007-10-04 삼성전자주식회사 Method of forming an isolation layer of a semiconductor device
US7781302B2 (en) 2006-05-16 2010-08-24 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices having isolation regions formed from annealed oxygen ion implanted regions

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