JPH1126392A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable formation of a transistor of triple well structure, without increasing the number of processes. SOLUTION: This method is provided with the following: a process wherein a thin resist mask 13 of about 2-2.5 μm thick is formed on a semiconductor substrate 10 in which element isolation regions 11 are formed, and then phosphorus ions are implanted in the semiconductor substrate 10 by an accelerating voltage 3 MV, a process for implanting phosphorus ions by an accelerating voltage 2.3 MV, a process for implanting boron ions by an acceleration voltage 100 KV, a process for eliminating the resist mask 13, and a process for heat- treating the semiconductor substrate 10. Thereby a transistor of triple-well structure can be formed by using a single resist mask 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a triple well transistor without increasing the number of steps.

[0002]

2. Description of the Related Art In MOS type semiconductor integrated circuit devices, problems in electrical characteristics such as latch-up and soft errors are becoming more serious as design dimensions become finer. As a method for avoiding this problem, there is a method of forming a transistor having a triple well structure. M using this method
FIGS. 3 and 4 show an example of an OS transistor formation method.

First, as shown in FIG. 3A, an element isolation region 21 is formed on a silicon substrate 20. Next, FIG.
As shown in (b), after a region on which an n-well region 25 will be formed later is masked with a resist 22 having a thickness of about 5 μm,
For example, P ions are converted to 1 × 10 ¹³ (/ c) at an acceleration voltage of 3 MeV.
m ² ) Implant to form an n ⁺ layer 23 at the bottom.

Next, as shown in FIG. 3C, the resist mask 22 is removed, and after masking with a resist material 24 having a thickness of about 2.54 μm on a region where a p-well region 28 is to be formed, for example, a P ion Is 1 × 10 at an acceleration voltage of 1 MeV.
¹³ (/ cm ² ) is implanted to form an n-well region 25.

Then, as shown in FIG. 4A, after the resist mask 24 is removed, a mask is formed on the n-well region 25 with a resist material 26 having a thickness of 1.5 μm. The area of the mask 26 is different from that of the initial mask 22, as indicated by reference numeral 27. This is necessary to surround the p-well region with the n-well region.

Thereafter, as shown in FIG. 4B, 5 × 10 ¹² (/ cm ² ) of B ions are implanted at, for example, 500 keV to form a p-well region 28.

[0007]

In the above-described method, three masks are required to form a well region. In addition, there has been a problem that the number of steps increases accordingly. Accordingly, the present invention provides a method of manufacturing a semiconductor device in which a transistor having a triple well structure can be formed with a single mask by performing ion implantation with varied implantation energy through a resist. Aim.

[0008]

According to a method of manufacturing a semiconductor device of the present invention, a first step of forming a photoresist in a first region on a semiconductor substrate on which an element isolation region is formed; After the step, a second step of ion-implanting an n-type impurity into the semiconductor substrate at a first implantation energy; and after the second step, a second step lower than the first implantation energy into the semiconductor substrate. A third step of ion-implanting the n-type impurity at an implantation energy of; a fourth step of ion-implanting a p-type impurity into the semiconductor substrate after the third step; and after the fourth step. A fifth step of removing the photoresist, and a sixth step of performing a heat treatment on the semiconductor substrate after the fifth step.

Another feature of the present invention is that
The photoresist has a thickness of 2.0 to 2.5 μm.

In another feature of the present invention, the n-type impurity is a phosphorus ion and the p-type impurity is a boron ion.

According to another feature of the present invention, the first implantation energy is 3 MeV, the second implantation energy is 2.0 to 2.5 MeV,
Further, in the fourth step, the p-type impurity is
It is characterized by ion implantation at 00 to 450 keV.

[0012]

1 and 2 show an embodiment of a method for manufacturing a semiconductor device according to the present invention. First, as shown in FIG. 1A, an element isolation region 11 is formed on a semiconductor substrate 10. Next, as shown in FIG.
A film thickness of 2.0 to 2.5 is formed on the region where the well region 12 is formed.
After forming a resist mask 13 having a thickness of about 2.3 μm, preferably about 2.3 μm, P ions are implanted at an acceleration voltage of 3 MeV to 1 × 10 ^13.
(/ Cm ² ). At this time, P ions are implanted into a region having a depth of about 2.7 μm, which is a deep portion in the P well region, to form the n ⁺ layer 14.

On the other hand, P ions are implanted into a region having a depth of 1.04 μm in a region where the n-well region 12 is to be formed, and this serves as the n-well region 12. Then, FIG.
As shown in (c), the P ions are converted to an acceleration voltage of 2.0 to 2.0.
2.5 MeV, preferably 4 × 10 ¹² (/ c) at 2.3 MeV
m ² ) Inject.

This is because the surface concentration of the n-type impurity in the n-well region 12 is insufficient, and the implantation is performed for the purpose of filling and for preventing the n-type impurity surrounding the p-well region immediately below the element isolation region 11 from being interrupted. Is what you do.

Subsequently, as shown in FIG. 2A, B ions are implanted at an acceleration voltage of 400 to 450 keV. Preferably, 5 × 10 ¹² (/ cm ² ) is implanted at 450 keV,
A p-well region 15 is formed.

At this time, since the resist mask 13 exists, B ions do not enter the n-well region 12. Next, as shown in FIG. 2B, after removing the resist mask 13, a heat treatment is performed, for example, at 950 ° C. for 30 minutes.
The respective well regions 12, 14, 15 are formed.

When a well region is formed by this method, an arbitrary isolation method such as LOCOS or trench isolation can be used as an element isolation method, regardless of the isolation method. Further, it may include a step of forming a silicon oxide film for protecting the surface of the substrate.

[0018]

As described above, in the present invention,
Boron ions implanted at a photoresist film thickness of, for example, about 500 keV are not allowed to pass, and 2.3.
By controlling the film thickness so that phosphor ions implanted at about MeV can pass, ion implantation can be performed through a resist, so that a transistor having a triple well structure can be formed with one mask. .

Furthermore, since the n-well region can be formed in a self-aligned manner, the n-well region surrounding the p-well region is not interrupted by a mask shift, and a semiconductor device having good characteristics can be manufactured. Can be.

[Brief description of the drawings]

FIG. 1 is a process sectional view showing an embodiment of the present invention.

FIG. 2 is a process cross-sectional view illustrating the embodiment of the present invention.

FIG. 3 is a process sectional view showing the formation of a conventional MOS transistor.

FIG. 4 is a process sectional view showing the formation of a conventional MOS transistor.

[Explanation of symbols]

 Reference Signs List 10 semiconductor substrate 11 element isolation region 12 n-well region 13 resist mask (on n-well region) 14 n-well region 15 p-well region

Claims (4)

[Claims] A first step of forming a photoresist in a first region on a semiconductor substrate on which an element isolation region is formed; and after the first step, a first implantation energy is applied to the semiconductor substrate. a second step of ion-implanting an n-type impurity; and after the second step, the n-type impurity is implanted into the semiconductor substrate at a second implantation energy lower than the first implantation energy.
A third step of ion-implanting a p-type impurity, a fourth step of ion-implanting a p-type impurity into the semiconductor substrate after the third step, and a step of removing the photoresist after the fourth step. A method for manufacturing a semiconductor device, comprising: a fifth step; and a sixth step of performing a heat treatment on the semiconductor substrate after the fifth step. 2. The method according to claim 1, wherein the photoresist has a thickness of 2.0 to 2.0.
The method according to claim 1, wherein the thickness is 2.5 μm. 3. The method according to claim 1, wherein the n-type impurities are phosphorus ions, and the p-type impurities are boron ions. 4. The first implantation energy is 3 MeV, and the second implantation energy is 2.0 to 2.5 MeV.
2. The method according to claim 1, wherein in the fourth step, the p-type impurity is ion-implanted at 400 to 450 keV. 3.