JP2647842B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

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Publication number
JP2647842B2
JP2647842B2 JP62007800A JP780087A JP2647842B2 JP 2647842 B2 JP2647842 B2 JP 2647842B2 JP 62007800 A JP62007800 A JP 62007800A JP 780087 A JP780087 A JP 780087A JP 2647842 B2 JP2647842 B2 JP 2647842B2
Authority
JP
Japan
Prior art keywords
layer
titanium
forming
diffusion region
titanium nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62007800A
Other languages
Japanese (ja)
Other versions
JPS63175420A (en
Inventor
誠一郎 三原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62007800A priority Critical patent/JP2647842B2/en
Publication of JPS63175420A publication Critical patent/JPS63175420A/en
Application granted granted Critical
Publication of JP2647842B2 publication Critical patent/JP2647842B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device.

〔従来の技術〕[Conventional technology]

半導体装置の高集積化技術の一つとして自己整合型の
コンタクト形成法が用いられるが、シリコン基板とアル
ミニウム電極との相互反応によって生ずる突抜け(アロ
イ・スパイク)が高集積化で要求される浅い接合のため
発生し易くなり、この突抜けを防止するため窒化チタン
等の障壁金属層を介して電極をコンタクトさせる方法が
用いられている。
A self-aligned contact formation method is used as one of the high integration techniques for semiconductor devices. However, a punch-through (alloy spike) caused by an interaction between a silicon substrate and an aluminum electrode is a shallow area required for high integration. A method of contacting an electrode through a barrier metal layer such as titanium nitride has been used to prevent the occurrence of penetration due to bonding.

従来の半導体装置の製造方法は、一導電型の半導体基
板上に逆導電型の拡散領域を形成し、前記半導体基板表
面を覆う絶縁層を形成する。次に、前記拡散領域上の前
記絶縁層にコンタクト用開孔部を設けた後全面にチタン
層を形成し、熱処理を行って前記開孔部の露出した前記
拡散領域表面と接する領域にチタン硅化物層を形成し、
エッチング法で絶縁層上のチタン層を除去する。次に、
反応性スパッタリング法により窒素雰囲気中でチタンを
スパッタリングして全面に窒化チタン層を形成し、前記
窒化チタン層の上にアルミニウム層を形成した後前記ア
ルミニウム層と窒化チタン層を選択的にエッチングして
前記拡散領域とコンタクトする配線を形成する。
In a conventional method for manufacturing a semiconductor device, a diffusion region of the opposite conductivity type is formed on a semiconductor substrate of one conductivity type, and an insulating layer covering the surface of the semiconductor substrate is formed. Next, a titanium layer is formed on the entire surface after providing a contact opening in the insulating layer on the diffusion region, and heat treatment is performed to form a titanium silicide in a region of the opening that is in contact with the surface of the diffusion region exposed. Material layer,
The titanium layer on the insulating layer is removed by an etching method. next,
Titanium is sputtered in a nitrogen atmosphere by a reactive sputtering method to form a titanium nitride layer on the entire surface, and after the aluminum layer is formed on the titanium nitride layer, the aluminum layer and the titanium nitride layer are selectively etched. An interconnect is formed to contact the diffusion region.

また、前記窒化チタン層を形成する他の例は、前記チ
タン硅化物層を形成した後に前記半導体基板を窒素雰囲
気中で熱処理し前記チタン硅化物層の表面に窒化チタン
層を形成していた。
In another example of forming the titanium nitride layer, after forming the titanium silicide layer, the semiconductor substrate is heat-treated in a nitrogen atmosphere to form a titanium nitride layer on the surface of the titanium silicide layer.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

上述した従来の半導体装置の製造方法は、窒化チタン
層を反応性スパッタリング法で形成する場合に窒素ガス
とアルゴンガスの分圧によってTiNxの組成が異なり制御
性が難しい。また、窒化チタン層を全面に被着後アルミ
ニウム層を被着して配線を形成する加工を行うが、窒化
チタン層はドライエッチングが困難で微細な配線が形成
し難いという問題点がある。また、チタン硅化物層を窒
素雰囲気中で熱処理し、その表面を窒化チタン層にする
方法は、表面状態により反応が不均一になり再現性が悪
くなる問題点を生ずる。
In the conventional method of manufacturing a semiconductor device described above, when the titanium nitride layer is formed by the reactive sputtering method, the composition of TiNx varies depending on the partial pressure of the nitrogen gas and the argon gas, and controllability is difficult. Further, a process of forming a wiring by applying an aluminum layer after applying a titanium nitride layer on the entire surface is performed. However, there is a problem in that the titanium nitride layer is difficult to dry-etch and it is difficult to form fine wiring. In addition, the method of heat-treating a titanium silicide layer in a nitrogen atmosphere to form a titanium nitride layer on the surface has a problem that the reaction becomes non-uniform depending on the surface state and the reproducibility is deteriorated.

本発明の目的は、突抜けを防止するための障壁金属層
を再現性良く形成する半導体装置の製造方法を提供する
ことにある。
An object of the present invention is to provide a method of manufacturing a semiconductor device in which a barrier metal layer for preventing penetration is formed with good reproducibility.

〔問題点を解決するための手段〕[Means for solving the problem]

本発明の半導体装置の製造方法は、一導電型半導体基
板の一主面に逆導電型の拡散領域を形成する工程と、前
記拡散領域を含む表面に絶縁層を形成した後前記拡散領
域上の前記絶縁膜に開孔部を形成する工程と、前記開孔
部に露出した拡散領域を含む前記絶縁膜上にチタン層を
堆積して熱処理し前記拡散領域の表面と接触している部
分にチタン硅化物層を形成する工程と、未反応の前記チ
タン層をエッチングして除去した後前記チタン硅化物層
の表面に窒素イオンをイオン注入して熱処理し前記チタ
ン硅化物層の表面に窒化チタン層を形成する工程と、前
記窒化チタン層を含む表面に金属層を堆積してパターニ
ングし前記拡散領域と電気的に接続する配線を形成する
工程とを含んで構成される。
The method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a reverse conductivity type diffusion region on one main surface of a one conductivity type semiconductor substrate; and forming an insulating layer on a surface including the diffusion region. Forming an opening in the insulating film, depositing a titanium layer on the insulating film including the diffusion region exposed to the opening, performing heat treatment, and forming a titanium layer in a portion in contact with the surface of the diffusion region. Forming a silicide layer; etching and removing the unreacted titanium layer; implanting nitrogen ions into the surface of the titanium silicide layer; and heat-treating the surface of the titanium silicide layer. And a step of depositing and patterning a metal layer on a surface including the titanium nitride layer to form a wiring electrically connected to the diffusion region.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明す
る。
Next, embodiments of the present invention will be described with reference to the drawings.

第1図(a)〜(c)は本発明の一実施例を説明する
ための工程順に示した半導体チップの断面図である。
1 (a) to 1 (c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.

まず、第1図(a)に示すように、一導電型のシリコ
ン基板1の一主面に素子分離用のフィールド絶縁層2を
形成して素子形成領域を形成し、該素子形成領域の表面
にゲート絶縁層3を介してゲート電極4を形成し、ゲー
ト電極4とフィールド絶縁層2とをマスクとしてシリコ
ン基板1に逆導電型の不純物を導入してソース領域5お
よびドレイン領域6を形成する。次に、シリコン基板1
の全面に絶縁層7を形成し、ソース領域5およびドレイ
ン領域6の上の絶縁層7に電極形成用の開孔部8を形成
する。
First, as shown in FIG. 1A, a field insulating layer 2 for element isolation is formed on one main surface of a silicon substrate 1 of one conductivity type to form an element formation region, and a surface of the element formation region is formed. A gate electrode 4 is formed via a gate insulating layer 3 and a source region 5 and a drain region 6 are formed by introducing a reverse conductivity type impurity into the silicon substrate 1 using the gate electrode 4 and the field insulating layer 2 as a mask. . Next, the silicon substrate 1
An insulating layer 7 is formed on the entire surface of the substrate, and an opening 8 for forming an electrode is formed in the insulating layer 7 on the source region 5 and the drain region 6.

次に、第1図(b)に示すように、開孔部8に露出し
たソース領域5およびドレイン領域6の表面と絶縁層7
を覆うチタン層をスパッタリング法で約1000Å堆積し、
窒素中で約600℃の熱処理を行い開孔部8のソース領域
5およびドレイン領域6の表面とチタン層が接触してい
る部分にチタン硅化物層9を約2000Åの厚さに生成させ
る。次に、絶縁層7の上のチタン層をH2O2+NH4OHのエ
ッチング液で除去する。
Next, as shown in FIG. 1B, the surface of the source region 5 and the drain region 6
About 1000 mm of titanium layer is deposited by sputtering.
A heat treatment at about 600 ° C. is performed in nitrogen to form a titanium silicide layer 9 to a thickness of about 2000 ° at a portion where the surface of the source region 5 and the drain region 6 of the opening 8 is in contact with the titanium layer. Next, the titanium layer on the insulating layer 7 is removed with an etchant of H 2 O 2 + NH 4 OH.

次に、第1図(c)に示すように、窒素を加速エネル
ギー30keV、ドーズ量1×1016cm-2でイオン注入する。
このときの投影飛程から窒素は表面から数100Åの深さ
に導入される。次に、約900℃の熱処理を行い、チタン
硅化物層9の表面に窒化チタン層10を形成し、チタン硅
化物層9に接続するアルミニウム配線11を選択的に形成
する。
Next, as shown in FIG. 1C, nitrogen ions are implanted at an acceleration energy of 30 keV and a dose of 1 × 10 16 cm −2 .
From the projection range at this time, nitrogen is introduced to a depth of several hundred degrees from the surface. Next, a heat treatment at about 900 ° C. is performed to form a titanium nitride layer 10 on the surface of the titanium silicide layer 9, and an aluminum wiring 11 connected to the titanium silicide layer 9 is selectively formed.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明は、拡散領域の表面に設け
た絶縁膜に開孔部を形成し、この開孔部に露出した拡散
領域の表面にのみチタン硅化物層を形成した後窒素イオ
ンをイオン注入してチタン硅化物層の表面に窒化チタン
層を形成することにより、バリア層を開孔部内にのみ形
成してエッチングの困難な窒化チタン層のパターニング
工程を不要とし、微細な配線を容易に形成できるという
効果を有する。
As described above, according to the present invention, an opening is formed in an insulating film provided on the surface of a diffusion region, and a titanium silicide layer is formed only on the surface of the diffusion region exposed to the opening, and then nitrogen ions are formed. By forming a titanium nitride layer on the surface of the titanium silicide layer by ion implantation, a barrier layer is formed only in the opening, eliminating the need for a patterning step of the titanium nitride layer that is difficult to etch, and facilitating fine wiring. This has the effect of being able to be formed into

また、窒素イオンのドーズ量の制御により、窒化チタ
ン層のTiとNとの構成比を所望の値に制御し易くし、再
現性良く窒化チタン層を形成できるという効果を有す
る。
Further, by controlling the dose of nitrogen ions, the composition ratio of Ti and N in the titanium nitride layer can be easily controlled to a desired value, and the titanium nitride layer can be formed with good reproducibility.

【図面の簡単な説明】[Brief description of the drawings]

第1図(a)〜(c)は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。 1……半導体基板、2……フィールド絶縁層、3……ゲ
ート絶縁層、4……ゲート電極、5……ソース領域、6
……ドレイン領域、7……絶縁層、8……開孔部、9…
…チタン硅化物層、10……窒化チタン層、11……アルミ
ニウム配線。
1 (a) to 1 (c) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Field insulating layer, 3 ... Gate insulating layer, 4 ... Gate electrode, 5 ... Source region, 6
... Drain region, 7... Insulating layer, 8.
... titanium silicide layer, 10 ... titanium nitride layer, 11 ... aluminum wiring.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】一導電型半導体基板の一主面に逆導電型の
拡散領域を形成する工程と、前記拡散領域を含む表面に
絶縁層を形成した後前記拡散領域上の前記絶縁膜に開孔
部を形成し前記拡散層の表面を露出する工程と、前記開
孔部に露出した前記拡散領域を含む前記絶縁膜上にチタ
ン層を堆積して熱処理し前記拡散領域の表面と接触して
いる部分にチタン硅化物層を形成する工程と、未反応の
前記チタン層をエッチングして除去した後前記チタン硅
化物層の表面に窒素イオンをイオン注入して熱処理し前
記チタン硅化物層の表面に窒化チタン層を形成する工程
と、前記窒化チタン層を含む表面に金属層を堆積してパ
ターニングし前記拡散領域と電気的に接続する配線を形
成する工程とを含むことを特徴とする半導体装置の製造
方法。
A step of forming a diffusion region of a reverse conductivity type on one principal surface of a semiconductor substrate of one conductivity type; forming an insulating layer on a surface including the diffusion region; Forming a hole and exposing the surface of the diffusion layer, and depositing a titanium layer on the insulating film including the diffusion region exposed to the opening and performing a heat treatment to contact the surface of the diffusion region. Forming a titanium silicide layer in the portion where the titanium silicide layer is present, etching the unreacted titanium layer, removing the unreacted titanium layer, implanting nitrogen ions into the surface of the titanium silicide layer, and heat-treating the surface of the titanium silicide layer. A step of forming a titanium nitride layer on the substrate, and a step of depositing and patterning a metal layer on a surface including the titanium nitride layer to form a wiring electrically connected to the diffusion region. Manufacturing method.
JP62007800A 1987-01-14 1987-01-14 Method for manufacturing semiconductor device Expired - Lifetime JP2647842B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62007800A JP2647842B2 (en) 1987-01-14 1987-01-14 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62007800A JP2647842B2 (en) 1987-01-14 1987-01-14 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS63175420A JPS63175420A (en) 1988-07-19
JP2647842B2 true JP2647842B2 (en) 1997-08-27

Family

ID=11675710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62007800A Expired - Lifetime JP2647842B2 (en) 1987-01-14 1987-01-14 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2647842B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508212A (en) * 1995-04-27 1996-04-16 Taiwan Semiconductor Manufacturing Co. Salicide process for a MOS semiconductor device using nitrogen implant of titanium
US5776831A (en) * 1995-12-27 1998-07-07 Lsi Logic Corporation Method of forming a high electromigration resistant metallization system
US5874351A (en) * 1996-06-13 1999-02-23 Micron Tecnology, Inc. Sputtered metal silicide film stress control by grain boundary stuffing
US5885896A (en) * 1996-07-08 1999-03-23 Micron Technology, Inc. Using implants to lower anneal temperatures

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60153121A (en) * 1984-01-20 1985-08-12 Nec Corp Fabrication of semiconductor device
JPS61101075A (en) * 1984-10-24 1986-05-19 Hitachi Ltd Manufacture of semiconductor device
JPS61142739A (en) * 1984-12-17 1986-06-30 Toshiba Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS63175420A (en) 1988-07-19

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