JPS5836505B2 - Method for manufacturing semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor memory device having one transistor and one capacitor memory cell.

Conventionally, as a device of the above type, one having the structure shown in FIG. 1 is known.

That is, the figure is an explanatory side cross-sectional view of the main parts, and 1 is a p-type silicon semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a capacitor electrode (first layer electrode) made of polycrystalline silicon, Reference numeral 5 indicates an insulating oxide film, 6 a transfer gate electrode (second layer electrode) made of polycrystalline silicon, and 7 an n+ type impurity region which is a bit line.

In this device, since the pit line is formed in the impurity region 7, its specific resistance is higher than IXIO-3 [Ω° steel], which is quite high.

As a result, signal delays will occur.

Generally, in order to reduce the resistance value of an impurity region, it is sufficient to form the region deeply, but this will also increase the lateral spread of diffusion, which will affect the gate length accuracy of the transfer gate. This results in deterioration of characteristics.

The present invention attempts to solve the above-mentioned conventional drawbacks by using an impurity-containing refractory metal silicide film as a bit line in the above-mentioned device, and will be described in detail below. do.

Note that the high melting point metal silicide mentioned here may have a different stoichiometric composition as long as it can maintain a stable state during heat treatment in the manufacturing process of a semiconductor device.

2 to 6 are sectional side views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and the following description will be made with reference to these figures.

In this embodiment, molybdenum silicide will be used as the metal silicide.

Refer to FIG. 2 (1) A field oxide film 2 is formed on the p-type silicon semiconductor substrate 1 by applying a selective oxidation method using, for example, a silicon nitride film as a mask.

(2) After removing the mask, a thermal oxidation method is applied to form a thin insulating oxide film 3.

(3) A molybdenum silicide film is formed by applying a sputtering method, and it is patterned by ordinary photolithography technology to form a capacitor electrode 4.

Refer to FIG. 3 (4) Using the capacitor electrode 4 as a mask, the oxide film 3 is patterned to form an opening 3A to expose a part of the surface of the substrate 10.

Note that this step may be omitted and the process may proceed to the next oxidation step.

In this case, the thickness of the exposed portion of the oxide film 30 increases.

Refer to FIG. 4 (5) Processing is performed in a high temperature oxidizing atmosphere to form a thermal oxide film 5 on the previously exposed surface of the substrate 1 and the surface of the capacitor electrode 40.

Refer to FIG. 5. (6) The oxide film 5 existing on the region where the bit line is to be formed is removed by photolithography technology.

(7) Sputtering is applied to form a molybdenum silicide film containing donor impurities such as phosphorus to a thickness of 3,000 ml, for example.
[A] Form in varying degrees.

In order to make the sputtering and emolybdenum silicide film contain phosphorus, for example, the sputtering atmosphere is changed to phosphine (P).
H3)/argon (Ar).

Further, as a method of impregnating phosphorus into molybdenum silicide, sputtering treatment may be performed with metallic phosphorus placed on a molybdenum tarket.

Furthermore, arsenic may be used as a donor impurity.

(8) The molybdenum silicide film is patterned using photolithography technology to form a transfer gate electrode 6G and a wiring 6B used as a pit line.

Note that a portion of the opening 3A remains on both sides of the wiring 6B.

(9) Applying the ion implantation method, arsenic (or phosphorus) is implanted to form the n+ type impurity introduction region 7.

Refer to FIG. 6 (10) Heat treatment is performed at a high temperature to activate the implanted ions in the region 7 and diffuse phosphorus from the wiring 6B, thereby joining the separated regions 7 into one.

01) Thereafter, a silicon dioxide film 8 (or a phosphosilicate glass film) is formed by chemical vapor deposition, and electrode contact windows are formed thereon, and electrodes and wiring are shaped to complete the process.

The bit line of the device thus completed is formed by the wiring 6B and the region 7.

FIG. 7 is a diagram showing the distribution when phosphorus is diffused from a phosphorus-containing molybdenum silicide film into a silicon semiconductor substrate by heat treatment.

As can be seen from the above description, according to the present invention, when manufacturing a semiconductor memory device having one transistor, one capacitor, and a memory cell, the wiring that becomes part of the transfer gate electrode and the bit line is doped with high impurity content. Since the bit line is made of melting point metal silicide, it is different from bit lines that use only polycrystalline silicon or impurity diffusion regions.
Since the resistance value is reduced by more than one order of magnitude, the propagation signal delay can also be reduced.

In addition, the impurity doped region that will become part of the bit line does not need to be diffused very deeply due to the existence of the wiring that will become part of the bit line, so the lateral spread of diffusion is also small, so a pattern as designed can be obtained. It is easy to do.

[Brief explanation of the drawing]

1 to 6 are side cross-sectional views of essential parts of a semiconductor device at key points in the process for explaining one embodiment of the present invention, and FIG. 7 is a diagram showing impurity distribution. In the figure, H is an engineered substrate, 2 is an oxide film, 3 is an oxide film, 4 is a capacitor electrode, 5 is an oxide film, 6B is a wiring, 6G is a transfer gate electrode, 7 is an impurity doped region, 8 is silicon dioxide It is a membrane.

Claims (1)

[Claims] 1 Form an oxide film on the active region of a semiconductor substrate of one conductivity type, then form a high melting point metal silicide film, pattern the high melting point metal silicide film to form a capacitor electrode, and mask the capacitor electrode. patterning the oxide film to expose a part of the surface of the active region, forming a gate oxide film on the exposed surface, and forming an insulating oxide film on the surface of the capacitor electrode; After patterning to form an opening for forming an impurity introduction region, a high melting point metal silicide film containing an impurity of the opposite conductivity type is formed, and the impurity containing high melting point metal silicide film is patterned to form a gate electrode and a gate electrode. After forming a wiring passing through the opening for forming the impurity doped region, impurities are introduced into the active region through the opening to form an opposite conductivity type impurity doped region facing the capacitor region and the channel region. A method of manufacturing a semiconductor memory device, comprising the steps of: . . . and thereafter diffusing impurities from the wiring.