JP2727576B2 - Method for manufacturing semiconductor device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having an electrode formed of a polycrystalline silicon layer.

[Conventional technology]

In the conventional method of manufacturing a semiconductor device, as shown in FIG. 2A, a polycrystalline silicon layer 9 doped with phosphorus is deposited on a silicon oxide film 2 formed on a silicon substrate 1. Next, a photoresist film 7 is formed on the polycrystalline silicon layer 9.
Is applied and patterned to form a required electrode forming pattern. Next, as shown in FIG. 2B, using the photoresist film 7 as a mask, the polycrystalline silicon layer 9 is etched by, for example, reactive ion etching using a chlorine-based gas to form an electrode composed of the polycrystalline silicon layer 9. I do.

At this time, since the polycrystalline silicon layer 9 is doped with phosphorus, it is easily etched, and a constriction 11 is formed at the interface between the reverse tapered portion 10 and the silicon oxide film 2 on the side surface of the electrode.

[Problems to be solved by the invention]

Horie et al. Described the above-mentioned conventional method of manufacturing a semiconductor device in the proceedings of symposium on dry.
Process (Proceedings of Symposium on Dry Proces)
s) 1981 October 26-27 days the 39 to 45 pages in the reactive ion etching of Phosphor doped polysilicon Yujingu _{· CF 3 Br-Cl 2 (} Reactive Ion Etc
As reported under the title of hing of P doped poly-Si using CF ₃ Br-Cl ₂ ), the cross-sectional shape of an electrode made of a phosphorus-doped polycrystalline silicon layer becomes reverse-tapered due to excessive etching, There is a problem that a constriction is formed at the interface with the film.

[Means for solving the problem]

In the method of manufacturing a semiconductor device according to the present invention, a non-doped polycrystalline silicon layer is formed on an insulating film provided on a semiconductor substrate, and a patterned first photoresist film is formed on the polycrystalline silicon layer. A step of implanting impurity ions into the surface of the polycrystalline silicon layer using the first photoresist film as a mask to provide an impurity ion implantation region; and removing the first photoresist film to remove the surface of the impurity ion implantation region. Selectively providing a second photoresist film having a pattern to cover, and forming an electrode having a required pattern by anisotropically removing the polycrystalline silicon layer using the second photoresist film as a mask; And a step of performing impurity diffusion and activation of the electrode by heat treatment.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

1 (a) to 1 (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.

First, as shown in FIG. 1A, a silicon oxide film 2 is provided on a silicon substrate 1, and a polycrystalline silicon layer 3 is deposited on the silicon oxide film 2 to a thickness of 0.6 μm. Next, a first photoresist film 4 is formed on the polycrystalline silicon layer 3.
Is applied and patterned to provide openings corresponding to the electrode forming patterns. Next, using the photoresist film 4 as a mask, phosphorus ions 5 are implanted at an acceleration energy of about 50 keV and a dose of about 1 × 10 ¹⁹ cm ⁻² , so that the phosphorus ions have a depth of 0.15 to 0.2 μm from the surface of the polycrystalline silicon layer 3. An implantation region 6 is formed. Here, the width of the phosphorus ion implanted region 6 is desirably formed to be smaller than the required electrode formation width by about 0.3 μm.

Next, as shown in FIG.
Is removed, and a second photoresist film 7 is applied to the surface including the phosphorus ion implanted region 6 and patterned to cover the surface of the phosphorus ion implanted region 6 and the polycrystalline silicon layer surrounding the region.

Next, as shown in FIG.
Is used as a mask to remove the polycrystalline silicon layer 3 by reactive ion etching using a chlorine-based gas such as CF ₂ Cl ₂ to form an electrode having a required pattern.
Here, the non-doped polycrystalline silicon layer 3 hardly causes an undercut, and can be patterned with high accuracy.

Next, as shown in FIG. 1 (d), annealing is performed at a temperature of 500 to 950 ° C. for 10 minutes to form an active region 8 in the electrode.

〔The invention's effect〕

As described above, the present invention provides a photoresist having an electrode forming pattern which is provided with an impurity ion implantation region in which impurity ions are selectively implanted in a part of a non-doped polycrystalline silicon layer, and which covers the surface of the impurity ion implantation region. Anisotropically etching the non-doped portion of the polycrystalline silicon layer using the film as a mask has the effect of preventing excessive etching of the side surface of the formed electrode and improving processing accuracy.

The electrode can be annealed after removing the photoresist film to diffuse and activate the impurities to obtain a required conductivity.

[Brief description of the drawings]

1 (a) to 1 (d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention, and FIGS. 2 (a) and 2 (b) show a conventional method of manufacturing a semiconductor device. FIG. 4 is a cross-sectional view of a semiconductor chip shown in the order of steps for explaining the method. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Silicon oxide film, 3 ... Polycrystalline silicon layer, 4 ... Photoresist film, 5 ... Phosphorus ion, 6 ... Phosphorus ion implantation region, 7 ... Photoresist film, 8 ... Activation Region, 9 ... polycrystalline silicon layer, 10 ...
… Inverted taper, 11… Constriction.

Claims (1)

(57) [Claims] A step of forming a non-doped polycrystalline silicon layer on an insulating film provided on a semiconductor substrate; and forming a patterned first photoresist film on the polycrystalline silicon layer. A step of implanting impurity ions into the surface of the polycrystalline silicon layer using a photoresist film as a mask to provide an impurity ion implantation region, and a pattern covering the surface of the impurity ion implantation region by removing the first photoresist film. Selectively providing a second photoresist film, anisotropically etching and removing the polycrystalline silicon layer using the second photoresist film as a mask to form an electrode having a required pattern, Performing impurity diffusion and activation of the electrode.